Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / arm / juno-motherboard.dtsi
1 /*
2  * ARM Juno Platform motherboard peripherals
3  *
4  * Copyright (c) 2013-2014 ARM Ltd
5  *
6  * This file is licensed under a dual GPLv2 or BSD license.
7  *
8  */
9
10                 mb_clk24mhz: clk24mhz {
11                         compatible = "fixed-clock";
12                         #clock-cells = <0>;
13                         clock-frequency = <24000000>;
14                         clock-output-names = "juno_mb:clk24mhz";
15                 };
16
17                 mb_clk25mhz: clk25mhz {
18                         compatible = "fixed-clock";
19                         #clock-cells = <0>;
20                         clock-frequency = <25000000>;
21                         clock-output-names = "juno_mb:clk25mhz";
22                 };
23
24                 v2m_refclk1mhz: refclk1mhz {
25                         compatible = "fixed-clock";
26                         #clock-cells = <0>;
27                         clock-frequency = <1000000>;
28                         clock-output-names = "juno_mb:refclk1mhz";
29                 };
30
31                 v2m_refclk32khz: refclk32khz {
32                         compatible = "fixed-clock";
33                         #clock-cells = <0>;
34                         clock-frequency = <32768>;
35                         clock-output-names = "juno_mb:refclk32khz";
36                 };
37
38                 motherboard {
39                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
40                         #address-cells = <2>;  /* SMB chipselect number and offset */
41                         #size-cells = <1>;
42                         #interrupt-cells = <1>;
43                         ranges;
44                         model = "V2M-Juno";
45                         arm,hbi = <0x252>;
46                         arm,vexpress,site = <0>;
47                         arm,v2m-memory-map = "rs1";
48
49                         mb_fixed_3v3: fixedregulator@0 {
50                                 compatible = "regulator-fixed";
51                                 regulator-name = "MCC_SB_3V3";
52                                 regulator-min-microvolt = <3300000>;
53                                 regulator-max-microvolt = <3300000>;
54                                 regulator-always-on;
55                         };
56
57                         ethernet@2,00000000 {
58                                 compatible = "smsc,lan9118", "smsc,lan9115";
59                                 reg = <2 0x00000000 0x10000>;
60                                 interrupts = <3>;
61                                 phy-mode = "mii";
62                                 reg-io-width = <4>;
63                                 smsc,irq-active-high;
64                                 smsc,irq-push-pull;
65                                 clocks = <&mb_clk25mhz>;
66                                 vdd33a-supply = <&mb_fixed_3v3>;
67                                 vddvario-supply = <&mb_fixed_3v3>;
68                         };
69
70                         usb@5,00000000 {
71                                 compatible = "nxp,usb-isp1763";
72                                 reg = <5 0x00000000 0x20000>;
73                                 bus-width = <16>;
74                                 interrupts = <4>;
75                         };
76
77                         iofpga@3,00000000 {
78                                 compatible = "arm,amba-bus", "simple-bus";
79                                 #address-cells = <1>;
80                                 #size-cells = <1>;
81                                 ranges = <0 3 0 0x200000>;
82
83                                 v2m_sysctl: sysctl@020000 {
84                                         compatible = "arm,sp810", "arm,primecell";
85                                         reg = <0x020000 0x1000>;
86                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
87                                         clock-names = "refclk", "timclk", "apb_pclk";
88                                         #clock-cells = <1>;
89                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
90                                 };
91
92                                 mmci@050000 {
93                                         compatible = "arm,pl180", "arm,primecell";
94                                         reg = <0x050000 0x1000>;
95                                         interrupts = <5>;
96                                         /* cd-gpios = <&v2m_mmc_gpios 0 0>;
97                                         wp-gpios = <&v2m_mmc_gpios 1 0>; */
98                                         max-frequency = <12000000>;
99                                         vmmc-supply = <&mb_fixed_3v3>;
100                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
101                                         clock-names = "mclk", "apb_pclk";
102                                 };
103
104                                 kmi@060000 {
105                                         compatible = "arm,pl050", "arm,primecell";
106                                         reg = <0x060000 0x1000>;
107                                         interrupts = <8>;
108                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
109                                         clock-names = "KMIREFCLK", "apb_pclk";
110                                 };
111
112                                 kmi@070000 {
113                                         compatible = "arm,pl050", "arm,primecell";
114                                         reg = <0x070000 0x1000>;
115                                         interrupts = <8>;
116                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
117                                         clock-names = "KMIREFCLK", "apb_pclk";
118                                 };
119
120                                 wdt@0f0000 {
121                                         compatible = "arm,sp805", "arm,primecell";
122                                         reg = <0x0f0000 0x10000>;
123                                         interrupts = <7>;
124                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
125                                         clock-names = "wdogclk", "apb_pclk";
126                                 };
127
128                                 v2m_timer01: timer@110000 {
129                                         compatible = "arm,sp804", "arm,primecell";
130                                         reg = <0x110000 0x10000>;
131                                         interrupts = <9>;
132                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
133                                         clock-names = "timclken1", "timclken2", "apb_pclk";
134                                 };
135
136                                 v2m_timer23: timer@120000 {
137                                         compatible = "arm,sp804", "arm,primecell";
138                                         reg = <0x120000 0x10000>;
139                                         interrupts = <9>;
140                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
141                                         clock-names = "timclken1", "timclken2", "apb_pclk";
142                                 };
143
144                                 rtc@170000 {
145                                         compatible = "arm,pl031", "arm,primecell";
146                                         reg = <0x170000 0x10000>;
147                                         interrupts = <0>;
148                                         clocks = <&soc_smc50mhz>;
149                                         clock-names = "apb_pclk";
150                                 };
151                         };
152                 };