arch/arm64/boot/dts/arm/juno-base.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "juno-clocks.dtsi"
   3
   4 / {
   5         /*
   6          *  Devices shared by all Juno boards
   7          */
   8         dma-ranges = <0 0 0 0 0x100 0>;
   9
  10         memtimer: timer@2a810000 {
  11                 compatible = "arm,armv7-timer-mem";
  12                 reg = <0x0 0x2a810000 0x0 0x10000>;
  13                 clock-frequency = <50000000>;
  14                 #address-cells = <2>;
  15                 #size-cells = <2>;
  16                 ranges;
  17                 status = "disabled";
  18                 frame@2a830000 {
  19                         frame-number = <1>;
  20                         interrupts = <0 60 4>;
  21                         reg = <0x0 0x2a830000 0x0 0x10000>;
  22                 };
  23         };
  24
  25         mailbox: mhu@2b1f0000 {
  26                 compatible = "arm,mhu", "arm,primecell";
  27                 reg = <0x0 0x2b1f0000 0x0 0x1000>;
  28                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  30                 interrupt-names = "mhu_lpri_rx",
  31                                   "mhu_hpri_rx";
  32                 #mbox-cells = <1>;
  33                 clocks = <&soc_refclk100mhz>;
  34                 clock-names = "apb_pclk";
  35         };
  36
  37         smmu_pcie: iommu@2b500000 {
  38                 compatible = "arm,mmu-401", "arm,smmu-v1";
  39                 reg = <0x0 0x2b500000 0x0 0x10000>;
  40                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  41                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  42                 #iommu-cells = <1>;
  43                 #global-interrupts = <1>;
  44                 dma-coherent;
  45                 status = "disabled";
  46         };
  47
  48         smmu_etr: iommu@2b600000 {
  49                 compatible = "arm,mmu-401", "arm,smmu-v1";
  50                 reg = <0x0 0x2b600000 0x0 0x10000>;
  51                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  52                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  53                 #iommu-cells = <1>;
  54                 #global-interrupts = <1>;
  55                 dma-coherent;
  56                 power-domains = <&scpi_devpd 0>;
  57         };
  58
  59         gic: interrupt-controller@2c010000 {
  60                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  61                 reg = <0x0 0x2c010000 0 0x1000>,
  62                       <0x0 0x2c02f000 0 0x2000>,
  63                       <0x0 0x2c04f000 0 0x2000>,
  64                       <0x0 0x2c06f000 0 0x2000>;
  65                 #address-cells = <2>;
  66                 #interrupt-cells = <3>;
  67                 #size-cells = <2>;
  68                 interrupt-controller;
  69                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  70                 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
  71                 v2m_0: v2m@0 {
  72                         compatible = "arm,gic-v2m-frame";
  73                         msi-controller;
  74                         reg = <0 0 0 0x1000>;
  75                 };
  76         };
  77
  78         timer {
  79                 compatible = "arm,armv8-timer";
  80                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  82                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
  84         };
  85
  86         /*
  87          * Juno TRMs specify the size for these coresight components as 64K.
  88          * The actual size is just 4K though 64K is reserved. Access to the
  89          * unmapped reserved region results in a DECERR response.
  90          */
  91         etf@20010000 { /* etf0 */
  92                 compatible = "arm,coresight-tmc", "arm,primecell";
  93                 reg = <0 0x20010000 0 0x1000>;
  94
  95                 clocks = <&soc_smc50mhz>;
  96                 clock-names = "apb_pclk";
  97                 power-domains = <&scpi_devpd 0>;
  98                 ports {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101
 102                         /* input port */
 103                         port@0 {
 104                                 reg = <0>;
 105                                 etf0_in_port: endpoint {
 106                                         slave-mode;
 107                                         remote-endpoint = <&main_funnel_out_port>;
 108                                 };
 109                         };
 110
 111                         /* output port */
 112                         port@1 {
 113                                 reg = <0>;
 114                                 etf0_out_port: endpoint {
 115                                 };
 116                         };
 117                 };
 118         };
 119
 120         tpiu@20030000 {
 121                 compatible = "arm,coresight-tpiu", "arm,primecell";
 122                 reg = <0 0x20030000 0 0x1000>;
 123
 124                 clocks = <&soc_smc50mhz>;
 125                 clock-names = "apb_pclk";
 126                 power-domains = <&scpi_devpd 0>;
 127                 port {
 128                         tpiu_in_port: endpoint {
 129                                 slave-mode;
 130                                 remote-endpoint = <&replicator_out_port0>;
 131                         };
 132                 };
 133         };
 134
 135         /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
 136         main_funnel: funnel@20040000 {
 137                 compatible = "arm,coresight-funnel", "arm,primecell";
 138                 reg = <0 0x20040000 0 0x1000>;
 139
 140                 clocks = <&soc_smc50mhz>;
 141                 clock-names = "apb_pclk";
 142                 power-domains = <&scpi_devpd 0>;
 143                 ports {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146
 147                         /* output port */
 148                         port@0 {
 149                                 reg = <0>;
 150                                 main_funnel_out_port: endpoint {
 151                                         remote-endpoint = <&etf0_in_port>;
 152                                 };
 153                         };
 154
 155                         /* input ports */
 156                         port@1 {
 157                                 reg = <0>;
 158                                 main_funnel_in_port0: endpoint {
 159                                         slave-mode;
 160                                         remote-endpoint = <&cluster0_funnel_out_port>;
 161                                 };
 162                         };
 163
 164                         port@2 {
 165                                 reg = <1>;
 166                                 main_funnel_in_port1: endpoint {
 167                                         slave-mode;
 168                                         remote-endpoint = <&cluster1_funnel_out_port>;
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         etr@20070000 {
 175                 compatible = "arm,coresight-tmc", "arm,primecell";
 176                 reg = <0 0x20070000 0 0x1000>;
 177                 iommus = <&smmu_etr 0>;
 178
 179                 clocks = <&soc_smc50mhz>;
 180                 clock-names = "apb_pclk";
 181                 power-domains = <&scpi_devpd 0>;
 182                 port {
 183                         etr_in_port: endpoint {
 184                                 slave-mode;
 185                                 remote-endpoint = <&replicator_out_port1>;
 186                         };
 187                 };
 188         };
 189
 190         stm@20100000 {
 191                 compatible = "arm,coresight-stm", "arm,primecell";
 192                 reg = <0 0x20100000 0 0x1000>,
 193                       <0 0x28000000 0 0x1000000>;
 194                 reg-names = "stm-base", "stm-stimulus-base";
 195
 196                 clocks = <&soc_smc50mhz>;
 197                 clock-names = "apb_pclk";
 198                 power-domains = <&scpi_devpd 0>;
 199                 port {
 200                         stm_out_port: endpoint {
 201                         };
 202                 };
 203         };
 204
 205         cpu_debug0: cpu-debug@22010000 {
 206                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 207                 reg = <0x0 0x22010000 0x0 0x1000>;
 208
 209                 clocks = <&soc_smc50mhz>;
 210                 clock-names = "apb_pclk";
 211                 power-domains = <&scpi_devpd 0>;
 212         };
 213
 214         etm0: etm@22040000 {
 215                 compatible = "arm,coresight-etm4x", "arm,primecell";
 216                 reg = <0 0x22040000 0 0x1000>;
 217
 218                 clocks = <&soc_smc50mhz>;
 219                 clock-names = "apb_pclk";
 220                 power-domains = <&scpi_devpd 0>;
 221                 port {
 222                         cluster0_etm0_out_port: endpoint {
 223                                 remote-endpoint = <&cluster0_funnel_in_port0>;
 224                         };
 225                 };
 226         };
 227
 228         funnel@220c0000 { /* cluster0 funnel */
 229                 compatible = "arm,coresight-funnel", "arm,primecell";
 230                 reg = <0 0x220c0000 0 0x1000>;
 231
 232                 clocks = <&soc_smc50mhz>;
 233                 clock-names = "apb_pclk";
 234                 power-domains = <&scpi_devpd 0>;
 235                 ports {
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238
 239                         port@0 {
 240                                 reg = <0>;
 241                                 cluster0_funnel_out_port: endpoint {
 242                                         remote-endpoint = <&main_funnel_in_port0>;
 243                                 };
 244                         };
 245
 246                         port@1 {
 247                                 reg = <0>;
 248                                 cluster0_funnel_in_port0: endpoint {
 249                                         slave-mode;
 250                                         remote-endpoint = <&cluster0_etm0_out_port>;
 251                                 };
 252                         };
 253
 254                         port@2 {
 255                                 reg = <1>;
 256                                 cluster0_funnel_in_port1: endpoint {
 257                                         slave-mode;
 258                                         remote-endpoint = <&cluster0_etm1_out_port>;
 259                                 };
 260                         };
 261                 };
 262         };
 263
 264         cpu_debug1: cpu-debug@22110000 {
 265                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 266                 reg = <0x0 0x22110000 0x0 0x1000>;
 267
 268                 clocks = <&soc_smc50mhz>;
 269                 clock-names = "apb_pclk";
 270                 power-domains = <&scpi_devpd 0>;
 271         };
 272
 273         etm1: etm@22140000 {
 274                 compatible = "arm,coresight-etm4x", "arm,primecell";
 275                 reg = <0 0x22140000 0 0x1000>;
 276
 277                 clocks = <&soc_smc50mhz>;
 278                 clock-names = "apb_pclk";
 279                 power-domains = <&scpi_devpd 0>;
 280                 port {
 281                         cluster0_etm1_out_port: endpoint {
 282                                 remote-endpoint = <&cluster0_funnel_in_port1>;
 283                         };
 284                 };
 285         };
 286
 287         cpu_debug2: cpu-debug@23010000 {
 288                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 289                 reg = <0x0 0x23010000 0x0 0x1000>;
 290
 291                 clocks = <&soc_smc50mhz>;
 292                 clock-names = "apb_pclk";
 293                 power-domains = <&scpi_devpd 0>;
 294         };
 295
 296         etm2: etm@23040000 {
 297                 compatible = "arm,coresight-etm4x", "arm,primecell";
 298                 reg = <0 0x23040000 0 0x1000>;
 299
 300                 clocks = <&soc_smc50mhz>;
 301                 clock-names = "apb_pclk";
 302                 power-domains = <&scpi_devpd 0>;
 303                 port {
 304                         cluster1_etm0_out_port: endpoint {
 305                                 remote-endpoint = <&cluster1_funnel_in_port0>;
 306                         };
 307                 };
 308         };
 309
 310         funnel@230c0000 { /* cluster1 funnel */
 311                 compatible = "arm,coresight-funnel", "arm,primecell";
 312                 reg = <0 0x230c0000 0 0x1000>;
 313
 314                 clocks = <&soc_smc50mhz>;
 315                 clock-names = "apb_pclk";
 316                 power-domains = <&scpi_devpd 0>;
 317                 ports {
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320
 321                         port@0 {
 322                                 reg = <0>;
 323                                 cluster1_funnel_out_port: endpoint {
 324                                         remote-endpoint = <&main_funnel_in_port1>;
 325                                 };
 326                         };
 327
 328                         port@1 {
 329                                 reg = <0>;
 330                                 cluster1_funnel_in_port0: endpoint {
 331                                         slave-mode;
 332                                         remote-endpoint = <&cluster1_etm0_out_port>;
 333                                 };
 334                         };
 335
 336                         port@2 {
 337                                 reg = <1>;
 338                                 cluster1_funnel_in_port1: endpoint {
 339                                         slave-mode;
 340                                         remote-endpoint = <&cluster1_etm1_out_port>;
 341                                 };
 342                         };
 343                         port@3 {
 344                                 reg = <2>;
 345                                 cluster1_funnel_in_port2: endpoint {
 346                                         slave-mode;
 347                                         remote-endpoint = <&cluster1_etm2_out_port>;
 348                                 };
 349                         };
 350                         port@4 {
 351                                 reg = <3>;
 352                                 cluster1_funnel_in_port3: endpoint {
 353                                         slave-mode;
 354                                         remote-endpoint = <&cluster1_etm3_out_port>;
 355                                 };
 356                         };
 357                 };
 358         };
 359
 360         cpu_debug3: cpu-debug@23110000 {
 361                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 362                 reg = <0x0 0x23110000 0x0 0x1000>;
 363
 364                 clocks = <&soc_smc50mhz>;
 365                 clock-names = "apb_pclk";
 366                 power-domains = <&scpi_devpd 0>;
 367         };
 368
 369         etm3: etm@23140000 {
 370                 compatible = "arm,coresight-etm4x", "arm,primecell";
 371                 reg = <0 0x23140000 0 0x1000>;
 372
 373                 clocks = <&soc_smc50mhz>;
 374                 clock-names = "apb_pclk";
 375                 power-domains = <&scpi_devpd 0>;
 376                 port {
 377                         cluster1_etm1_out_port: endpoint {
 378                                 remote-endpoint = <&cluster1_funnel_in_port1>;
 379                         };
 380                 };
 381         };
 382
 383         cpu_debug4: cpu-debug@23210000 {
 384                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 385                 reg = <0x0 0x23210000 0x0 0x1000>;
 386
 387                 clocks = <&soc_smc50mhz>;
 388                 clock-names = "apb_pclk";
 389                 power-domains = <&scpi_devpd 0>;
 390         };
 391
 392         etm4: etm@23240000 {
 393                 compatible = "arm,coresight-etm4x", "arm,primecell";
 394                 reg = <0 0x23240000 0 0x1000>;
 395
 396                 clocks = <&soc_smc50mhz>;
 397                 clock-names = "apb_pclk";
 398                 power-domains = <&scpi_devpd 0>;
 399                 port {
 400                         cluster1_etm2_out_port: endpoint {
 401                                 remote-endpoint = <&cluster1_funnel_in_port2>;
 402                         };
 403                 };
 404         };
 405
 406         cpu_debug5: cpu-debug@23310000 {
 407                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 408                 reg = <0x0 0x23310000 0x0 0x1000>;
 409
 410                 clocks = <&soc_smc50mhz>;
 411                 clock-names = "apb_pclk";
 412                 power-domains = <&scpi_devpd 0>;
 413         };
 414
 415         etm5: etm@23340000 {
 416                 compatible = "arm,coresight-etm4x", "arm,primecell";
 417                 reg = <0 0x23340000 0 0x1000>;
 418
 419                 clocks = <&soc_smc50mhz>;
 420                 clock-names = "apb_pclk";
 421                 power-domains = <&scpi_devpd 0>;
 422                 port {
 423                         cluster1_etm3_out_port: endpoint {
 424                                 remote-endpoint = <&cluster1_funnel_in_port3>;
 425                         };
 426                 };
 427         };
 428
 429         replicator@20120000 {
 430                 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 431                 reg = <0 0x20120000 0 0x1000>;
 432
 433                 clocks = <&soc_smc50mhz>;
 434                 clock-names = "apb_pclk";
 435                 power-domains = <&scpi_devpd 0>;
 436
 437                 ports {
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440
 441                         /* replicator output ports */
 442                         port@0 {
 443                                 reg = <0>;
 444                                 replicator_out_port0: endpoint {
 445                                         remote-endpoint = <&tpiu_in_port>;
 446                                 };
 447                         };
 448
 449                         port@1 {
 450                                 reg = <1>;
 451                                 replicator_out_port1: endpoint {
 452                                         remote-endpoint = <&etr_in_port>;
 453                                 };
 454                         };
 455
 456                         /* replicator input port */
 457                         port@2 {
 458                                 reg = <0>;
 459                                 replicator_in_port0: endpoint {
 460                                         slave-mode;
 461                                 };
 462                         };
 463                 };
 464         };
 465
 466         sram: sram@2e000000 {
 467                 compatible = "arm,juno-sram-ns", "mmio-sram";
 468                 reg = <0x0 0x2e000000 0x0 0x8000>;
 469
 470                 #address-cells = <1>;
 471                 #size-cells = <1>;
 472                 ranges = <0 0x0 0x2e000000 0x8000>;
 473
 474                 cpu_scp_lpri: scp-shmem@0 {
 475                         compatible = "arm,juno-scp-shmem";
 476                         reg = <0x0 0x200>;
 477                 };
 478
 479                 cpu_scp_hpri: scp-shmem@200 {
 480                         compatible = "arm,juno-scp-shmem";
 481                         reg = <0x200 0x200>;
 482                 };
 483         };
 484
 485         pcie_ctlr: pcie@40000000 {
 486                 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
 487                 device_type = "pci";
 488                 reg = <0 0x40000000 0 0x10000000>;      /* ECAM config space */
 489                 bus-range = <0 255>;
 490                 linux,pci-domain = <0>;
 491                 #address-cells = <3>;
 492                 #size-cells = <2>;
 493                 dma-coherent;
 494                 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 495                          <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 496                          <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 497                 #interrupt-cells = <1>;
 498                 interrupt-map-mask = <0 0 0 7>;
 499                 interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
 500                                 <0 0 0 2 &gic 0 0 0 137 4>,
 501                                 <0 0 0 3 &gic 0 0 0 138 4>,
 502                                 <0 0 0 4 &gic 0 0 0 139 4>;
 503                 msi-parent = <&v2m_0>;
 504                 status = "disabled";
 505                 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
 506                 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
 507         };
 508
 509         scpi {
 510                 compatible = "arm,scpi";
 511                 mboxes = <&mailbox 1>;
 512                 shmem = <&cpu_scp_hpri>;
 513
 514                 clocks {
 515                         compatible = "arm,scpi-clocks";
 516
 517                         scpi_dvfs: scpi-dvfs {
 518                                 compatible = "arm,scpi-dvfs-clocks";
 519                                 #clock-cells = <1>;
 520                                 clock-indices = <0>, <1>, <2>;
 521                                 clock-output-names = "atlclk", "aplclk","gpuclk";
 522                         };
 523                         scpi_clk: scpi-clk {
 524                                 compatible = "arm,scpi-variable-clocks";
 525                                 #clock-cells = <1>;
 526                                 clock-indices = <3>;
 527                                 clock-output-names = "pxlclk";
 528                         };
 529                 };
 530
 531                 scpi_devpd: scpi-power-domains {
 532                         compatible = "arm,scpi-power-domains";
 533                         num-domains = <2>;
 534                         #power-domain-cells = <1>;
 535                 };
 536
 537                 scpi_sensors0: sensors {
 538                         compatible = "arm,scpi-sensors";
 539                         #thermal-sensor-cells = <1>;
 540                 };
 541         };
 542
 543         thermal-zones {
 544                 pmic {
 545                         polling-delay = <1000>;
 546                         polling-delay-passive = <100>;
 547                         thermal-sensors = <&scpi_sensors0 0>;
 548                 };
 549
 550                 soc {
 551                         polling-delay = <1000>;
 552                         polling-delay-passive = <100>;
 553                         thermal-sensors = <&scpi_sensors0 3>;
 554                 };
 555
 556                 big_cluster_thermal_zone: big_cluster {
 557                         polling-delay = <1000>;
 558                         polling-delay-passive = <100>;
 559                         thermal-sensors = <&scpi_sensors0 21>;
 560                         status = "disabled";
 561                 };
 562
 563                 little_cluster_thermal_zone: little_cluster {
 564                         polling-delay = <1000>;
 565                         polling-delay-passive = <100>;
 566                         thermal-sensors = <&scpi_sensors0 22>;
 567                         status = "disabled";
 568                 };
 569
 570                 gpu0_thermal_zone: gpu0 {
 571                         polling-delay = <1000>;
 572                         polling-delay-passive = <100>;
 573                         thermal-sensors = <&scpi_sensors0 23>;
 574                         status = "disabled";
 575                 };
 576
 577                 gpu1_thermal_zone: gpu1 {
 578                         polling-delay = <1000>;
 579                         polling-delay-passive = <100>;
 580                         thermal-sensors = <&scpi_sensors0 24>;
 581                         status = "disabled";
 582                 };
 583         };
 584
 585         smmu_dma: iommu@7fb00000 {
 586                 compatible = "arm,mmu-401", "arm,smmu-v1";
 587                 reg = <0x0 0x7fb00000 0x0 0x10000>;
 588                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 589                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 590                 #iommu-cells = <1>;
 591                 #global-interrupts = <1>;
 592                 dma-coherent;
 593                 status = "disabled";
 594         };
 595
 596         smmu_hdlcd1: iommu@7fb10000 {
 597                 compatible = "arm,mmu-401", "arm,smmu-v1";
 598                 reg = <0x0 0x7fb10000 0x0 0x10000>;
 599                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 600                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 601                 #iommu-cells = <1>;
 602                 #global-interrupts = <1>;
 603         };
 604
 605         smmu_hdlcd0: iommu@7fb20000 {
 606                 compatible = "arm,mmu-401", "arm,smmu-v1";
 607                 reg = <0x0 0x7fb20000 0x0 0x10000>;
 608                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 609                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 610                 #iommu-cells = <1>;
 611                 #global-interrupts = <1>;
 612         };
 613
 614         smmu_usb: iommu@7fb30000 {
 615                 compatible = "arm,mmu-401", "arm,smmu-v1";
 616                 reg = <0x0 0x7fb30000 0x0 0x10000>;
 617                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 618                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 619                 #iommu-cells = <1>;
 620                 #global-interrupts = <1>;
 621                 dma-coherent;
 622         };
 623
 624         dma@7ff00000 {
 625                 compatible = "arm,pl330", "arm,primecell";
 626                 reg = <0x0 0x7ff00000 0 0x1000>;
 627                 #dma-cells = <1>;
 628                 #dma-channels = <8>;
 629                 #dma-requests = <32>;
 630                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 631                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 632                              <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 633                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 634                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 635                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 636                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 637                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 638                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 639                 iommus = <&smmu_dma 0>,
 640                          <&smmu_dma 1>,
 641                          <&smmu_dma 2>,
 642                          <&smmu_dma 3>,
 643                          <&smmu_dma 4>,
 644                          <&smmu_dma 5>,
 645                          <&smmu_dma 6>,
 646                          <&smmu_dma 7>,
 647                          <&smmu_dma 8>;
 648                 clocks = <&soc_faxiclk>;
 649                 clock-names = "apb_pclk";
 650         };
 651
 652         hdlcd@7ff50000 {
 653                 compatible = "arm,hdlcd";
 654                 reg = <0 0x7ff50000 0 0x1000>;
 655                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 656                 iommus = <&smmu_hdlcd1 0>;
 657                 clocks = <&scpi_clk 3>;
 658                 clock-names = "pxlclk";
 659
 660                 port {
 661                         hdlcd1_output: hdlcd1-endpoint {
 662                                 remote-endpoint = <&tda998x_1_input>;
 663                         };
 664                 };
 665         };
 666
 667         hdlcd@7ff60000 {
 668                 compatible = "arm,hdlcd";
 669                 reg = <0 0x7ff60000 0 0x1000>;
 670                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 671                 iommus = <&smmu_hdlcd0 0>;
 672                 clocks = <&scpi_clk 3>;
 673                 clock-names = "pxlclk";
 674
 675                 port {
 676                         hdlcd0_output: hdlcd0-endpoint {
 677                                 remote-endpoint = <&tda998x_0_input>;
 678                         };
 679                 };
 680         };
 681
 682         soc_uart0: uart@7ff80000 {
 683                 compatible = "arm,pl011", "arm,primecell";
 684                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 685                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 686                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 687                 clock-names = "uartclk", "apb_pclk";
 688         };
 689
 690         i2c@7ffa0000 {
 691                 compatible = "snps,designware-i2c";
 692                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 696                 clock-frequency = <400000>;
 697                 i2c-sda-hold-time-ns = <500>;
 698                 clocks = <&soc_smc50mhz>;
 699
 700                 hdmi-transmitter@70 {
 701                         compatible = "nxp,tda998x";
 702                         reg = <0x70>;
 703                         port {
 704                                 tda998x_0_input: tda998x-0-endpoint {
 705                                         remote-endpoint = <&hdlcd0_output>;
 706                                 };
 707                         };
 708                 };
 709
 710                 hdmi-transmitter@71 {
 711                         compatible = "nxp,tda998x";
 712                         reg = <0x71>;
 713                         port {
 714                                 tda998x_1_input: tda998x-1-endpoint {
 715                                         remote-endpoint = <&hdlcd1_output>;
 716                                 };
 717                         };
 718                 };
 719         };
 720
 721         ohci@7ffb0000 {
 722                 compatible = "generic-ohci";
 723                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 724                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 725                 iommus = <&smmu_usb 0>;
 726                 clocks = <&soc_usb48mhz>;
 727         };
 728
 729         ehci@7ffc0000 {
 730                 compatible = "generic-ehci";
 731                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 732                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 733                 iommus = <&smmu_usb 0>;
 734                 clocks = <&soc_usb48mhz>;
 735         };
 736
 737         memory-controller@7ffd0000 {
 738                 compatible = "arm,pl354", "arm,primecell";
 739                 reg = <0 0x7ffd0000 0 0x1000>;
 740                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 741                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 742                 clocks = <&soc_smc50mhz>;
 743                 clock-names = "apb_pclk";
 744         };
 745
 746         memory@80000000 {
 747                 device_type = "memory";
 748                 /* last 16MB of the first memory area is reserved for secure world use by firmware */
 749                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
 750                       <0x00000008 0x80000000 0x1 0x80000000>;
 751         };
 752
 753         smb@8000000 {
 754                 compatible = "simple-bus";
 755                 #address-cells = <2>;
 756                 #size-cells = <1>;
 757                 ranges = <0 0 0 0x08000000 0x04000000>,
 758                          <1 0 0 0x14000000 0x04000000>,
 759                          <2 0 0 0x18000000 0x04000000>,
 760                          <3 0 0 0x1c000000 0x04000000>,
 761                          <4 0 0 0x0c000000 0x04000000>,
 762                          <5 0 0 0x10000000 0x04000000>;
 763
 764                 #interrupt-cells = <1>;
 765                 interrupt-map-mask = <0 0 15>;
 766                 interrupt-map = <0 0  0 &gic 0 0 0  68 IRQ_TYPE_LEVEL_HIGH>,
 767                                 <0 0  1 &gic 0 0 0  69 IRQ_TYPE_LEVEL_HIGH>,
 768                                 <0 0  2 &gic 0 0 0  70 IRQ_TYPE_LEVEL_HIGH>,
 769                                 <0 0  3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
 770                                 <0 0  4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
 771                                 <0 0  5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
 772                                 <0 0  6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
 773                                 <0 0  7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
 774                                 <0 0  8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
 775                                 <0 0  9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
 776                                 <0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
 777                                 <0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
 778                                 <0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
 779
 780                 /include/ "juno-motherboard.dtsi"
 781         };
 782
 783         site2: tlx@60000000 {
 784                 compatible = "simple-bus";
 785                 #address-cells = <1>;
 786                 #size-cells = <1>;
 787                 ranges = <0 0 0x60000000 0x10000000>;
 788                 #interrupt-cells = <1>;
 789                 interrupt-map-mask = <0 0>;
 790                 interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
 791         };
 792 };