arch/arm64/boot/dts/arm/foundation-v8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd.
   4  *
   5  * ARMv8 Foundation model DTS
   6  */
   7
   8 /dts-v1/;
   9
  10 /memreserve/ 0x80000000 0x00010000;
  11
  12 / {
  13         model = "Foundation-v8A";
  14         compatible = "arm,foundation-aarch64", "arm,vexpress";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         aliases {
  22                 serial0 = &v2m_serial0;
  23                 serial1 = &v2m_serial1;
  24                 serial2 = &v2m_serial2;
  25                 serial3 = &v2m_serial3;
  26         };
  27
  28         cpus {
  29                 #address-cells = <2>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,armv8";
  35                         reg = <0x0 0x0>;
  36                         enable-method = "spin-table";
  37                         cpu-release-addr = <0x0 0x8000fff8>;
  38                         next-level-cache = <&L2_0>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,armv8";
  43                         reg = <0x0 0x1>;
  44                         enable-method = "spin-table";
  45                         cpu-release-addr = <0x0 0x8000fff8>;
  46                         next-level-cache = <&L2_0>;
  47                 };
  48                 cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,armv8";
  51                         reg = <0x0 0x2>;
  52                         enable-method = "spin-table";
  53                         cpu-release-addr = <0x0 0x8000fff8>;
  54                         next-level-cache = <&L2_0>;
  55                 };
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,armv8";
  59                         reg = <0x0 0x3>;
  60                         enable-method = "spin-table";
  61                         cpu-release-addr = <0x0 0x8000fff8>;
  62                         next-level-cache = <&L2_0>;
  63                 };
  64
  65                 L2_0: l2-cache0 {
  66                         compatible = "cache";
  67                 };
  68         };
  69
  70         memory@80000000 {
  71                 device_type = "memory";
  72                 reg = <0x00000000 0x80000000 0 0x80000000>,
  73                       <0x00000008 0x80000000 0 0x80000000>;
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv8-timer";
  78                 interrupts = <1 13 0xf08>,
  79                              <1 14 0xf08>,
  80                              <1 11 0xf08>,
  81                              <1 10 0xf08>;
  82                 clock-frequency = <100000000>;
  83         };
  84
  85         pmu {
  86                 compatible = "arm,armv8-pmuv3";
  87                 interrupts = <0 60 4>,
  88                              <0 61 4>,
  89                              <0 62 4>,
  90                              <0 63 4>;
  91         };
  92
  93         watchdog@2a440000 {
  94                 compatible = "arm,sbsa-gwdt";
  95                 reg = <0x0 0x2a440000 0 0x1000>,
  96                         <0x0 0x2a450000 0 0x1000>;
  97                 interrupts = <0 27 4>;
  98                 timeout-sec = <30>;
  99         };
 100
 101         smb@08000000 {
 102                 compatible = "arm,vexpress,v2m-p1", "simple-bus";
 103                 arm,v2m-memory-map = "rs1";
 104                 #address-cells = <2>; /* SMB chipselect number and offset */
 105                 #size-cells = <1>;
 106
 107                 ranges = <0 0 0 0x08000000 0x04000000>,
 108                          <1 0 0 0x14000000 0x04000000>,
 109                          <2 0 0 0x18000000 0x04000000>,
 110                          <3 0 0 0x1c000000 0x04000000>,
 111                          <4 0 0 0x0c000000 0x04000000>,
 112                          <5 0 0 0x10000000 0x04000000>;
 113
 114                 #interrupt-cells = <1>;
 115                 interrupt-map-mask = <0 0 63>;
 116                 interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
 117                                 <0 0  1 &gic 0 0 0  1 4>,
 118                                 <0 0  2 &gic 0 0 0  2 4>,
 119                                 <0 0  3 &gic 0 0 0  3 4>,
 120                                 <0 0  4 &gic 0 0 0  4 4>,
 121                                 <0 0  5 &gic 0 0 0  5 4>,
 122                                 <0 0  6 &gic 0 0 0  6 4>,
 123                                 <0 0  7 &gic 0 0 0  7 4>,
 124                                 <0 0  8 &gic 0 0 0  8 4>,
 125                                 <0 0  9 &gic 0 0 0  9 4>,
 126                                 <0 0 10 &gic 0 0 0 10 4>,
 127                                 <0 0 11 &gic 0 0 0 11 4>,
 128                                 <0 0 12 &gic 0 0 0 12 4>,
 129                                 <0 0 13 &gic 0 0 0 13 4>,
 130                                 <0 0 14 &gic 0 0 0 14 4>,
 131                                 <0 0 15 &gic 0 0 0 15 4>,
 132                                 <0 0 16 &gic 0 0 0 16 4>,
 133                                 <0 0 17 &gic 0 0 0 17 4>,
 134                                 <0 0 18 &gic 0 0 0 18 4>,
 135                                 <0 0 19 &gic 0 0 0 19 4>,
 136                                 <0 0 20 &gic 0 0 0 20 4>,
 137                                 <0 0 21 &gic 0 0 0 21 4>,
 138                                 <0 0 22 &gic 0 0 0 22 4>,
 139                                 <0 0 23 &gic 0 0 0 23 4>,
 140                                 <0 0 24 &gic 0 0 0 24 4>,
 141                                 <0 0 25 &gic 0 0 0 25 4>,
 142                                 <0 0 26 &gic 0 0 0 26 4>,
 143                                 <0 0 27 &gic 0 0 0 27 4>,
 144                                 <0 0 28 &gic 0 0 0 28 4>,
 145                                 <0 0 29 &gic 0 0 0 29 4>,
 146                                 <0 0 30 &gic 0 0 0 30 4>,
 147                                 <0 0 31 &gic 0 0 0 31 4>,
 148                                 <0 0 32 &gic 0 0 0 32 4>,
 149                                 <0 0 33 &gic 0 0 0 33 4>,
 150                                 <0 0 34 &gic 0 0 0 34 4>,
 151                                 <0 0 35 &gic 0 0 0 35 4>,
 152                                 <0 0 36 &gic 0 0 0 36 4>,
 153                                 <0 0 37 &gic 0 0 0 37 4>,
 154                                 <0 0 38 &gic 0 0 0 38 4>,
 155                                 <0 0 39 &gic 0 0 0 39 4>,
 156                                 <0 0 40 &gic 0 0 0 40 4>,
 157                                 <0 0 41 &gic 0 0 0 41 4>,
 158                                 <0 0 42 &gic 0 0 0 42 4>;
 159
 160                 ethernet@2,02000000 {
 161                         compatible = "smsc,lan91c111";
 162                         reg = <2 0x02000000 0x10000>;
 163                         interrupts = <15>;
 164                 };
 165
 166                 v2m_clk24mhz: clk24mhz {
 167                         compatible = "fixed-clock";
 168                         #clock-cells = <0>;
 169                         clock-frequency = <24000000>;
 170                         clock-output-names = "v2m:clk24mhz";
 171                 };
 172
 173                 v2m_refclk1mhz: refclk1mhz {
 174                         compatible = "fixed-clock";
 175                         #clock-cells = <0>;
 176                         clock-frequency = <1000000>;
 177                         clock-output-names = "v2m:refclk1mhz";
 178                 };
 179
 180                 v2m_refclk32khz: refclk32khz {
 181                         compatible = "fixed-clock";
 182                         #clock-cells = <0>;
 183                         clock-frequency = <32768>;
 184                         clock-output-names = "v2m:refclk32khz";
 185                 };
 186
 187                 iofpga@3,00000000 {
 188                         compatible = "simple-bus";
 189                         #address-cells = <1>;
 190                         #size-cells = <1>;
 191                         ranges = <0 3 0 0x200000>;
 192
 193                         v2m_sysreg: sysreg@010000 {
 194                                 compatible = "arm,vexpress-sysreg";
 195                                 reg = <0x010000 0x1000>;
 196                         };
 197
 198                         v2m_serial0: uart@090000 {
 199                                 compatible = "arm,pl011", "arm,primecell";
 200                                 reg = <0x090000 0x1000>;
 201                                 interrupts = <5>;
 202                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 203                                 clock-names = "uartclk", "apb_pclk";
 204                         };
 205
 206                         v2m_serial1: uart@0a0000 {
 207                                 compatible = "arm,pl011", "arm,primecell";
 208                                 reg = <0x0a0000 0x1000>;
 209                                 interrupts = <6>;
 210                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 211                                 clock-names = "uartclk", "apb_pclk";
 212                         };
 213
 214                         v2m_serial2: uart@0b0000 {
 215                                 compatible = "arm,pl011", "arm,primecell";
 216                                 reg = <0x0b0000 0x1000>;
 217                                 interrupts = <7>;
 218                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 219                                 clock-names = "uartclk", "apb_pclk";
 220                         };
 221
 222                         v2m_serial3: uart@0c0000 {
 223                                 compatible = "arm,pl011", "arm,primecell";
 224                                 reg = <0x0c0000 0x1000>;
 225                                 interrupts = <8>;
 226                                 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
 227                                 clock-names = "uartclk", "apb_pclk";
 228                         };
 229
 230                         virtio-block@0130000 {
 231                                 compatible = "virtio,mmio";
 232                                 reg = <0x130000 0x200>;
 233                                 interrupts = <42>;
 234                         };
 235                 };
 236         };
 237 };