arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                         next-level-cache = <&xgene_L2_0>;
  29                 };
  30                 cpu@001 {
  31                         device_type = "cpu";
  32                         compatible = "apm,potenza", "arm,armv8";
  33                         reg = <0x0 0x001>;
  34                         enable-method = "spin-table";
  35                         cpu-release-addr = <0x1 0x0000fff8>;
  36                         next-level-cache = <&xgene_L2_0>;
  37                 };
  38                 cpu@100 {
  39                         device_type = "cpu";
  40                         compatible = "apm,potenza", "arm,armv8";
  41                         reg = <0x0 0x100>;
  42                         enable-method = "spin-table";
  43                         cpu-release-addr = <0x1 0x0000fff8>;
  44                         next-level-cache = <&xgene_L2_1>;
  45                 };
  46                 cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "apm,potenza", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "spin-table";
  51                         cpu-release-addr = <0x1 0x0000fff8>;
  52                         next-level-cache = <&xgene_L2_1>;
  53                 };
  54                 cpu@200 {
  55                         device_type = "cpu";
  56                         compatible = "apm,potenza", "arm,armv8";
  57                         reg = <0x0 0x200>;
  58                         enable-method = "spin-table";
  59                         cpu-release-addr = <0x1 0x0000fff8>;
  60                         next-level-cache = <&xgene_L2_2>;
  61                 };
  62                 cpu@201 {
  63                         device_type = "cpu";
  64                         compatible = "apm,potenza", "arm,armv8";
  65                         reg = <0x0 0x201>;
  66                         enable-method = "spin-table";
  67                         cpu-release-addr = <0x1 0x0000fff8>;
  68                         next-level-cache = <&xgene_L2_2>;
  69                 };
  70                 cpu@300 {
  71                         device_type = "cpu";
  72                         compatible = "apm,potenza", "arm,armv8";
  73                         reg = <0x0 0x300>;
  74                         enable-method = "spin-table";
  75                         cpu-release-addr = <0x1 0x0000fff8>;
  76                         next-level-cache = <&xgene_L2_3>;
  77                 };
  78                 cpu@301 {
  79                         device_type = "cpu";
  80                         compatible = "apm,potenza", "arm,armv8";
  81                         reg = <0x0 0x301>;
  82                         enable-method = "spin-table";
  83                         cpu-release-addr = <0x1 0x0000fff8>;
  84                         next-level-cache = <&xgene_L2_3>;
  85                 };
  86                 xgene_L2_0: l2-cache-0 {
  87                         compatible = "cache";
  88                 };
  89                 xgene_L2_1: l2-cache-1 {
  90                         compatible = "cache";
  91                 };
  92                 xgene_L2_2: l2-cache-2 {
  93                         compatible = "cache";
  94                 };
  95                 xgene_L2_3: l2-cache-3 {
  96                         compatible = "cache";
  97                 };
  98         };
  99
 100         gic: interrupt-controller@78010000 {
 101                 compatible = "arm,cortex-a15-gic";
 102                 #interrupt-cells = <3>;
 103                 interrupt-controller;
 104                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
 105                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
 106                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
 107                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
 108                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupts = <1 0 0xff08>,      /* Secure Phys IRQ */
 114                              <1 13 0xff08>,     /* Non-secure Phys IRQ */
 115                              <1 14 0xff08>,     /* Virt IRQ */
 116                              <1 15 0xff08>;     /* Hyp IRQ */
 117                 clock-frequency = <50000000>;
 118         };
 119
 120         pmu {
 121                 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
 122                 interrupts = <1 12 0xff04>;
 123         };
 124
 125         soc {
 126                 compatible = "simple-bus";
 127                 #address-cells = <2>;
 128                 #size-cells = <2>;
 129                 ranges;
 130                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 131
 132                 clocks {
 133                         #address-cells = <2>;
 134                         #size-cells = <2>;
 135                         ranges;
 136                         refclk: refclk {
 137                                 compatible = "fixed-clock";
 138                                 #clock-cells = <1>;
 139                                 clock-frequency = <100000000>;
 140                                 clock-output-names = "refclk";
 141                         };
 142
 143                         pcppll: pcppll@17000100 {
 144                                 compatible = "apm,xgene-pcppll-clock";
 145                                 #clock-cells = <1>;
 146                                 clocks = <&refclk 0>;
 147                                 clock-names = "pcppll";
 148                                 reg = <0x0 0x17000100 0x0 0x1000>;
 149                                 clock-output-names = "pcppll";
 150                                 type = <0>;
 151                         };
 152
 153                         socpll: socpll@17000120 {
 154                                 compatible = "apm,xgene-socpll-clock";
 155                                 #clock-cells = <1>;
 156                                 clocks = <&refclk 0>;
 157                                 clock-names = "socpll";
 158                                 reg = <0x0 0x17000120 0x0 0x1000>;
 159                                 clock-output-names = "socpll";
 160                                 type = <1>;
 161                         };
 162
 163                         socplldiv2: socplldiv2  {
 164                                 compatible = "fixed-factor-clock";
 165                                 #clock-cells = <1>;
 166                                 clocks = <&socpll 0>;
 167                                 clock-names = "socplldiv2";
 168                                 clock-mult = <1>;
 169                                 clock-div = <2>;
 170                                 clock-output-names = "socplldiv2";
 171                         };
 172
 173                         ahbclk: ahbclk@17000000 {
 174                                 compatible = "apm,xgene-device-clock";
 175                                 #clock-cells = <1>;
 176                                 clocks = <&socplldiv2 0>;
 177                                 reg = <0x0 0x17000000 0x0 0x2000>;
 178                                 reg-names = "div-reg";
 179                                 divider-offset = <0x164>;
 180                                 divider-width = <0x5>;
 181                                 divider-shift = <0x0>;
 182                                 clock-output-names = "ahbclk";
 183                         };
 184
 185                         sdioclk: sdioclk@1f2ac000 {
 186                                 compatible = "apm,xgene-device-clock";
 187                                 #clock-cells = <1>;
 188                                 clocks = <&socplldiv2 0>;
 189                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 190                                         0x0 0x17000000 0x0 0x2000>;
 191                                 reg-names = "csr-reg", "div-reg";
 192                                 csr-offset = <0x0>;
 193                                 csr-mask = <0x2>;
 194                                 enable-offset = <0x8>;
 195                                 enable-mask = <0x2>;
 196                                 divider-offset = <0x178>;
 197                                 divider-width = <0x8>;
 198                                 divider-shift = <0x0>;
 199                                 clock-output-names = "sdioclk";
 200                         };
 201
 202                         ethclk: ethclk {
 203                                 compatible = "apm,xgene-device-clock";
 204                                 #clock-cells = <1>;
 205                                 clocks = <&socplldiv2 0>;
 206                                 clock-names = "ethclk";
 207                                 reg = <0x0 0x17000000 0x0 0x1000>;
 208                                 reg-names = "div-reg";
 209                                 divider-offset = <0x238>;
 210                                 divider-width = <0x9>;
 211                                 divider-shift = <0x0>;
 212                                 clock-output-names = "ethclk";
 213                         };
 214
 215                         menetclk: menetclk {
 216                                 compatible = "apm,xgene-device-clock";
 217                                 #clock-cells = <1>;
 218                                 clocks = <&ethclk 0>;
 219                                 reg = <0x0 0x1702c000 0x0 0x1000>;
 220                                 reg-names = "csr-reg";
 221                                 clock-output-names = "menetclk";
 222                         };
 223
 224                         sge0clk: sge0clk@1f21c000 {
 225                                 compatible = "apm,xgene-device-clock";
 226                                 #clock-cells = <1>;
 227                                 clocks = <&socplldiv2 0>;
 228                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 229                                 reg-names = "csr-reg";
 230                                 csr-mask = <0xa>;
 231                                 enable-mask = <0xf>;
 232                                 clock-output-names = "sge0clk";
 233                         };
 234
 235                         xge0clk: xge0clk@1f61c000 {
 236                                 compatible = "apm,xgene-device-clock";
 237                                 #clock-cells = <1>;
 238                                 clocks = <&socplldiv2 0>;
 239                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 240                                 reg-names = "csr-reg";
 241                                 csr-mask = <0x3>;
 242                                 clock-output-names = "xge0clk";
 243                         };
 244
 245                         xge1clk: xge1clk@1f62c000 {
 246                                 compatible = "apm,xgene-device-clock";
 247                                 status = "disabled";
 248                                 #clock-cells = <1>;
 249                                 clocks = <&socplldiv2 0>;
 250                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 251                                 reg-names = "csr-reg";
 252                                 csr-mask = <0x3>;
 253                                 clock-output-names = "xge1clk";
 254                         };
 255
 256                         sataphy1clk: sataphy1clk@1f21c000 {
 257                                 compatible = "apm,xgene-device-clock";
 258                                 #clock-cells = <1>;
 259                                 clocks = <&socplldiv2 0>;
 260                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 261                                 reg-names = "csr-reg";
 262                                 clock-output-names = "sataphy1clk";
 263                                 status = "disabled";
 264                                 csr-offset = <0x4>;
 265                                 csr-mask = <0x00>;
 266                                 enable-offset = <0x0>;
 267                                 enable-mask = <0x06>;
 268                         };
 269
 270                         sataphy2clk: sataphy1clk@1f22c000 {
 271                                 compatible = "apm,xgene-device-clock";
 272                                 #clock-cells = <1>;
 273                                 clocks = <&socplldiv2 0>;
 274                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 275                                 reg-names = "csr-reg";
 276                                 clock-output-names = "sataphy2clk";
 277                                 status = "ok";
 278                                 csr-offset = <0x4>;
 279                                 csr-mask = <0x3a>;
 280                                 enable-offset = <0x0>;
 281                                 enable-mask = <0x06>;
 282                         };
 283
 284                         sataphy3clk: sataphy1clk@1f23c000 {
 285                                 compatible = "apm,xgene-device-clock";
 286                                 #clock-cells = <1>;
 287                                 clocks = <&socplldiv2 0>;
 288                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 289                                 reg-names = "csr-reg";
 290                                 clock-output-names = "sataphy3clk";
 291                                 status = "ok";
 292                                 csr-offset = <0x4>;
 293                                 csr-mask = <0x3a>;
 294                                 enable-offset = <0x0>;
 295                                 enable-mask = <0x06>;
 296                         };
 297
 298                         sata01clk: sata01clk@1f21c000 {
 299                                 compatible = "apm,xgene-device-clock";
 300                                 #clock-cells = <1>;
 301                                 clocks = <&socplldiv2 0>;
 302                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 303                                 reg-names = "csr-reg";
 304                                 clock-output-names = "sata01clk";
 305                                 csr-offset = <0x4>;
 306                                 csr-mask = <0x05>;
 307                                 enable-offset = <0x0>;
 308                                 enable-mask = <0x39>;
 309                         };
 310
 311                         sata23clk: sata23clk@1f22c000 {
 312                                 compatible = "apm,xgene-device-clock";
 313                                 #clock-cells = <1>;
 314                                 clocks = <&socplldiv2 0>;
 315                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 316                                 reg-names = "csr-reg";
 317                                 clock-output-names = "sata23clk";
 318                                 csr-offset = <0x4>;
 319                                 csr-mask = <0x05>;
 320                                 enable-offset = <0x0>;
 321                                 enable-mask = <0x39>;
 322                         };
 323
 324                         sata45clk: sata45clk@1f23c000 {
 325                                 compatible = "apm,xgene-device-clock";
 326                                 #clock-cells = <1>;
 327                                 clocks = <&socplldiv2 0>;
 328                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 329                                 reg-names = "csr-reg";
 330                                 clock-output-names = "sata45clk";
 331                                 csr-offset = <0x4>;
 332                                 csr-mask = <0x05>;
 333                                 enable-offset = <0x0>;
 334                                 enable-mask = <0x39>;
 335                         };
 336
 337                         rtcclk: rtcclk@17000000 {
 338                                 compatible = "apm,xgene-device-clock";
 339                                 #clock-cells = <1>;
 340                                 clocks = <&socplldiv2 0>;
 341                                 reg = <0x0 0x17000000 0x0 0x2000>;
 342                                 reg-names = "csr-reg";
 343                                 csr-offset = <0xc>;
 344                                 csr-mask = <0x2>;
 345                                 enable-offset = <0x10>;
 346                                 enable-mask = <0x2>;
 347                                 clock-output-names = "rtcclk";
 348                         };
 349
 350                         rngpkaclk: rngpkaclk@17000000 {
 351                                 compatible = "apm,xgene-device-clock";
 352                                 #clock-cells = <1>;
 353                                 clocks = <&socplldiv2 0>;
 354                                 reg = <0x0 0x17000000 0x0 0x2000>;
 355                                 reg-names = "csr-reg";
 356                                 csr-offset = <0xc>;
 357                                 csr-mask = <0x10>;
 358                                 enable-offset = <0x10>;
 359                                 enable-mask = <0x10>;
 360                                 clock-output-names = "rngpkaclk";
 361                         };
 362
 363                         pcie0clk: pcie0clk@1f2bc000 {
 364                                 status = "disabled";
 365                                 compatible = "apm,xgene-device-clock";
 366                                 #clock-cells = <1>;
 367                                 clocks = <&socplldiv2 0>;
 368                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 369                                 reg-names = "csr-reg";
 370                                 clock-output-names = "pcie0clk";
 371                         };
 372
 373                         pcie1clk: pcie1clk@1f2cc000 {
 374                                 status = "disabled";
 375                                 compatible = "apm,xgene-device-clock";
 376                                 #clock-cells = <1>;
 377                                 clocks = <&socplldiv2 0>;
 378                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 379                                 reg-names = "csr-reg";
 380                                 clock-output-names = "pcie1clk";
 381                         };
 382
 383                         pcie2clk: pcie2clk@1f2dc000 {
 384                                 status = "disabled";
 385                                 compatible = "apm,xgene-device-clock";
 386                                 #clock-cells = <1>;
 387                                 clocks = <&socplldiv2 0>;
 388                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 389                                 reg-names = "csr-reg";
 390                                 clock-output-names = "pcie2clk";
 391                         };
 392
 393                         pcie3clk: pcie3clk@1f50c000 {
 394                                 status = "disabled";
 395                                 compatible = "apm,xgene-device-clock";
 396                                 #clock-cells = <1>;
 397                                 clocks = <&socplldiv2 0>;
 398                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 399                                 reg-names = "csr-reg";
 400                                 clock-output-names = "pcie3clk";
 401                         };
 402
 403                         pcie4clk: pcie4clk@1f51c000 {
 404                                 status = "disabled";
 405                                 compatible = "apm,xgene-device-clock";
 406                                 #clock-cells = <1>;
 407                                 clocks = <&socplldiv2 0>;
 408                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 409                                 reg-names = "csr-reg";
 410                                 clock-output-names = "pcie4clk";
 411                         };
 412
 413                         dmaclk: dmaclk@1f27c000 {
 414                                 compatible = "apm,xgene-device-clock";
 415                                 #clock-cells = <1>;
 416                                 clocks = <&socplldiv2 0>;
 417                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 418                                 reg-names = "csr-reg";
 419                                 clock-output-names = "dmaclk";
 420                         };
 421                 };
 422
 423                 msi: msi@79000000 {
 424                         compatible = "apm,xgene1-msi";
 425                         msi-controller;
 426                         reg = <0x00 0x79000000 0x0 0x900000>;
 427                         interrupts = <  0x0 0x10 0x4
 428                                         0x0 0x11 0x4
 429                                         0x0 0x12 0x4
 430                                         0x0 0x13 0x4
 431                                         0x0 0x14 0x4
 432                                         0x0 0x15 0x4
 433                                         0x0 0x16 0x4
 434                                         0x0 0x17 0x4
 435                                         0x0 0x18 0x4
 436                                         0x0 0x19 0x4
 437                                         0x0 0x1a 0x4
 438                                         0x0 0x1b 0x4
 439                                         0x0 0x1c 0x4
 440                                         0x0 0x1d 0x4
 441                                         0x0 0x1e 0x4
 442                                         0x0 0x1f 0x4>;
 443                 };
 444
 445                 scu: system-clk-controller@17000000 {
 446                         compatible = "apm,xgene-scu","syscon";
 447                         reg = <0x0 0x17000000 0x0 0x400>;
 448                 };
 449
 450                 reboot: reboot@17000014 {
 451                         compatible = "syscon-reboot";
 452                         regmap = <&scu>;
 453                         offset = <0x14>;
 454                         mask = <0x1>;
 455                 };
 456
 457                 csw: csw@7e200000 {
 458                         compatible = "apm,xgene-csw", "syscon";
 459                         reg = <0x0 0x7e200000 0x0 0x1000>;
 460                 };
 461
 462                 mcba: mcba@7e700000 {
 463                         compatible = "apm,xgene-mcb", "syscon";
 464                         reg = <0x0 0x7e700000 0x0 0x1000>;
 465                 };
 466
 467                 mcbb: mcbb@7e720000 {
 468                         compatible = "apm,xgene-mcb", "syscon";
 469                         reg = <0x0 0x7e720000 0x0 0x1000>;
 470                 };
 471
 472                 efuse: efuse@1054a000 {
 473                         compatible = "apm,xgene-efuse", "syscon";
 474                         reg = <0x0 0x1054a000 0x0 0x20>;
 475                 };
 476
 477                 rb: rb@7e000000 {
 478                         compatible = "apm,xgene-rb", "syscon";
 479                         reg = <0x0 0x7e000000 0x0 0x10>;
 480                 };
 481
 482                 edac@78800000 {
 483                         compatible = "apm,xgene-edac";
 484                         #address-cells = <2>;
 485                         #size-cells = <2>;
 486                         ranges;
 487                         regmap-csw = <&csw>;
 488                         regmap-mcba = <&mcba>;
 489                         regmap-mcbb = <&mcbb>;
 490                         regmap-efuse = <&efuse>;
 491                         regmap-rb = <&rb>;
 492                         reg = <0x0 0x78800000 0x0 0x100>;
 493                         interrupts = <0x0 0x20 0x4>,
 494                                      <0x0 0x21 0x4>,
 495                                      <0x0 0x27 0x4>;
 496
 497                         edacmc@7e800000 {
 498                                 compatible = "apm,xgene-edac-mc";
 499                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 500                                 memory-controller = <0>;
 501                         };
 502
 503                         edacmc@7e840000 {
 504                                 compatible = "apm,xgene-edac-mc";
 505                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 506                                 memory-controller = <1>;
 507                         };
 508
 509                         edacmc@7e880000 {
 510                                 compatible = "apm,xgene-edac-mc";
 511                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 512                                 memory-controller = <2>;
 513                         };
 514
 515                         edacmc@7e8c0000 {
 516                                 compatible = "apm,xgene-edac-mc";
 517                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 518                                 memory-controller = <3>;
 519                         };
 520
 521                         edacpmd@7c000000 {
 522                                 compatible = "apm,xgene-edac-pmd";
 523                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 524                                 pmd-controller = <0>;
 525                         };
 526
 527                         edacpmd@7c200000 {
 528                                 compatible = "apm,xgene-edac-pmd";
 529                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 530                                 pmd-controller = <1>;
 531                         };
 532
 533                         edacpmd@7c400000 {
 534                                 compatible = "apm,xgene-edac-pmd";
 535                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 536                                 pmd-controller = <2>;
 537                         };
 538
 539                         edacpmd@7c600000 {
 540                                 compatible = "apm,xgene-edac-pmd";
 541                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 542                                 pmd-controller = <3>;
 543                         };
 544
 545                         edacl3@7e600000 {
 546                                 compatible = "apm,xgene-edac-l3";
 547                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 548                         };
 549
 550                         edacsoc@7e930000 {
 551                                 compatible = "apm,xgene-edac-soc-v1";
 552                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 553                         };
 554                 };
 555
 556                 pcie0: pcie@1f2b0000 {
 557                         status = "disabled";
 558                         device_type = "pci";
 559                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 560                         #interrupt-cells = <1>;
 561                         #size-cells = <2>;
 562                         #address-cells = <3>;
 563                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 564                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 565                         reg-names = "csr", "cfg";
 566                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 567                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 568                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 569                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 570                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 571                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 572                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 573                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 574                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 575                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 576                         dma-coherent;
 577                         clocks = <&pcie0clk 0>;
 578                         msi-parent = <&msi>;
 579                 };
 580
 581                 pcie1: pcie@1f2c0000 {
 582                         status = "disabled";
 583                         device_type = "pci";
 584                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 585                         #interrupt-cells = <1>;
 586                         #size-cells = <2>;
 587                         #address-cells = <3>;
 588                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 589                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 590                         reg-names = "csr", "cfg";
 591                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 592                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 593                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 594                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 595                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 596                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 597                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 598                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 599                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 600                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 601                         dma-coherent;
 602                         clocks = <&pcie1clk 0>;
 603                         msi-parent = <&msi>;
 604                 };
 605
 606                 pcie2: pcie@1f2d0000 {
 607                         status = "disabled";
 608                         device_type = "pci";
 609                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 610                         #interrupt-cells = <1>;
 611                         #size-cells = <2>;
 612                         #address-cells = <3>;
 613                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 614                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 615                         reg-names = "csr", "cfg";
 616                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 617                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 618                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 619                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 620                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 621                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 622                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 623                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 624                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 625                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 626                         dma-coherent;
 627                         clocks = <&pcie2clk 0>;
 628                         msi-parent = <&msi>;
 629                 };
 630
 631                 pcie3: pcie@1f500000 {
 632                         status = "disabled";
 633                         device_type = "pci";
 634                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 635                         #interrupt-cells = <1>;
 636                         #size-cells = <2>;
 637                         #address-cells = <3>;
 638                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 639                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 640                         reg-names = "csr", "cfg";
 641                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 642                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 643                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 644                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 645                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 646                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 647                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 648                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 649                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 650                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 651                         dma-coherent;
 652                         clocks = <&pcie3clk 0>;
 653                         msi-parent = <&msi>;
 654                 };
 655
 656                 pcie4: pcie@1f510000 {
 657                         status = "disabled";
 658                         device_type = "pci";
 659                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 660                         #interrupt-cells = <1>;
 661                         #size-cells = <2>;
 662                         #address-cells = <3>;
 663                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 664                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 665                         reg-names = "csr", "cfg";
 666                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 667                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 668                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 669                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 670                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 671                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 672                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 673                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 674                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 675                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 676                         dma-coherent;
 677                         clocks = <&pcie4clk 0>;
 678                         msi-parent = <&msi>;
 679                 };
 680
 681                 mailbox: mailbox@10540000 {
 682                         compatible = "apm,xgene-slimpro-mbox";
 683                         reg = <0x0 0x10540000 0x0 0xa000>;
 684                         #mbox-cells = <1>;
 685                         interrupts =    <0x0 0x0 0x4>,
 686                                         <0x0 0x1 0x4>,
 687                                         <0x0 0x2 0x4>,
 688                                         <0x0 0x3 0x4>,
 689                                         <0x0 0x4 0x4>,
 690                                         <0x0 0x5 0x4>,
 691                                         <0x0 0x6 0x4>,
 692                                         <0x0 0x7 0x4>;
 693                 };
 694
 695                 i2cslimpro {
 696                         compatible = "apm,xgene-slimpro-i2c";
 697                         mboxes = <&mailbox 0>;
 698                 };
 699
 700                 serial0: serial@1c020000 {
 701                         status = "disabled";
 702                         device_type = "serial";
 703                         compatible = "ns16550a";
 704                         reg = <0 0x1c020000 0x0 0x1000>;
 705                         reg-shift = <2>;
 706                         clock-frequency = <10000000>; /* Updated by bootloader */
 707                         interrupt-parent = <&gic>;
 708                         interrupts = <0x0 0x4c 0x4>;
 709                 };
 710
 711                 serial1: serial@1c021000 {
 712                         status = "disabled";
 713                         device_type = "serial";
 714                         compatible = "ns16550a";
 715                         reg = <0 0x1c021000 0x0 0x1000>;
 716                         reg-shift = <2>;
 717                         clock-frequency = <10000000>; /* Updated by bootloader */
 718                         interrupt-parent = <&gic>;
 719                         interrupts = <0x0 0x4d 0x4>;
 720                 };
 721
 722                 serial2: serial@1c022000 {
 723                         status = "disabled";
 724                         device_type = "serial";
 725                         compatible = "ns16550a";
 726                         reg = <0 0x1c022000 0x0 0x1000>;
 727                         reg-shift = <2>;
 728                         clock-frequency = <10000000>; /* Updated by bootloader */
 729                         interrupt-parent = <&gic>;
 730                         interrupts = <0x0 0x4e 0x4>;
 731                 };
 732
 733                 serial3: serial@1c023000 {
 734                         status = "disabled";
 735                         device_type = "serial";
 736                         compatible = "ns16550a";
 737                         reg = <0 0x1c023000 0x0 0x1000>;
 738                         reg-shift = <2>;
 739                         clock-frequency = <10000000>; /* Updated by bootloader */
 740                         interrupt-parent = <&gic>;
 741                         interrupts = <0x0 0x4f 0x4>;
 742                 };
 743
 744                 mmc0: mmc@1c000000 {
 745                         compatible = "arasan,sdhci-4.9a";
 746                         reg = <0x0 0x1c000000 0x0 0x100>;
 747                         interrupts = <0x0 0x49 0x4>;
 748                         dma-coherent;
 749                         no-1-8-v;
 750                         clock-names = "clk_xin", "clk_ahb";
 751                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 752                 };
 753
 754                 gfcgpio: gpio0@1701c000 {
 755                         compatible = "apm,xgene-gpio";
 756                         reg = <0x0 0x1701c000 0x0 0x40>;
 757                         gpio-controller;
 758                         #gpio-cells = <2>;
 759                 };
 760
 761                 dwgpio: gpio@1c024000 {
 762                         compatible = "snps,dw-apb-gpio";
 763                         reg = <0x0 0x1c024000 0x0 0x1000>;
 764                         reg-io-width = <4>;
 765                         #address-cells = <1>;
 766                         #size-cells = <0>;
 767
 768                         porta: gpio-controller@0 {
 769                                 compatible = "snps,dw-apb-gpio-port";
 770                                 gpio-controller;
 771                                 snps,nr-gpios = <32>;
 772                                 reg = <0>;
 773                         };
 774                 };
 775
 776                 i2c0: i2c@10512000 {
 777                         status = "disabled";
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         compatible = "snps,designware-i2c";
 781                         reg = <0x0 0x10512000 0x0 0x1000>;
 782                         interrupts = <0 0x44 0x4>;
 783                         #clock-cells = <1>;
 784                         clocks = <&ahbclk 0>;
 785                         bus_num = <0>;
 786                 };
 787
 788                 phy1: phy@1f21a000 {
 789                         compatible = "apm,xgene-phy";
 790                         reg = <0x0 0x1f21a000 0x0 0x100>;
 791                         #phy-cells = <1>;
 792                         clocks = <&sataphy1clk 0>;
 793                         status = "disabled";
 794                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 795                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 796                 };
 797
 798                 phy2: phy@1f22a000 {
 799                         compatible = "apm,xgene-phy";
 800                         reg = <0x0 0x1f22a000 0x0 0x100>;
 801                         #phy-cells = <1>;
 802                         clocks = <&sataphy2clk 0>;
 803                         status = "ok";
 804                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 805                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 806                 };
 807
 808                 phy3: phy@1f23a000 {
 809                         compatible = "apm,xgene-phy";
 810                         reg = <0x0 0x1f23a000 0x0 0x100>;
 811                         #phy-cells = <1>;
 812                         clocks = <&sataphy3clk 0>;
 813                         status = "ok";
 814                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 815                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 816                 };
 817
 818                 sata1: sata@1a000000 {
 819                         compatible = "apm,xgene-ahci";
 820                         reg = <0x0 0x1a000000 0x0 0x1000>,
 821                               <0x0 0x1f210000 0x0 0x1000>,
 822                               <0x0 0x1f21d000 0x0 0x1000>,
 823                               <0x0 0x1f21e000 0x0 0x1000>,
 824                               <0x0 0x1f217000 0x0 0x1000>;
 825                         interrupts = <0x0 0x86 0x4>;
 826                         dma-coherent;
 827                         status = "disabled";
 828                         clocks = <&sata01clk 0>;
 829                         phys = <&phy1 0>;
 830                         phy-names = "sata-phy";
 831                 };
 832
 833                 sata2: sata@1a400000 {
 834                         compatible = "apm,xgene-ahci";
 835                         reg = <0x0 0x1a400000 0x0 0x1000>,
 836                               <0x0 0x1f220000 0x0 0x1000>,
 837                               <0x0 0x1f22d000 0x0 0x1000>,
 838                               <0x0 0x1f22e000 0x0 0x1000>,
 839                               <0x0 0x1f227000 0x0 0x1000>;
 840                         interrupts = <0x0 0x87 0x4>;
 841                         dma-coherent;
 842                         status = "ok";
 843                         clocks = <&sata23clk 0>;
 844                         phys = <&phy2 0>;
 845                         phy-names = "sata-phy";
 846                 };
 847
 848                 sata3: sata@1a800000 {
 849                         compatible = "apm,xgene-ahci";
 850                         reg = <0x0 0x1a800000 0x0 0x1000>,
 851                               <0x0 0x1f230000 0x0 0x1000>,
 852                               <0x0 0x1f23d000 0x0 0x1000>,
 853                               <0x0 0x1f23e000 0x0 0x1000>;
 854                         interrupts = <0x0 0x88 0x4>;
 855                         dma-coherent;
 856                         status = "ok";
 857                         clocks = <&sata45clk 0>;
 858                         phys = <&phy3 0>;
 859                         phy-names = "sata-phy";
 860                 };
 861
 862                 /* Do not change dwusb name, coded for backward compatibility */
 863                 usb0: dwusb@19000000 {
 864                         status = "disabled";
 865                         compatible = "snps,dwc3";
 866                         reg =  <0x0 0x19000000 0x0 0x100000>;
 867                         interrupts = <0x0 0x89 0x4>;
 868                         dma-coherent;
 869                         dr_mode = "host";
 870                 };
 871
 872                 usb1: dwusb@19800000 {
 873                         status = "disabled";
 874                         compatible = "snps,dwc3";
 875                         reg =  <0x0 0x19800000 0x0 0x100000>;
 876                         interrupts = <0x0 0x8a 0x4>;
 877                         dma-coherent;
 878                         dr_mode = "host";
 879                 };
 880
 881                 sbgpio: gpio@17001000{
 882                         compatible = "apm,xgene-gpio-sb";
 883                         reg = <0x0 0x17001000 0x0 0x400>;
 884                         #gpio-cells = <2>;
 885                         gpio-controller;
 886                         interrupts =    <0x0 0x28 0x1>,
 887                                         <0x0 0x29 0x1>,
 888                                         <0x0 0x2a 0x1>,
 889                                         <0x0 0x2b 0x1>,
 890                                         <0x0 0x2c 0x1>,
 891                                         <0x0 0x2d 0x1>;
 892                         interrupt-parent = <&gic>;
 893                         #interrupt-cells = <2>;
 894                         interrupt-controller;
 895                 };
 896
 897                 rtc: rtc@10510000 {
 898                         compatible = "apm,xgene-rtc";
 899                         reg = <0x0 0x10510000 0x0 0x400>;
 900                         interrupts = <0x0 0x46 0x4>;
 901                         #clock-cells = <1>;
 902                         clocks = <&rtcclk 0>;
 903                 };
 904
 905                 mdio: mdio@17020000 {
 906                         compatible = "apm,xgene-mdio-rgmii";
 907                         #address-cells = <1>;
 908                         #size-cells = <0>;
 909                         reg = <0x0 0x17020000 0x0 0xd100>;
 910                         clocks = <&menetclk 0>;
 911                 };
 912
 913                 menet: ethernet@17020000 {
 914                         compatible = "apm,xgene-enet";
 915                         status = "disabled";
 916                         reg = <0x0 0x17020000 0x0 0xd100>,
 917                               <0x0 0x17030000 0x0 0xc300>,
 918                               <0x0 0x10000000 0x0 0x200>;
 919                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 920                         interrupts = <0x0 0x3c 0x4>;
 921                         dma-coherent;
 922                         clocks = <&menetclk 0>;
 923                         /* mac address will be overwritten by the bootloader */
 924                         local-mac-address = [00 00 00 00 00 00];
 925                         phy-connection-type = "rgmii";
 926                         phy-handle = <&menetphy>,<&menet0phy>;
 927                         mdio {
 928                                 compatible = "apm,xgene-mdio";
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 menetphy: menetphy@3 {
 932                                         compatible = "ethernet-phy-id001c.c915";
 933                                         reg = <0x3>;
 934                                 };
 935
 936                         };
 937                 };
 938
 939                 sgenet0: ethernet@1f210000 {
 940                         compatible = "apm,xgene1-sgenet";
 941                         status = "disabled";
 942                         reg = <0x0 0x1f210000 0x0 0xd100>,
 943                               <0x0 0x1f200000 0x0 0xc300>,
 944                               <0x0 0x1b000000 0x0 0x200>;
 945                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 946                         interrupts = <0x0 0xa0 0x4>,
 947                                      <0x0 0xa1 0x4>;
 948                         dma-coherent;
 949                         clocks = <&sge0clk 0>;
 950                         local-mac-address = [00 00 00 00 00 00];
 951                         phy-connection-type = "sgmii";
 952                         phy-handle = <&sgenet0phy>;
 953                 };
 954
 955                 sgenet1: ethernet@1f210030 {
 956                         compatible = "apm,xgene1-sgenet";
 957                         status = "disabled";
 958                         reg = <0x0 0x1f210030 0x0 0xd100>,
 959                               <0x0 0x1f200000 0x0 0xc300>,
 960                               <0x0 0x1b000000 0x0 0x8000>;
 961                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 962                         interrupts = <0x0 0xac 0x4>,
 963                                      <0x0 0xad 0x4>;
 964                         port-id = <1>;
 965                         dma-coherent;
 966                         local-mac-address = [00 00 00 00 00 00];
 967                         phy-connection-type = "sgmii";
 968                         phy-handle = <&sgenet1phy>;
 969                 };
 970
 971                 xgenet: ethernet@1f610000 {
 972                         compatible = "apm,xgene1-xgenet";
 973                         status = "disabled";
 974                         reg = <0x0 0x1f610000 0x0 0xd100>,
 975                               <0x0 0x1f600000 0x0 0xc300>,
 976                               <0x0 0x18000000 0x0 0x200>;
 977                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 978                         interrupts = <0x0 0x60 0x4>,
 979                                      <0x0 0x61 0x4>,
 980                                      <0x0 0x62 0x4>,
 981                                      <0x0 0x63 0x4>,
 982                                      <0x0 0x64 0x4>,
 983                                      <0x0 0x65 0x4>,
 984                                      <0x0 0x66 0x4>,
 985                                      <0x0 0x67 0x4>;
 986                         channel = <0>;
 987                         dma-coherent;
 988                         clocks = <&xge0clk 0>;
 989                         /* mac address will be overwritten by the bootloader */
 990                         local-mac-address = [00 00 00 00 00 00];
 991                         phy-connection-type = "xgmii";
 992                 };
 993
 994                 xgenet1: ethernet@1f620000 {
 995                         compatible = "apm,xgene1-xgenet";
 996                         status = "disabled";
 997                         reg = <0x0 0x1f620000 0x0 0xd100>,
 998                               <0x0 0x1f600000 0x0 0xc300>,
 999                               <0x0 0x18000000 0x0 0x8000>;
1000                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1001                         interrupts = <0x0 0x6c 0x4>,
1002                                      <0x0 0x6d 0x4>;
1003                         port-id = <1>;
1004                         dma-coherent;
1005                         clocks = <&xge1clk 0>;
1006                         /* mac address will be overwritten by the bootloader */
1007                         local-mac-address = [00 00 00 00 00 00];
1008                         phy-connection-type = "xgmii";
1009                 };
1010
1011                 rng: rng@10520000 {
1012                         compatible = "apm,xgene-rng";
1013                         reg = <0x0 0x10520000 0x0 0x100>;
1014                         interrupts = <0x0 0x41 0x4>;
1015                         clocks = <&rngpkaclk 0>;
1016                 };
1017
1018                 dma: dma@1f270000 {
1019                         compatible = "apm,xgene-storm-dma";
1020                         device_type = "dma";
1021                         reg = <0x0 0x1f270000 0x0 0x10000>,
1022                               <0x0 0x1f200000 0x0 0x10000>,
1023                               <0x0 0x1b000000 0x0 0x400000>,
1024                               <0x0 0x1054a000 0x0 0x100>;
1025                         interrupts = <0x0 0x82 0x4>,
1026                                      <0x0 0xb8 0x4>,
1027                                      <0x0 0xb9 0x4>,
1028                                      <0x0 0xba 0x4>,
1029                                      <0x0 0xbb 0x4>;
1030                         dma-coherent;
1031                         clocks = <&dmaclk 0>;
1032                 };
1033         };
1034 };