arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

   1 /*
   2  * Copyright (c) 2016 Endless Computers, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "meson-gx.dtsi"
  45 #include <dt-bindings/clock/gxbb-clkc.h>
  46 #include <dt-bindings/clock/gxbb-aoclkc.h>
  47 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  49
  50 / {
  51         compatible = "amlogic,meson-gxl";
  52 };
  53
  54 &ethmac {
  55         reg = <0x0 0xc9410000 0x0 0x10000
  56                0x0 0xc8834540 0x0 0x4>;
  57
  58         clocks = <&clkc CLKID_ETH>,
  59                  <&clkc CLKID_FCLK_DIV2>,
  60                  <&clkc CLKID_MPLL2>;
  61         clock-names = "stmmaceth", "clkin0", "clkin1";
  62
  63         mdio0: mdio {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 compatible = "snps,dwmac-mdio";
  67         };
  68 };
  69
  70 &aobus {
  71         pinctrl_aobus: pinctrl@14 {
  72                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 gpio_ao: bank@14 {
  78                         reg = <0x0 0x00014 0x0 0x8>,
  79                               <0x0 0x0002c 0x0 0x4>,
  80                               <0x0 0x00024 0x0 0x8>;
  81                         reg-names = "mux", "pull", "gpio";
  82                         gpio-controller;
  83                         #gpio-cells = <2>;
  84                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
  85                 };
  86
  87                 uart_ao_a_pins: uart_ao_a {
  88                         mux {
  89                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
  90                                 function = "uart_ao";
  91                         };
  92                 };
  93
  94                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  95                         mux {
  96                                 groups = "uart_cts_ao_a",
  97                                        "uart_rts_ao_a";
  98                                 function = "uart_ao";
  99                         };
 100                 };
 101
 102                 uart_ao_b_pins: uart_ao_b {
 103                         mux {
 104                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 105                                 function = "uart_ao_b";
 106                         };
 107                 };
 108
 109                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 110                         mux {
 111                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 112                                 function = "uart_ao_b";
 113                         };
 114                 };
 115
 116                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 117                         mux {
 118                                 groups = "uart_cts_ao_b",
 119                                        "uart_rts_ao_b";
 120                                 function = "uart_ao_b";
 121                         };
 122                 };
 123
 124                 remote_input_ao_pins: remote_input_ao {
 125                         mux {
 126                                 groups = "remote_input_ao";
 127                                 function = "remote_input_ao";
 128                         };
 129                 };
 130
 131                 i2c_ao_pins: i2c_ao {
 132                         mux {
 133                                 groups = "i2c_sck_ao",
 134                                        "i2c_sda_ao";
 135                                 function = "i2c_ao";
 136                         };
 137                 };
 138
 139                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 140                         mux {
 141                                 groups = "pwm_ao_a_3";
 142                                 function = "pwm_ao_a";
 143                         };
 144                 };
 145
 146                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 147                         mux {
 148                                 groups = "pwm_ao_a_8";
 149                                 function = "pwm_ao_a";
 150                         };
 151                 };
 152
 153                 pwm_ao_b_pins: pwm_ao_b {
 154                         mux {
 155                                 groups = "pwm_ao_b";
 156                                 function = "pwm_ao_b";
 157                         };
 158                 };
 159
 160                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 161                         mux {
 162                                 groups = "pwm_ao_b_6";
 163                                 function = "pwm_ao_b";
 164                         };
 165                 };
 166
 167                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 168                         mux {
 169                                 groups = "i2s_out_ch23_ao";
 170                                 function = "i2s_out_ao";
 171                         };
 172                 };
 173
 174                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 175                         mux {
 176                                 groups = "i2s_out_ch45_ao";
 177                                 function = "i2s_out_ao";
 178                         };
 179                 };
 180
 181                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 182                         mux {
 183                                 groups = "spdif_out_ao_6";
 184                                 function = "spdif_out_ao";
 185                         };
 186                 };
 187
 188                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 189                         mux {
 190                                 groups = "spdif_out_ao_9";
 191                                 function = "spdif_out_ao";
 192                         };
 193                 };
 194
 195                 ao_cec_pins: ao_cec {
 196                         mux {
 197                                 groups = "ao_cec";
 198                                 function = "cec_ao";
 199                         };
 200                 };
 201
 202                 ee_cec_pins: ee_cec {
 203                         mux {
 204                                 groups = "ee_cec";
 205                                 function = "cec_ao";
 206                         };
 207                 };
 208         };
 209 };
 210
 211 &cec_AO {
 212         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 213         clock-names = "core";
 214 };
 215
 216 &clkc_AO {
 217         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 218 };
 219
 220 &hdmi_tx {
 221         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 222         resets = <&reset RESET_HDMITX_CAPB3>,
 223                  <&reset RESET_HDMI_SYSTEM_RESET>,
 224                  <&reset RESET_HDMI_TX>;
 225         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 226         clocks = <&clkc CLKID_HDMI_PCLK>,
 227                  <&clkc CLKID_CLK81>,
 228                  <&clkc CLKID_GCLK_VENCI_INT0>;
 229         clock-names = "isfr", "iahb", "venci";
 230 };
 231
 232 &hiubus {
 233         clkc: clock-controller@0 {
 234                 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
 235                 #clock-cells = <1>;
 236                 reg = <0x0 0x0 0x0 0x3db>;
 237         };
 238 };
 239
 240 &i2c_A {
 241         clocks = <&clkc CLKID_I2C>;
 242 };
 243
 244 &i2c_AO {
 245         clocks = <&clkc CLKID_AO_I2C>;
 246 };
 247
 248 &i2c_B {
 249         clocks = <&clkc CLKID_I2C>;
 250 };
 251
 252 &i2c_C {
 253         clocks = <&clkc CLKID_I2C>;
 254 };
 255
 256 &periphs {
 257         pinctrl_periphs: pinctrl@4b0 {
 258                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 259                 #address-cells = <2>;
 260                 #size-cells = <2>;
 261                 ranges;
 262
 263                 gpio: bank@4b0 {
 264                         reg = <0x0 0x004b0 0x0 0x28>,
 265                               <0x0 0x004e8 0x0 0x14>,
 266                               <0x0 0x00520 0x0 0x14>,
 267                               <0x0 0x00430 0x0 0x40>;
 268                         reg-names = "mux", "pull", "pull-enable", "gpio";
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271                         gpio-ranges = <&pinctrl_periphs 0 10 101>;
 272                 };
 273
 274                 emmc_pins: emmc {
 275                         mux {
 276                                 groups = "emmc_nand_d07",
 277                                        "emmc_cmd",
 278                                        "emmc_clk",
 279                                        "emmc_ds";
 280                                 function = "emmc";
 281                         };
 282                 };
 283
 284                 emmc_clk_gate_pins: emmc_clk_gate {
 285                         mux {
 286                                 groups = "BOOT_8";
 287                                 function = "gpio_periphs";
 288                         };
 289                         cfg-pull-down {
 290                                 pins = "BOOT_8";
 291                                 bias-pull-down;
 292                         };
 293                 };
 294
 295                 nor_pins: nor {
 296                         mux {
 297                                 groups = "nor_d",
 298                                        "nor_q",
 299                                        "nor_c",
 300                                        "nor_cs";
 301                                 function = "nor";
 302                         };
 303                 };
 304
 305                 spi_pins: spi {
 306                         mux {
 307                                 groups = "spi_miso",
 308                                         "spi_mosi",
 309                                         "spi_sclk";
 310                                 function = "spi";
 311                         };
 312                 };
 313
 314                 spi_ss0_pins: spi-ss0 {
 315                         mux {
 316                                 groups = "spi_ss0";
 317                                 function = "spi";
 318                         };
 319                 };
 320
 321                 sdcard_pins: sdcard {
 322                         mux {
 323                                 groups = "sdcard_d0",
 324                                        "sdcard_d1",
 325                                        "sdcard_d2",
 326                                        "sdcard_d3",
 327                                        "sdcard_cmd",
 328                                        "sdcard_clk";
 329                                 function = "sdcard";
 330                         };
 331                 };
 332
 333                 sdcard_clk_gate_pins: sdcard_clk_gate {
 334                         mux {
 335                                 groups = "CARD_2";
 336                                 function = "gpio_periphs";
 337                         };
 338                         cfg-pull-down {
 339                                 pins = "CARD_2";
 340                                 bias-pull-down;
 341                         };
 342                 };
 343
 344                 sdio_pins: sdio {
 345                         mux {
 346                                 groups = "sdio_d0",
 347                                        "sdio_d1",
 348                                        "sdio_d2",
 349                                        "sdio_d3",
 350                                        "sdio_cmd",
 351                                        "sdio_clk";
 352                                 function = "sdio";
 353                         };
 354                 };
 355
 356                 sdio_clk_gate_pins: sdio_clk_gate {
 357                         mux {
 358                                 groups = "GPIOX_4";
 359                                 function = "gpio_periphs";
 360                         };
 361                         cfg-pull-down {
 362                                 pins = "GPIOX_4";
 363                                 bias-pull-down;
 364                         };
 365                 };
 366
 367                 sdio_irq_pins: sdio_irq {
 368                         mux {
 369                                 groups = "sdio_irq";
 370                                 function = "sdio";
 371                         };
 372                 };
 373
 374                 uart_a_pins: uart_a {
 375                         mux {
 376                                 groups = "uart_tx_a",
 377                                        "uart_rx_a";
 378                                 function = "uart_a";
 379                         };
 380                 };
 381
 382                 uart_a_cts_rts_pins: uart_a_cts_rts {
 383                         mux {
 384                                 groups = "uart_cts_a",
 385                                        "uart_rts_a";
 386                                 function = "uart_a";
 387                         };
 388                 };
 389
 390                 uart_b_pins: uart_b {
 391                         mux {
 392                                 groups = "uart_tx_b",
 393                                        "uart_rx_b";
 394                                 function = "uart_b";
 395                         };
 396                 };
 397
 398                 uart_b_cts_rts_pins: uart_b_cts_rts {
 399                         mux {
 400                                 groups = "uart_cts_b",
 401                                        "uart_rts_b";
 402                                 function = "uart_b";
 403                         };
 404                 };
 405
 406                 uart_c_pins: uart_c {
 407                         mux {
 408                                 groups = "uart_tx_c",
 409                                        "uart_rx_c";
 410                                 function = "uart_c";
 411                         };
 412                 };
 413
 414                 uart_c_cts_rts_pins: uart_c_cts_rts {
 415                         mux {
 416                                 groups = "uart_cts_c",
 417                                        "uart_rts_c";
 418                                 function = "uart_c";
 419                         };
 420                 };
 421
 422                 i2c_a_pins: i2c_a {
 423                         mux {
 424                                 groups = "i2c_sck_a",
 425                                      "i2c_sda_a";
 426                                 function = "i2c_a";
 427                         };
 428                 };
 429
 430                 i2c_b_pins: i2c_b {
 431                         mux {
 432                                 groups = "i2c_sck_b",
 433                                       "i2c_sda_b";
 434                                 function = "i2c_b";
 435                         };
 436                 };
 437
 438                 i2c_c_pins: i2c_c {
 439                         mux {
 440                                 groups = "i2c_sck_c",
 441                                       "i2c_sda_c";
 442                                 function = "i2c_c";
 443                         };
 444                 };
 445
 446                 eth_pins: eth_c {
 447                         mux {
 448                                 groups = "eth_mdio",
 449                                        "eth_mdc",
 450                                        "eth_clk_rx_clk",
 451                                        "eth_rx_dv",
 452                                        "eth_rxd0",
 453                                        "eth_rxd1",
 454                                        "eth_rxd2",
 455                                        "eth_rxd3",
 456                                        "eth_rgmii_tx_clk",
 457                                        "eth_tx_en",
 458                                        "eth_txd0",
 459                                        "eth_txd1",
 460                                        "eth_txd2",
 461                                        "eth_txd3";
 462                                 function = "eth";
 463                         };
 464                 };
 465
 466                 eth_link_led_pins: eth_link_led {
 467                         mux {
 468                                 groups = "eth_link_led";
 469                                 function = "eth_led";
 470                         };
 471                 };
 472
 473                 eth_act_led_pins: eth_act_led {
 474                         mux {
 475                                 groups = "eth_act_led";
 476                                 function = "eth_led";
 477                         };
 478                 };
 479
 480                 pwm_a_pins: pwm_a {
 481                         mux {
 482                                 groups = "pwm_a";
 483                                 function = "pwm_a";
 484                         };
 485                 };
 486
 487                 pwm_b_pins: pwm_b {
 488                         mux {
 489                                 groups = "pwm_b";
 490                                 function = "pwm_b";
 491                         };
 492                 };
 493
 494                 pwm_c_pins: pwm_c {
 495                         mux {
 496                                 groups = "pwm_c";
 497                                 function = "pwm_c";
 498                         };
 499                 };
 500
 501                 pwm_d_pins: pwm_d {
 502                         mux {
 503                                 groups = "pwm_d";
 504                                 function = "pwm_d";
 505                         };
 506                 };
 507
 508                 pwm_e_pins: pwm_e {
 509                         mux {
 510                                 groups = "pwm_e";
 511                                 function = "pwm_e";
 512                         };
 513                 };
 514
 515                 pwm_f_clk_pins: pwm_f_clk {
 516                         mux {
 517                                 groups = "pwm_f_clk";
 518                                 function = "pwm_f";
 519                         };
 520                 };
 521
 522                 pwm_f_x_pins: pwm_f_x {
 523                         mux {
 524                                 groups = "pwm_f_x";
 525                                 function = "pwm_f";
 526                         };
 527                 };
 528
 529                 hdmi_hpd_pins: hdmi_hpd {
 530                         mux {
 531                                 groups = "hdmi_hpd";
 532                                 function = "hdmi_hpd";
 533                         };
 534                 };
 535
 536                 hdmi_i2c_pins: hdmi_i2c {
 537                         mux {
 538                                 groups = "hdmi_sda", "hdmi_scl";
 539                                 function = "hdmi_i2c";
 540                         };
 541                 };
 542
 543                 i2s_am_clk_pins: i2s_am_clk {
 544                         mux {
 545                                 groups = "i2s_am_clk";
 546                                 function = "i2s_out";
 547                         };
 548                 };
 549
 550                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 551                         mux {
 552                                 groups = "i2s_out_ao_clk";
 553                                 function = "i2s_out";
 554                         };
 555                 };
 556
 557                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 558                         mux {
 559                                 groups = "i2s_out_lr_clk";
 560                                 function = "i2s_out";
 561                         };
 562                 };
 563
 564                 i2s_out_ch01_pins: i2s_out_ch01 {
 565                         mux {
 566                                 groups = "i2s_out_ch01";
 567                                 function = "i2s_out";
 568                         };
 569                 };
 570                 i2sout_ch23_z_pins: i2sout_ch23_z {
 571                         mux {
 572                                 groups = "i2sout_ch23_z";
 573                                 function = "i2s_out";
 574                         };
 575                 };
 576
 577                 i2sout_ch45_z_pins: i2sout_ch45_z {
 578                         mux {
 579                                 groups = "i2sout_ch45_z";
 580                                 function = "i2s_out";
 581                         };
 582                 };
 583
 584                 i2sout_ch67_z_pins: i2sout_ch67_z {
 585                         mux {
 586                                 groups = "i2sout_ch67_z";
 587                                 function = "i2s_out";
 588                         };
 589                 };
 590
 591                 spdif_out_h_pins: spdif_out_ao_h {
 592                         mux {
 593                                 groups = "spdif_out_h";
 594                                 function = "spdif_out";
 595                         };
 596                 };
 597         };
 598
 599         eth-phy-mux {
 600                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 reg = <0x0 0x55c 0x0 0x4>;
 604                 mux-mask = <0xffffffff>;
 605                 mdio-parent-bus = <&mdio0>;
 606
 607                 internal_mdio: mdio@e40908ff {
 608                         reg = <0xe40908ff>;
 609                         #address-cells = <1>;
 610                         #size-cells = <0>;
 611
 612                         internal_phy: ethernet-phy@8 {
 613                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 614                                 reg = <8>;
 615                                 max-speed = <100>;
 616                         };
 617                 };
 618
 619                 external_mdio: mdio@2009087f {
 620                         reg = <0x2009087f>;
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                 };
 624         };
 625 };
 626
 627 &saradc {
 628         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 629         clocks = <&xtal>,
 630                  <&clkc CLKID_SAR_ADC>,
 631                  <&clkc CLKID_SANA>,
 632                  <&clkc CLKID_SAR_ADC_CLK>,
 633                  <&clkc CLKID_SAR_ADC_SEL>;
 634         clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
 635 };
 636
 637 &sd_emmc_a {
 638         clocks = <&clkc CLKID_SD_EMMC_A>,
 639                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 640                  <&clkc CLKID_FCLK_DIV2>;
 641         clock-names = "core", "clkin0", "clkin1";
 642 };
 643
 644 &sd_emmc_b {
 645         clocks = <&clkc CLKID_SD_EMMC_B>,
 646                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 647                  <&clkc CLKID_FCLK_DIV2>;
 648        clock-names = "core", "clkin0", "clkin1";
 649 };
 650
 651 &sd_emmc_c {
 652         clocks = <&clkc CLKID_SD_EMMC_C>,
 653                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 654                  <&clkc CLKID_FCLK_DIV2>;
 655         clock-names = "core", "clkin0", "clkin1";
 656 };
 657
 658 &spicc {
 659         clocks = <&clkc CLKID_SPICC>;
 660         clock-names = "core";
 661         resets = <&reset RESET_PERIPHS_SPICC>;
 662         num-cs = <1>;
 663 };
 664
 665 &spifc {
 666         clocks = <&clkc CLKID_SPI>;
 667 };
 668
 669 &uart_A {
 670         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 671         clock-names = "xtal", "core", "baud";
 672 };
 673
 674 &uart_AO {
 675         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 676         clock-names = "xtal", "pclk", "baud";
 677 };
 678
 679 &uart_AO_B {
 680         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 681         clock-names = "xtal", "pclk", "baud";
 682 };
 683
 684 &uart_B {
 685         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 686         clock-names = "xtal", "core", "baud";
 687 };
 688
 689 &uart_C {
 690         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 691         clock-names = "xtal", "core", "baud";
 692 };
 693
 694 &vpu {
 695         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 696 };