arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
   6  */
   7
   8 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
   9
  10 / {
  11         vddcpu_a: regulator-vddcpu-a {
  12                 /*
  13                  * MP8756GD Regulator.
  14                  */
  15                 compatible = "pwm-regulator";
  16
  17                 regulator-name = "VDDCPU_A";
  18                 regulator-min-microvolt = <690000>;
  19                 regulator-max-microvolt = <1050000>;
  20
  21                 vin-supply = <&dc_in>;
  22
  23                 pwms = <&pwm_ab 0 1250 0>;
  24                 pwm-dutycycle-range = <100 0>;
  25
  26                 regulator-boot-on;
  27                 regulator-always-on;
  28         };
  29
  30         vddcpu_b: regulator-vddcpu-b {
  31                 /*
  32                  * Silergy SY8030DEC Regulator.
  33                  */
  34                 compatible = "pwm-regulator";
  35
  36                 regulator-name = "VDDCPU_B";
  37                 regulator-min-microvolt = <690000>;
  38                 regulator-max-microvolt = <1050000>;
  39
  40                 vin-supply = <&vsys_3v3>;
  41
  42                 pwms = <&pwm_AO_cd 1 1250 0>;
  43                 pwm-dutycycle-range = <100 0>;
  44
  45                 regulator-boot-on;
  46                 regulator-always-on;
  47         };
  48
  49         sound {
  50                 compatible = "amlogic,axg-sound-card";
  51                 model = "G12A-KHADAS-VIM3";
  52                 audio-aux-devs = <&tdmout_b>;
  53                 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
  54                                 "TDMOUT_B IN 1", "FRDDR_B OUT 1",
  55                                 "TDMOUT_B IN 2", "FRDDR_C OUT 1",
  56                                 "TDM_B Playback", "TDMOUT_B OUT";
  57
  58                 assigned-clocks = <&clkc CLKID_MPLL2>,
  59                                   <&clkc CLKID_MPLL0>,
  60                                   <&clkc CLKID_MPLL1>;
  61                 assigned-clock-parents = <0>, <0>, <0>;
  62                 assigned-clock-rates = <294912000>,
  63                                        <270950400>,
  64                                        <393216000>;
  65                 status = "okay";
  66
  67                 dai-link-0 {
  68                         sound-dai = <&frddr_a>;
  69                 };
  70
  71                 dai-link-1 {
  72                         sound-dai = <&frddr_b>;
  73                 };
  74
  75                 dai-link-2 {
  76                         sound-dai = <&frddr_c>;
  77                 };
  78
  79                 /* 8ch hdmi interface */
  80                 dai-link-3 {
  81                         sound-dai = <&tdmif_b>;
  82                         dai-format = "i2s";
  83                         dai-tdm-slot-tx-mask-0 = <1 1>;
  84                         dai-tdm-slot-tx-mask-1 = <1 1>;
  85                         dai-tdm-slot-tx-mask-2 = <1 1>;
  86                         dai-tdm-slot-tx-mask-3 = <1 1>;
  87                         mclk-fs = <256>;
  88
  89                         codec {
  90                                 sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
  91                         };
  92                 };
  93
  94                 /* hdmi glue */
  95                 dai-link-4 {
  96                         sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
  97
  98                         codec {
  99                                 sound-dai = <&hdmi_tx>;
 100                         };
 101                 };
 102         };
 103 };
 104
 105 &arb {
 106         status = "okay";
 107 };
 108
 109 &clkc_audio {
 110         status = "okay";
 111 };
 112
 113 &cpu0 {
 114         cpu-supply = <&vddcpu_b>;
 115         operating-points-v2 = <&cpu_opp_table_0>;
 116         clocks = <&clkc CLKID_CPU_CLK>;
 117         clock-latency = <50000>;
 118 };
 119
 120 &cpu1 {
 121         cpu-supply = <&vddcpu_b>;
 122         operating-points-v2 = <&cpu_opp_table_0>;
 123         clocks = <&clkc CLKID_CPU_CLK>;
 124         clock-latency = <50000>;
 125 };
 126
 127 &cpu100 {
 128         cpu-supply = <&vddcpu_a>;
 129         operating-points-v2 = <&cpub_opp_table_1>;
 130         clocks = <&clkc CLKID_CPUB_CLK>;
 131         clock-latency = <50000>;
 132 };
 133
 134 &cpu101 {
 135         cpu-supply = <&vddcpu_a>;
 136         operating-points-v2 = <&cpub_opp_table_1>;
 137         clocks = <&clkc CLKID_CPUB_CLK>;
 138         clock-latency = <50000>;
 139 };
 140
 141 &cpu102 {
 142         cpu-supply = <&vddcpu_a>;
 143         operating-points-v2 = <&cpub_opp_table_1>;
 144         clocks = <&clkc CLKID_CPUB_CLK>;
 145         clock-latency = <50000>;
 146 };
 147
 148 &cpu103 {
 149         cpu-supply = <&vddcpu_a>;
 150         operating-points-v2 = <&cpub_opp_table_1>;
 151         clocks = <&clkc CLKID_CPUB_CLK>;
 152         clock-latency = <50000>;
 153 };
 154
 155 &frddr_b {
 156         status = "okay";
 157 };
 158
 159 &frddr_c {
 160         status = "okay";
 161 };
 162
 163 &pwm_ab {
 164         pinctrl-0 = <&pwm_a_e_pins>;
 165         pinctrl-names = "default";
 166         clocks = <&xtal>;
 167         clock-names = "clkin0";
 168         status = "okay";
 169 };
 170
 171 &pwm_AO_cd {
 172         pinctrl-0 = <&pwm_ao_d_e_pins>;
 173         pinctrl-names = "default";
 174         clocks = <&xtal>;
 175         clock-names = "clkin1";
 176         status = "okay";
 177 };
 178
 179 &tdmif_b {
 180         status = "okay";
 181 };
 182
 183 &tdmout_b {
 184         status = "okay";
 185 };
 186
 187 &tohdmitx {
 188         status = "okay";
 189 };