arch/arm64/boot/dts/amlogic/meson-g12a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "amlogic,g12a";
  12
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <0x2>;
  19                 #size-cells = <0x0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53", "arm,armv8";
  24                         reg = <0x0 0x0>;
  25                         enable-method = "psci";
  26                         next-level-cache = <&l2>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a53", "arm,armv8";
  32                         reg = <0x0 0x1>;
  33                         enable-method = "psci";
  34                         next-level-cache = <&l2>;
  35                 };
  36
  37                 cpu2: cpu@2 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         reg = <0x0 0x2>;
  41                         enable-method = "psci";
  42                         next-level-cache = <&l2>;
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         reg = <0x0 0x3>;
  49                         enable-method = "psci";
  50                         next-level-cache = <&l2>;
  51                 };
  52
  53                 l2: l2-cache0 {
  54                         compatible = "cache";
  55                 };
  56         };
  57
  58         psci {
  59                 compatible = "arm,psci-1.0";
  60                 method = "smc";
  61         };
  62
  63         reserved-memory {
  64                 #address-cells = <2>;
  65                 #size-cells = <2>;
  66                 ranges;
  67
  68                 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
  69                 secmon_reserved: secmon@5000000 {
  70                         reg = <0x0 0x05000000 0x0 0x300000>;
  71                         no-map;
  72                 };
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80
  81                 periphs: periphs@ff634000 {
  82                         compatible = "simple-bus";
  83                         reg = <0x0 0xff634000 0x0 0x2000>;
  84                         #address-cells = <2>;
  85                         #size-cells = <2>;
  86                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
  87                 };
  88
  89                 hiubus: bus@ff63c000 {
  90                         compatible = "simple-bus";
  91                         reg = <0x0 0xff63c000 0x0 0x1c00>;
  92                         #address-cells = <2>;
  93                         #size-cells = <2>;
  94                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
  95                 };
  96
  97                 aobus: bus@ff800000 {
  98                         compatible = "simple-bus";
  99                         reg = <0x0 0xff800000 0x0 0x100000>;
 100                         #address-cells = <2>;
 101                         #size-cells = <2>;
 102                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
 103
 104                         uart_AO: serial@3000 {
 105                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 106                                 reg = <0x0 0x3000 0x0 0x18>;
 107                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 108                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 109                                 clock-names = "xtal", "pclk", "baud";
 110                                 status = "disabled";
 111                         };
 112
 113                         uart_AO_B: serial@4000 {
 114                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
 115                                 reg = <0x0 0x4000 0x0 0x18>;
 116                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
 117                                 clocks = <&xtal>, <&xtal>, <&xtal>;
 118                                 clock-names = "xtal", "pclk", "baud";
 119                                 status = "disabled";
 120                         };
 121                 };
 122
 123                 gic: interrupt-controller@ffc01000 {
 124                         compatible = "arm,gic-400";
 125                         reg = <0x0 0xffc01000 0 0x1000>,
 126                               <0x0 0xffc02000 0 0x2000>,
 127                               <0x0 0xffc04000 0 0x2000>,
 128                               <0x0 0xffc06000 0 0x2000>;
 129                         interrupt-controller;
 130                         interrupts = <GIC_PPI 9
 131                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 132                         #interrupt-cells = <3>;
 133                         #address-cells = <0>;
 134                 };
 135
 136                 cbus: bus@ffd00000 {
 137                         compatible = "simple-bus";
 138                         reg = <0x0 0xffd00000 0x0 0x25000>;
 139                         #address-cells = <2>;
 140                         #size-cells = <2>;
 141                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
 142                 };
 143
 144                 apb: apb@ffe00000 {
 145                         compatible = "simple-bus";
 146                         reg = <0x0 0xffe00000 0x0 0x200000>;
 147                         #address-cells = <2>;
 148                         #size-cells = <2>;
 149                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
 150                 };
 151         };
 152
 153         timer {
 154                 compatible = "arm,armv8-timer";
 155                 interrupts = <GIC_PPI 13
 156                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 157                              <GIC_PPI 14
 158                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 159                              <GIC_PPI 11
 160                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <GIC_PPI 10
 162                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         xtal: xtal-clk {
 166                 compatible = "fixed-clock";
 167                 clock-frequency = <24000000>;
 168                 clock-output-names = "xtal";
 169                 #clock-cells = <0>;
 170         };
 171
 172 };