arch/arm64/boot/dts/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/clock/axg-aoclkc.h>
   7 #include <dt-bindings/clock/axg-audio-clkc.h>
   8 #include <dt-bindings/clock/axg-clkc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/gpio/meson-axg-gpio.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
  14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  15
  16 / {
  17         compatible = "amlogic,meson-axg";
  18
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         tdmif_a: audio-controller-0 {
  24                 compatible = "amlogic,axg-tdm-iface";
  25                 #sound-dai-cells = <0>;
  26                 sound-name-prefix = "TDM_A";
  27                 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
  28                          <&clkc_audio AUD_CLKID_MST_A_SCLK>,
  29                          <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
  30                 clock-names = "mclk", "sclk", "lrclk";
  31                 status = "disabled";
  32         };
  33
  34         tdmif_b: audio-controller-1 {
  35                 compatible = "amlogic,axg-tdm-iface";
  36                 #sound-dai-cells = <0>;
  37                 sound-name-prefix = "TDM_B";
  38                 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
  39                          <&clkc_audio AUD_CLKID_MST_B_SCLK>,
  40                          <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
  41                 clock-names = "mclk", "sclk", "lrclk";
  42                 status = "disabled";
  43         };
  44
  45         tdmif_c: audio-controller-2 {
  46                 compatible = "amlogic,axg-tdm-iface";
  47                 #sound-dai-cells = <0>;
  48                 sound-name-prefix = "TDM_C";
  49                 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
  50                          <&clkc_audio AUD_CLKID_MST_C_SCLK>,
  51                          <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
  52                 clock-names = "mclk", "sclk", "lrclk";
  53                 status = "disabled";
  54         };
  55
  56         arm-pmu {
  57                 compatible = "arm,cortex-a53-pmu";
  58                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  59                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  60                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  62                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  63         };
  64
  65         cpus {
  66                 #address-cells = <0x2>;
  67                 #size-cells = <0x0>;
  68
  69                 cpu0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&l2>;
  75                         clocks = <&scpi_dvfs 0>;
  76                 };
  77
  78                 cpu1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <0x0 0x1>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&l2>;
  84                         clocks = <&scpi_dvfs 0>;
  85                 };
  86
  87                 cpu2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         reg = <0x0 0x2>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&l2>;
  93                         clocks = <&scpi_dvfs 0>;
  94                 };
  95
  96                 cpu3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&l2>;
 102                         clocks = <&scpi_dvfs 0>;
 103                 };
 104
 105                 l2: l2-cache0 {
 106                         compatible = "cache";
 107                 };
 108         };
 109
 110         sm: secure-monitor {
 111                 compatible = "amlogic,meson-gxbb-sm";
 112         };
 113
 114         efuse: efuse {
 115                 compatible = "amlogic,meson-gxbb-efuse";
 116                 clocks = <&clkc CLKID_EFUSE>;
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 read-only;
 120         };
 121
 122         psci {
 123                 compatible = "arm,psci-1.0";
 124                 method = "smc";
 125         };
 126
 127         reserved-memory {
 128                 #address-cells = <2>;
 129                 #size-cells = <2>;
 130                 ranges;
 131
 132                 /* 16 MiB reserved for Hardware ROM Firmware */
 133                 hwrom_reserved: hwrom@0 {
 134                         reg = <0x0 0x0 0x0 0x1000000>;
 135                         no-map;
 136                 };
 137
 138                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
 139                 secmon_reserved: secmon@5000000 {
 140                         reg = <0x0 0x05000000 0x0 0x300000>;
 141                         no-map;
 142                 };
 143         };
 144
 145         scpi {
 146                 compatible = "arm,scpi-pre-1.0";
 147                 mboxes = <&mailbox 1 &mailbox 2>;
 148                 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
 149
 150                 scpi_clocks: clocks {
 151                         compatible = "arm,scpi-clocks";
 152
 153                         scpi_dvfs: clock-controller {
 154                                 compatible = "arm,scpi-dvfs-clocks";
 155                                 #clock-cells = <1>;
 156                                 clock-indices = <0>;
 157                                 clock-output-names = "vcpu";
 158                         };
 159                 };
 160
 161                 scpi_sensors: sensors {
 162                         compatible = "amlogic,meson-gxbb-scpi-sensors";
 163                         #thermal-sensor-cells = <1>;
 164                 };
 165         };
 166
 167         soc {
 168                 compatible = "simple-bus";
 169                 #address-cells = <2>;
 170                 #size-cells = <2>;
 171                 ranges;
 172
 173                 ethmac: ethernet@ff3f0000 {
 174                         compatible = "amlogic,meson-axg-dwmac",
 175                                      "snps,dwmac-3.70a",
 176                                      "snps,dwmac";
 177                         reg = <0x0 0xff3f0000 0x0 0x10000>,
 178                               <0x0 0xff634540 0x0 0x8>;
 179                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 180                         interrupt-names = "macirq";
 181                         clocks = <&clkc CLKID_ETH>,
 182                                  <&clkc CLKID_FCLK_DIV2>,
 183                                  <&clkc CLKID_MPLL2>;
 184                         clock-names = "stmmaceth", "clkin0", "clkin1";
 185                         rx-fifo-depth = <4096>;
 186                         tx-fifo-depth = <2048>;
 187                         status = "disabled";
 188                 };
 189
 190                 pdm: audio-controller@ff632000 {
 191                         compatible = "amlogic,axg-pdm";
 192                         reg = <0x0 0xff632000 0x0 0x34>;
 193                         #sound-dai-cells = <0>;
 194                         sound-name-prefix = "PDM";
 195                         clocks = <&clkc_audio AUD_CLKID_PDM>,
 196                                  <&clkc_audio AUD_CLKID_PDM_DCLK>,
 197                                  <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
 198                         clock-names = "pclk", "dclk", "sysclk";
 199                         status = "disabled";
 200                 };
 201
 202                 periphs: bus@ff634000 {
 203                         compatible = "simple-bus";
 204                         reg = <0x0 0xff634000 0x0 0x2000>;
 205                         #address-cells = <2>;
 206                         #size-cells = <2>;
 207                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 208
 209                         hwrng: rng@18 {
 210                                 compatible = "amlogic,meson-rng";
 211                                 reg = <0x0 0x18 0x0 0x4>;
 212                                 clocks = <&clkc CLKID_RNG0>;
 213                                 clock-names = "core";
 214                         };
 215
 216                         pinctrl_periphs: pinctrl@480 {
 217                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 218                                 #address-cells = <2>;
 219                                 #size-cells = <2>;
 220                                 ranges;
 221
 222                                 gpio: bank@480 {
 223                                         reg = <0x0 0x00480 0x0 0x40>,
 224                                               <0x0 0x004e8 0x0 0x14>,
 225                                               <0x0 0x00520 0x0 0x14>,
 226                                               <0x0 0x00430 0x0 0x3c>;
 227                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 228                                         gpio-controller;
 229                                         #gpio-cells = <2>;
 230                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 231                                 };
 232
 233                                 i2c0_pins: i2c0 {
 234                                         mux {
 235                                                 groups = "i2c0_sck",
 236                                                          "i2c0_sda";
 237                                                 function = "i2c0";
 238                                                 bias-disable;
 239                                         };
 240                                 };
 241
 242                                 i2c1_x_pins: i2c1_x {
 243                                         mux {
 244                                                 groups = "i2c1_sck_x",
 245                                                          "i2c1_sda_x";
 246                                                 function = "i2c1";
 247                                                 bias-disable;
 248                                         };
 249                                 };
 250
 251                                 i2c1_z_pins: i2c1_z {
 252                                         mux {
 253                                                 groups = "i2c1_sck_z",
 254                                                          "i2c1_sda_z";
 255                                                 function = "i2c1";
 256                                                 bias-disable;
 257                                         };
 258                                 };
 259
 260                                 i2c2_a_pins: i2c2_a {
 261                                         mux {
 262                                                 groups = "i2c2_sck_a",
 263                                                          "i2c2_sda_a";
 264                                                 function = "i2c2";
 265                                                 bias-disable;
 266                                         };
 267                                 };
 268
 269                                 i2c2_x_pins: i2c2_x {
 270                                         mux {
 271                                                 groups = "i2c2_sck_x",
 272                                                          "i2c2_sda_x";
 273                                                 function = "i2c2";
 274                                                 bias-disable;
 275                                         };
 276                                 };
 277
 278                                 i2c3_a6_pins: i2c3_a6 {
 279                                         mux {
 280                                                 groups = "i2c3_sda_a6",
 281                                                          "i2c3_sck_a7";
 282                                                 function = "i2c3";
 283                                                 bias-disable;
 284                                         };
 285                                 };
 286
 287                                 i2c3_a12_pins: i2c3_a12 {
 288                                         mux {
 289                                                 groups = "i2c3_sda_a12",
 290                                                          "i2c3_sck_a13";
 291                                                 function = "i2c3";
 292                                                 bias-disable;
 293                                         };
 294                                 };
 295
 296                                 i2c3_a19_pins: i2c3_a19 {
 297                                         mux {
 298                                                 groups = "i2c3_sda_a19",
 299                                                          "i2c3_sck_a20";
 300                                                 function = "i2c3";
 301                                                 bias-disable;
 302                                         };
 303                                 };
 304
 305                                 emmc_pins: emmc {
 306                                         mux-0 {
 307                                                 groups = "emmc_nand_d0",
 308                                                          "emmc_nand_d1",
 309                                                          "emmc_nand_d2",
 310                                                          "emmc_nand_d3",
 311                                                          "emmc_nand_d4",
 312                                                          "emmc_nand_d5",
 313                                                          "emmc_nand_d6",
 314                                                          "emmc_nand_d7",
 315                                                          "emmc_cmd";
 316                                                 function = "emmc";
 317                                                 bias-pull-up;
 318                                         };
 319
 320                                         mux-1 {
 321                                                 groups = "emmc_clk";
 322                                                 function = "emmc";
 323                                                 bias-disable;
 324                                         };
 325                                 };
 326
 327                                 emmc_ds_pins: emmc_ds {
 328                                         mux {
 329                                                 groups = "emmc_ds";
 330                                                 function = "emmc";
 331                                                 bias-pull-down;
 332                                         };
 333                                 };
 334
 335                                 emmc_clk_gate_pins: emmc_clk_gate {
 336                                         mux {
 337                                                 groups = "BOOT_8";
 338                                                 function = "gpio_periphs";
 339                                                 bias-pull-down;
 340                                         };
 341                                 };
 342
 343                                 eth_rgmii_x_pins: eth-x-rgmii {
 344                                         mux {
 345                                                 groups = "eth_mdio_x",
 346                                                          "eth_mdc_x",
 347                                                          "eth_rgmii_rx_clk_x",
 348                                                          "eth_rx_dv_x",
 349                                                          "eth_rxd0_x",
 350                                                          "eth_rxd1_x",
 351                                                          "eth_rxd2_rgmii",
 352                                                          "eth_rxd3_rgmii",
 353                                                          "eth_rgmii_tx_clk",
 354                                                          "eth_txen_x",
 355                                                          "eth_txd0_x",
 356                                                          "eth_txd1_x",
 357                                                          "eth_txd2_rgmii",
 358                                                          "eth_txd3_rgmii";
 359                                                 function = "eth";
 360                                                 bias-disable;
 361                                         };
 362                                 };
 363
 364                                 eth_rgmii_y_pins: eth-y-rgmii {
 365                                         mux {
 366                                                 groups = "eth_mdio_y",
 367                                                          "eth_mdc_y",
 368                                                          "eth_rgmii_rx_clk_y",
 369                                                          "eth_rx_dv_y",
 370                                                          "eth_rxd0_y",
 371                                                          "eth_rxd1_y",
 372                                                          "eth_rxd2_rgmii",
 373                                                          "eth_rxd3_rgmii",
 374                                                          "eth_rgmii_tx_clk",
 375                                                          "eth_txen_y",
 376                                                          "eth_txd0_y",
 377                                                          "eth_txd1_y",
 378                                                          "eth_txd2_rgmii",
 379                                                          "eth_txd3_rgmii";
 380                                                 function = "eth";
 381                                                 bias-disable;
 382                                         };
 383                                 };
 384
 385                                 eth_rmii_x_pins: eth-x-rmii {
 386                                         mux {
 387                                                 groups = "eth_mdio_x",
 388                                                          "eth_mdc_x",
 389                                                          "eth_rgmii_rx_clk_x",
 390                                                          "eth_rx_dv_x",
 391                                                          "eth_rxd0_x",
 392                                                          "eth_rxd1_x",
 393                                                          "eth_txen_x",
 394                                                          "eth_txd0_x",
 395                                                          "eth_txd1_x";
 396                                                 function = "eth";
 397                                                 bias-disable;
 398                                         };
 399                                 };
 400
 401                                 eth_rmii_y_pins: eth-y-rmii {
 402                                         mux {
 403                                                 groups = "eth_mdio_y",
 404                                                          "eth_mdc_y",
 405                                                          "eth_rgmii_rx_clk_y",
 406                                                          "eth_rx_dv_y",
 407                                                          "eth_rxd0_y",
 408                                                          "eth_rxd1_y",
 409                                                          "eth_txen_y",
 410                                                          "eth_txd0_y",
 411                                                          "eth_txd1_y";
 412                                                 function = "eth";
 413                                                 bias-disable;
 414                                         };
 415                                 };
 416
 417                                 mclk_b_pins: mclk_b {
 418                                         mux {
 419                                                 groups = "mclk_b";
 420                                                 function = "mclk_b";
 421                                                 bias-disable;
 422                                         };
 423                                 };
 424
 425                                 mclk_c_pins: mclk_c {
 426                                         mux {
 427                                                 groups = "mclk_c";
 428                                                 function = "mclk_c";
 429                                                 bias-disable;
 430                                         };
 431                                 };
 432
 433                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
 434                                         mux {
 435                                                 groups = "pdm_dclk_a14";
 436                                                 function = "pdm";
 437                                                 bias-disable;
 438                                         };
 439                                 };
 440
 441                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
 442                                         mux {
 443                                                 groups = "pdm_dclk_a19";
 444                                                 function = "pdm";
 445                                                 bias-disable;
 446                                         };
 447                                 };
 448
 449                                 pdm_din0_pins: pdm_din0 {
 450                                         mux {
 451                                                 groups = "pdm_din0";
 452                                                 function = "pdm";
 453                                                 bias-disable;
 454                                         };
 455                                 };
 456
 457                                 pdm_din1_pins: pdm_din1 {
 458                                         mux {
 459                                                 groups = "pdm_din1";
 460                                                 function = "pdm";
 461                                                 bias-disable;
 462                                         };
 463                                 };
 464
 465                                 pdm_din2_pins: pdm_din2 {
 466                                         mux {
 467                                                 groups = "pdm_din2";
 468                                                 function = "pdm";
 469                                                 bias-disable;
 470                                         };
 471                                 };
 472
 473                                 pdm_din3_pins: pdm_din3 {
 474                                         mux {
 475                                                 groups = "pdm_din3";
 476                                                 function = "pdm";
 477                                                 bias-disable;
 478                                         };
 479                                 };
 480
 481                                 pwm_a_a_pins: pwm_a_a {
 482                                         mux {
 483                                                 groups = "pwm_a_a";
 484                                                 function = "pwm_a";
 485                                                 bias-disable;
 486                                         };
 487                                 };
 488
 489                                 pwm_a_x18_pins: pwm_a_x18 {
 490                                         mux {
 491                                                 groups = "pwm_a_x18";
 492                                                 function = "pwm_a";
 493                                                 bias-disable;
 494                                         };
 495                                 };
 496
 497                                 pwm_a_x20_pins: pwm_a_x20 {
 498                                         mux {
 499                                                 groups = "pwm_a_x20";
 500                                                 function = "pwm_a";
 501                                                 bias-disable;
 502                                         };
 503                                 };
 504
 505                                 pwm_a_z_pins: pwm_a_z {
 506                                         mux {
 507                                                 groups = "pwm_a_z";
 508                                                 function = "pwm_a";
 509                                                 bias-disable;
 510                                         };
 511                                 };
 512
 513                                 pwm_b_a_pins: pwm_b_a {
 514                                         mux {
 515                                                 groups = "pwm_b_a";
 516                                                 function = "pwm_b";
 517                                                 bias-disable;
 518                                         };
 519                                 };
 520
 521                                 pwm_b_x_pins: pwm_b_x {
 522                                         mux {
 523                                                 groups = "pwm_b_x";
 524                                                 function = "pwm_b";
 525                                                 bias-disable;
 526                                         };
 527                                 };
 528
 529                                 pwm_b_z_pins: pwm_b_z {
 530                                         mux {
 531                                                 groups = "pwm_b_z";
 532                                                 function = "pwm_b";
 533                                                 bias-disable;
 534                                         };
 535                                 };
 536
 537                                 pwm_c_a_pins: pwm_c_a {
 538                                         mux {
 539                                                 groups = "pwm_c_a";
 540                                                 function = "pwm_c";
 541                                                 bias-disable;
 542                                         };
 543                                 };
 544
 545                                 pwm_c_x10_pins: pwm_c_x10 {
 546                                         mux {
 547                                                 groups = "pwm_c_x10";
 548                                                 function = "pwm_c";
 549                                                 bias-disable;
 550                                         };
 551                                 };
 552
 553                                 pwm_c_x17_pins: pwm_c_x17 {
 554                                         mux {
 555                                                 groups = "pwm_c_x17";
 556                                                 function = "pwm_c";
 557                                                 bias-disable;
 558                                         };
 559                                 };
 560
 561                                 pwm_d_x11_pins: pwm_d_x11 {
 562                                         mux {
 563                                                 groups = "pwm_d_x11";
 564                                                 function = "pwm_d";
 565                                                 bias-disable;
 566                                         };
 567                                 };
 568
 569                                 pwm_d_x16_pins: pwm_d_x16 {
 570                                         mux {
 571                                                 groups = "pwm_d_x16";
 572                                                 function = "pwm_d";
 573                                                 bias-disable;
 574                                         };
 575                                 };
 576
 577                                 sdio_pins: sdio {
 578                                         mux-0 {
 579                                                 groups = "sdio_d0",
 580                                                          "sdio_d1",
 581                                                          "sdio_d2",
 582                                                          "sdio_d3",
 583                                                          "sdio_cmd";
 584                                                 function = "sdio";
 585                                                 bias-pull-up;
 586                                         };
 587
 588                                         mux-1 {
 589                                                 groups = "sdio_clk";
 590                                                 function = "sdio";
 591                                                 bias-disable;
 592                                         };
 593                                 };
 594
 595                                 sdio_clk_gate_pins: sdio_clk_gate {
 596                                         mux {
 597                                                 groups = "GPIOX_4";
 598                                                 function = "gpio_periphs";
 599                                                 bias-pull-down;
 600                                         };
 601                                 };
 602
 603                                 spdif_in_z_pins: spdif_in_z {
 604                                         mux {
 605                                                 groups = "spdif_in_z";
 606                                                 function = "spdif_in";
 607                                                 bias-disable;
 608                                         };
 609                                 };
 610
 611                                 spdif_in_a1_pins: spdif_in_a1 {
 612                                         mux {
 613                                                 groups = "spdif_in_a1";
 614                                                 function = "spdif_in";
 615                                                 bias-disable;
 616                                         };
 617                                 };
 618
 619                                 spdif_in_a7_pins: spdif_in_a7 {
 620                                         mux {
 621                                                 groups = "spdif_in_a7";
 622                                                 function = "spdif_in";
 623                                                 bias-disable;
 624                                         };
 625                                 };
 626
 627                                 spdif_in_a19_pins: spdif_in_a19 {
 628                                         mux {
 629                                                 groups = "spdif_in_a19";
 630                                                 function = "spdif_in";
 631                                                 bias-disable;
 632                                         };
 633                                 };
 634
 635                                 spdif_in_a20_pins: spdif_in_a20 {
 636                                         mux {
 637                                                 groups = "spdif_in_a20";
 638                                                 function = "spdif_in";
 639                                                 bias-disable;
 640                                         };
 641                                 };
 642
 643                                 spdif_out_a1_pins: spdif_out_a1 {
 644                                         mux {
 645                                                 groups = "spdif_out_a1";
 646                                                 function = "spdif_out";
 647                                                 bias-disable;
 648                                         };
 649                                 };
 650
 651                                 spdif_out_a11_pins: spdif_out_a11 {
 652                                         mux {
 653                                                 groups = "spdif_out_a11";
 654                                                 function = "spdif_out";
 655                                                 bias-disable;
 656                                         };
 657                                 };
 658
 659                                 spdif_out_a19_pins: spdif_out_a19 {
 660                                         mux {
 661                                                 groups = "spdif_out_a19";
 662                                                 function = "spdif_out";
 663                                                 bias-disable;
 664                                         };
 665                                 };
 666
 667                                 spdif_out_a20_pins: spdif_out_a20 {
 668                                         mux {
 669                                                 groups = "spdif_out_a20";
 670                                                 function = "spdif_out";
 671                                                 bias-disable;
 672                                         };
 673                                 };
 674
 675                                 spdif_out_z_pins: spdif_out_z {
 676                                         mux {
 677                                                 groups = "spdif_out_z";
 678                                                 function = "spdif_out";
 679                                                 bias-disable;
 680                                         };
 681                                 };
 682
 683                                 spi0_pins: spi0 {
 684                                         mux {
 685                                                 groups = "spi0_miso",
 686                                                          "spi0_mosi",
 687                                                          "spi0_clk";
 688                                                 function = "spi0";
 689                                                 bias-disable;
 690                                         };
 691                                 };
 692
 693                                 spi0_ss0_pins: spi0_ss0 {
 694                                         mux {
 695                                                 groups = "spi0_ss0";
 696                                                 function = "spi0";
 697                                                 bias-disable;
 698                                         };
 699                                 };
 700
 701                                 spi0_ss1_pins: spi0_ss1 {
 702                                         mux {
 703                                                 groups = "spi0_ss1";
 704                                                 function = "spi0";
 705                                                 bias-disable;
 706                                         };
 707                                 };
 708
 709                                 spi0_ss2_pins: spi0_ss2 {
 710                                         mux {
 711                                                 groups = "spi0_ss2";
 712                                                 function = "spi0";
 713                                                 bias-disable;
 714                                         };
 715                                 };
 716
 717                                 spi1_a_pins: spi1_a {
 718                                         mux {
 719                                                 groups = "spi1_miso_a",
 720                                                          "spi1_mosi_a",
 721                                                          "spi1_clk_a";
 722                                                 function = "spi1";
 723                                                 bias-disable;
 724                                         };
 725                                 };
 726
 727                                 spi1_ss0_a_pins: spi1_ss0_a {
 728                                         mux {
 729                                                 groups = "spi1_ss0_a";
 730                                                 function = "spi1";
 731                                                 bias-disable;
 732                                         };
 733                                 };
 734
 735                                 spi1_ss1_pins: spi1_ss1 {
 736                                         mux {
 737                                                 groups = "spi1_ss1";
 738                                                 function = "spi1";
 739                                                 bias-disable;
 740                                         };
 741                                 };
 742
 743                                 spi1_x_pins: spi1_x {
 744                                         mux {
 745                                                 groups = "spi1_miso_x",
 746                                                          "spi1_mosi_x",
 747                                                          "spi1_clk_x";
 748                                                 function = "spi1";
 749                                                 bias-disable;
 750                                         };
 751                                 };
 752
 753                                 spi1_ss0_x_pins: spi1_ss0_x {
 754                                         mux {
 755                                                 groups = "spi1_ss0_x";
 756                                                 function = "spi1";
 757                                                 bias-disable;
 758                                         };
 759                                 };
 760
 761                                 tdma_din0_pins: tdma_din0 {
 762                                         mux {
 763                                                 groups = "tdma_din0";
 764                                                 function = "tdma";
 765                                                 bias-disable;
 766                                         };
 767                                 };
 768
 769                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
 770                                         mux {
 771                                                 groups = "tdma_dout0_x14";
 772                                                 function = "tdma";
 773                                                 bias-disable;
 774                                         };
 775                                 };
 776
 777                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
 778                                         mux {
 779                                                 groups = "tdma_dout0_x15";
 780                                                 function = "tdma";
 781                                                 bias-disable;
 782                                         };
 783                                 };
 784
 785                                 tdma_dout1_pins: tdma_dout1 {
 786                                         mux {
 787                                                 groups = "tdma_dout1";
 788                                                 function = "tdma";
 789                                                 bias-disable;
 790                                         };
 791                                 };
 792
 793                                 tdma_din1_pins: tdma_din1 {
 794                                         mux {
 795                                                 groups = "tdma_din1";
 796                                                 function = "tdma";
 797                                                 bias-disable;
 798                                         };
 799                                 };
 800
 801                                 tdma_fs_pins: tdma_fs {
 802                                         mux {
 803                                                 groups = "tdma_fs";
 804                                                 function = "tdma";
 805                                                 bias-disable;
 806                                         };
 807                                 };
 808
 809                                 tdma_fs_slv_pins: tdma_fs_slv {
 810                                         mux {
 811                                                 groups = "tdma_fs_slv";
 812                                                 function = "tdma";
 813                                                 bias-disable;
 814                                         };
 815                                 };
 816
 817                                 tdma_sclk_pins: tdma_sclk {
 818                                         mux {
 819                                                 groups = "tdma_sclk";
 820                                                 function = "tdma";
 821                                                 bias-disable;
 822                                         };
 823                                 };
 824
 825                                 tdma_sclk_slv_pins: tdma_sclk_slv {
 826                                         mux {
 827                                                 groups = "tdma_sclk_slv";
 828                                                 function = "tdma";
 829                                                 bias-disable;
 830                                         };
 831                                 };
 832
 833                                 tdmb_din0_pins: tdmb_din0 {
 834                                         mux {
 835                                                 groups = "tdmb_din0";
 836                                                 function = "tdmb";
 837                                                 bias-disable;
 838                                         };
 839                                 };
 840
 841                                 tdmb_din1_pins: tdmb_din1 {
 842                                         mux {
 843                                                 groups = "tdmb_din1";
 844                                                 function = "tdmb";
 845                                                 bias-disable;
 846                                         };
 847                                 };
 848
 849                                 tdmb_din2_pins: tdmb_din2 {
 850                                         mux {
 851                                                 groups = "tdmb_din2";
 852                                                 function = "tdmb";
 853                                                 bias-disable;
 854                                         };
 855                                 };
 856
 857                                 tdmb_din3_pins: tdmb_din3 {
 858                                         mux {
 859                                                 groups = "tdmb_din3";
 860                                                 function = "tdmb";
 861                                                 bias-disable;
 862                                         };
 863                                 };
 864
 865                                 tdmb_dout0_pins: tdmb_dout0 {
 866                                         mux {
 867                                                 groups = "tdmb_dout0";
 868                                                 function = "tdmb";
 869                                                 bias-disable;
 870                                         };
 871                                 };
 872
 873                                 tdmb_dout1_pins: tdmb_dout1 {
 874                                         mux {
 875                                                 groups = "tdmb_dout1";
 876                                                 function = "tdmb";
 877                                                 bias-disable;
 878                                         };
 879                                 };
 880
 881                                 tdmb_dout2_pins: tdmb_dout2 {
 882                                         mux {
 883                                                 groups = "tdmb_dout2";
 884                                                 function = "tdmb";
 885                                                 bias-disable;
 886                                         };
 887                                 };
 888
 889                                 tdmb_dout3_pins: tdmb_dout3 {
 890                                         mux {
 891                                                 groups = "tdmb_dout3";
 892                                                 function = "tdmb";
 893                                                 bias-disable;
 894                                         };
 895                                 };
 896
 897                                 tdmb_fs_pins: tdmb_fs {
 898                                         mux {
 899                                                 groups = "tdmb_fs";
 900                                                 function = "tdmb";
 901                                                 bias-disable;
 902                                         };
 903                                 };
 904
 905                                 tdmb_fs_slv_pins: tdmb_fs_slv {
 906                                         mux {
 907                                                 groups = "tdmb_fs_slv";
 908                                                 function = "tdmb";
 909                                                 bias-disable;
 910                                         };
 911                                 };
 912
 913                                 tdmb_sclk_pins: tdmb_sclk {
 914                                         mux {
 915                                                 groups = "tdmb_sclk";
 916                                                 function = "tdmb";
 917                                                 bias-disable;
 918                                         };
 919                                 };
 920
 921                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
 922                                         mux {
 923                                                 groups = "tdmb_sclk_slv";
 924                                                 function = "tdmb";
 925                                                 bias-disable;
 926                                         };
 927                                 };
 928
 929                                 tdmc_fs_pins: tdmc_fs {
 930                                         mux {
 931                                                 groups = "tdmc_fs";
 932                                                 function = "tdmc";
 933                                                 bias-disable;
 934                                         };
 935                                 };
 936
 937                                 tdmc_fs_slv_pins: tdmc_fs_slv {
 938                                         mux {
 939                                                 groups = "tdmc_fs_slv";
 940                                                 function = "tdmc";
 941                                                 bias-disable;
 942                                         };
 943                                 };
 944
 945                                 tdmc_sclk_pins: tdmc_sclk {
 946                                         mux {
 947                                                 groups = "tdmc_sclk";
 948                                                 function = "tdmc";
 949                                                 bias-disable;
 950                                         };
 951                                 };
 952
 953                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
 954                                         mux {
 955                                                 groups = "tdmc_sclk_slv";
 956                                                 function = "tdmc";
 957                                                 bias-disable;
 958                                         };
 959                                 };
 960
 961                                 tdmc_din0_pins: tdmc_din0 {
 962                                         mux {
 963                                                 groups = "tdmc_din0";
 964                                                 function = "tdmc";
 965                                                 bias-disable;
 966                                         };
 967                                 };
 968
 969                                 tdmc_din1_pins: tdmc_din1 {
 970                                         mux {
 971                                                 groups = "tdmc_din1";
 972                                                 function = "tdmc";
 973                                                 bias-disable;
 974                                         };
 975                                 };
 976
 977                                 tdmc_din2_pins: tdmc_din2 {
 978                                         mux {
 979                                                 groups = "tdmc_din2";
 980                                                 function = "tdmc";
 981                                                 bias-disable;
 982                                         };
 983                                 };
 984
 985                                 tdmc_din3_pins: tdmc_din3 {
 986                                         mux {
 987                                                 groups = "tdmc_din3";
 988                                                 function = "tdmc";
 989                                                 bias-disable;
 990                                         };
 991                                 };
 992
 993                                 tdmc_dout0_pins: tdmc_dout0 {
 994                                         mux {
 995                                                 groups = "tdmc_dout0";
 996                                                 function = "tdmc";
 997                                                 bias-disable;
 998                                         };
 999                                 };
1000
1001                                 tdmc_dout1_pins: tdmc_dout1 {
1002                                         mux {
1003                                                 groups = "tdmc_dout1";
1004                                                 function = "tdmc";
1005                                                 bias-disable;
1006                                         };
1007                                 };
1008
1009                                 tdmc_dout2_pins: tdmc_dout2 {
1010                                         mux {
1011                                                 groups = "tdmc_dout2";
1012                                                 function = "tdmc";
1013                                                 bias-disable;
1014                                         };
1015                                 };
1016
1017                                 tdmc_dout3_pins: tdmc_dout3 {
1018                                         mux {
1019                                                 groups = "tdmc_dout3";
1020                                                 function = "tdmc";
1021                                                 bias-disable;
1022                                         };
1023                                 };
1024
1025                                 uart_a_pins: uart_a {
1026                                         mux {
1027                                                 groups = "uart_tx_a",
1028                                                          "uart_rx_a";
1029                                                 function = "uart_a";
1030                                                 bias-disable;
1031                                         };
1032                                 };
1033
1034                                 uart_a_cts_rts_pins: uart_a_cts_rts {
1035                                         mux {
1036                                                 groups = "uart_cts_a",
1037                                                          "uart_rts_a";
1038                                                 function = "uart_a";
1039                                                 bias-disable;
1040                                         };
1041                                 };
1042
1043                                 uart_b_x_pins: uart_b_x {
1044                                         mux {
1045                                                 groups = "uart_tx_b_x",
1046                                                          "uart_rx_b_x";
1047                                                 function = "uart_b";
1048                                                 bias-disable;
1049                                         };
1050                                 };
1051
1052                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1053                                         mux {
1054                                                 groups = "uart_cts_b_x",
1055                                                          "uart_rts_b_x";
1056                                                 function = "uart_b";
1057                                                 bias-disable;
1058                                         };
1059                                 };
1060
1061                                 uart_b_z_pins: uart_b_z {
1062                                         mux {
1063                                                 groups = "uart_tx_b_z",
1064                                                          "uart_rx_b_z";
1065                                                 function = "uart_b";
1066                                                 bias-disable;
1067                                         };
1068                                 };
1069
1070                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1071                                         mux {
1072                                                 groups = "uart_cts_b_z",
1073                                                          "uart_rts_b_z";
1074                                                 function = "uart_b";
1075                                                 bias-disable;
1076                                         };
1077                                 };
1078
1079                                 uart_ao_b_z_pins: uart_ao_b_z {
1080                                         mux {
1081                                                 groups = "uart_ao_tx_b_z",
1082                                                          "uart_ao_rx_b_z";
1083                                                 function = "uart_ao_b_z";
1084                                                 bias-disable;
1085                                         };
1086                                 };
1087
1088                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1089                                         mux {
1090                                                 groups = "uart_ao_cts_b_z",
1091                                                          "uart_ao_rts_b_z";
1092                                                 function = "uart_ao_b_z";
1093                                                 bias-disable;
1094                                         };
1095                                 };
1096                         };
1097                 };
1098
1099                 hiubus: bus@ff63c000 {
1100                         compatible = "simple-bus";
1101                         reg = <0x0 0xff63c000 0x0 0x1c00>;
1102                         #address-cells = <2>;
1103                         #size-cells = <2>;
1104                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1105
1106                         sysctrl: system-controller@0 {
1107                                 compatible = "amlogic,meson-axg-hhi-sysctrl",
1108                                              "simple-mfd", "syscon";
1109                                 reg = <0 0 0 0x400>;
1110
1111                                 clkc: clock-controller {
1112                                         compatible = "amlogic,axg-clkc";
1113                                         #clock-cells = <1>;
1114                                         clocks = <&xtal>;
1115                                         clock-names = "xtal";
1116                                 };
1117                         };
1118                 };
1119
1120                 mailbox: mailbox@ff63c404 {
1121                         compatible = "amlogic,meson-gxbb-mhu";
1122                         reg = <0 0xff63c404 0 0x4c>;
1123                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1124                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1125                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1126                         #mbox-cells = <1>;
1127                 };
1128
1129                 audio: bus@ff642000 {
1130                         compatible = "simple-bus";
1131                         reg = <0x0 0xff642000 0x0 0x2000>;
1132                         #address-cells = <2>;
1133                         #size-cells = <2>;
1134                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1135
1136                         clkc_audio: clock-controller@0 {
1137                                 compatible = "amlogic,axg-audio-clkc";
1138                                 reg = <0x0 0x0 0x0 0xb4>;
1139                                 #clock-cells = <1>;
1140
1141                                 clocks = <&clkc CLKID_AUDIO>,
1142                                          <&clkc CLKID_MPLL0>,
1143                                          <&clkc CLKID_MPLL1>,
1144                                          <&clkc CLKID_MPLL2>,
1145                                          <&clkc CLKID_MPLL3>,
1146                                          <&clkc CLKID_HIFI_PLL>,
1147                                          <&clkc CLKID_FCLK_DIV3>,
1148                                          <&clkc CLKID_FCLK_DIV4>,
1149                                          <&clkc CLKID_GP0_PLL>;
1150                                 clock-names = "pclk",
1151                                               "mst_in0",
1152                                               "mst_in1",
1153                                               "mst_in2",
1154                                               "mst_in3",
1155                                               "mst_in4",
1156                                               "mst_in5",
1157                                               "mst_in6",
1158                                               "mst_in7";
1159
1160                                 resets = <&reset RESET_AUDIO>;
1161                         };
1162
1163                         toddr_a: audio-controller@100 {
1164                                 compatible = "amlogic,axg-toddr";
1165                                 reg = <0x0 0x100 0x0 0x1c>;
1166                                 #sound-dai-cells = <0>;
1167                                 sound-name-prefix = "TODDR_A";
1168                                 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1169                                 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1170                                 resets = <&arb AXG_ARB_TODDR_A>;
1171                                 status = "disabled";
1172                         };
1173
1174                         toddr_b: audio-controller@140 {
1175                                 compatible = "amlogic,axg-toddr";
1176                                 reg = <0x0 0x140 0x0 0x1c>;
1177                                 #sound-dai-cells = <0>;
1178                                 sound-name-prefix = "TODDR_B";
1179                                 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1180                                 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1181                                 resets = <&arb AXG_ARB_TODDR_B>;
1182                                 status = "disabled";
1183                         };
1184
1185                         toddr_c: audio-controller@180 {
1186                                 compatible = "amlogic,axg-toddr";
1187                                 reg = <0x0 0x180 0x0 0x1c>;
1188                                 #sound-dai-cells = <0>;
1189                                 sound-name-prefix = "TODDR_C";
1190                                 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1191                                 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1192                                 resets = <&arb AXG_ARB_TODDR_C>;
1193                                 status = "disabled";
1194                         };
1195
1196                         frddr_a: audio-controller@1c0 {
1197                                 compatible = "amlogic,axg-frddr";
1198                                 reg = <0x0 0x1c0 0x0 0x1c>;
1199                                 #sound-dai-cells = <0>;
1200                                 sound-name-prefix = "FRDDR_A";
1201                                 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1202                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1203                                 resets = <&arb AXG_ARB_FRDDR_A>;
1204                                 status = "disabled";
1205                         };
1206
1207                         frddr_b: audio-controller@200 {
1208                                 compatible = "amlogic,axg-frddr";
1209                                 reg = <0x0 0x200 0x0 0x1c>;
1210                                 #sound-dai-cells = <0>;
1211                                 sound-name-prefix = "FRDDR_B";
1212                                 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1213                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1214                                 resets = <&arb AXG_ARB_FRDDR_B>;
1215                                 status = "disabled";
1216                         };
1217
1218                         frddr_c: audio-controller@240 {
1219                                 compatible = "amlogic,axg-frddr";
1220                                 reg = <0x0 0x240 0x0 0x1c>;
1221                                 #sound-dai-cells = <0>;
1222                                 sound-name-prefix = "FRDDR_C";
1223                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1224                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1225                                 resets = <&arb AXG_ARB_FRDDR_C>;
1226                                 status = "disabled";
1227                         };
1228
1229                         arb: reset-controller@280 {
1230                                 compatible = "amlogic,meson-axg-audio-arb";
1231                                 reg = <0x0 0x280 0x0 0x4>;
1232                                 #reset-cells = <1>;
1233                                 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1234                         };
1235
1236                         tdmin_a: audio-controller@300 {
1237                                 compatible = "amlogic,axg-tdmin";
1238                                 reg = <0x0 0x300 0x0 0x40>;
1239                                 sound-name-prefix = "TDMIN_A";
1240                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1241                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1242                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1243                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1244                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1245                                 clock-names = "pclk", "sclk", "sclk_sel",
1246                                               "lrclk", "lrclk_sel";
1247                                 status = "disabled";
1248                         };
1249
1250                         tdmin_b: audio-controller@340 {
1251                                 compatible = "amlogic,axg-tdmin";
1252                                 reg = <0x0 0x340 0x0 0x40>;
1253                                 sound-name-prefix = "TDMIN_B";
1254                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1255                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1256                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1257                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1258                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1259                                 clock-names = "pclk", "sclk", "sclk_sel",
1260                                               "lrclk", "lrclk_sel";
1261                                 status = "disabled";
1262                         };
1263
1264                         tdmin_c: audio-controller@380 {
1265                                 compatible = "amlogic,axg-tdmin";
1266                                 reg = <0x0 0x380 0x0 0x40>;
1267                                 sound-name-prefix = "TDMIN_C";
1268                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1269                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1270                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1271                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1272                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1273                                 clock-names = "pclk", "sclk", "sclk_sel",
1274                                               "lrclk", "lrclk_sel";
1275                                 status = "disabled";
1276                         };
1277
1278                         tdmin_lb: audio-controller@3c0 {
1279                                 compatible = "amlogic,axg-tdmin";
1280                                 reg = <0x0 0x3c0 0x0 0x40>;
1281                                 sound-name-prefix = "TDMIN_LB";
1282                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1283                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1284                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1285                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1286                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1287                                 clock-names = "pclk", "sclk", "sclk_sel",
1288                                               "lrclk", "lrclk_sel";
1289                                 status = "disabled";
1290                         };
1291
1292                         spdifin: audio-controller@400 {
1293                                 compatible = "amlogic,axg-spdifin";
1294                                 reg = <0x0 0x400 0x0 0x30>;
1295                                 #sound-dai-cells = <0>;
1296                                 sound-name-prefix = "SPDIFIN";
1297                                 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1298                                 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1299                                          <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1300                                 clock-names = "pclk", "refclk";
1301                                 status = "disabled";
1302                         };
1303
1304                         spdifout: audio-controller@480 {
1305                                 compatible = "amlogic,axg-spdifout";
1306                                 reg = <0x0 0x480 0x0 0x50>;
1307                                 #sound-dai-cells = <0>;
1308                                 sound-name-prefix = "SPDIFOUT";
1309                                 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1310                                          <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1311                                 clock-names = "pclk", "mclk";
1312                                 status = "disabled";
1313                         };
1314
1315                         tdmout_a: audio-controller@500 {
1316                                 compatible = "amlogic,axg-tdmout";
1317                                 reg = <0x0 0x500 0x0 0x40>;
1318                                 sound-name-prefix = "TDMOUT_A";
1319                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1320                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1321                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1322                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1323                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1324                                 clock-names = "pclk", "sclk", "sclk_sel",
1325                                               "lrclk", "lrclk_sel";
1326                                 status = "disabled";
1327                         };
1328
1329                         tdmout_b: audio-controller@540 {
1330                                 compatible = "amlogic,axg-tdmout";
1331                                 reg = <0x0 0x540 0x0 0x40>;
1332                                 sound-name-prefix = "TDMOUT_B";
1333                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1334                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1335                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1336                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1337                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1338                                 clock-names = "pclk", "sclk", "sclk_sel",
1339                                               "lrclk", "lrclk_sel";
1340                                 status = "disabled";
1341                         };
1342
1343                         tdmout_c: audio-controller@580 {
1344                                 compatible = "amlogic,axg-tdmout";
1345                                 reg = <0x0 0x580 0x0 0x40>;
1346                                 sound-name-prefix = "TDMOUT_C";
1347                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1348                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1349                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1350                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1351                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1352                                 clock-names = "pclk", "sclk", "sclk_sel",
1353                                               "lrclk", "lrclk_sel";
1354                                 status = "disabled";
1355                         };
1356                 };
1357
1358                 aobus: bus@ff800000 {
1359                         compatible = "simple-bus";
1360                         reg = <0x0 0xff800000 0x0 0x100000>;
1361                         #address-cells = <2>;
1362                         #size-cells = <2>;
1363                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1364
1365                         sysctrl_AO: sys-ctrl@0 {
1366                                 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1367                                 reg =  <0x0 0x0 0x0 0x100>;
1368
1369                                 clkc_AO: clock-controller {
1370                                         compatible = "amlogic,meson-axg-aoclkc";
1371                                         #clock-cells = <1>;
1372                                         #reset-cells = <1>;
1373                                         clocks = <&xtal>, <&clkc CLKID_CLK81>;
1374                                         clock-names = "xtal", "mpeg-clk";
1375                                 };
1376                         };
1377
1378                         pinctrl_aobus: pinctrl@14 {
1379                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1380                                 #address-cells = <2>;
1381                                 #size-cells = <2>;
1382                                 ranges;
1383
1384                                 gpio_ao: bank@14 {
1385                                         reg = <0x0 0x00014 0x0 0x8>,
1386                                               <0x0 0x0002c 0x0 0x4>,
1387                                               <0x0 0x00024 0x0 0x8>;
1388                                         reg-names = "mux", "pull", "gpio";
1389                                         gpio-controller;
1390                                         #gpio-cells = <2>;
1391                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1392                                 };
1393
1394                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1395                                         mux {
1396                                                 groups = "i2c_ao_sck_4";
1397                                                 function = "i2c_ao";
1398                                                 bias-disable;
1399                                         };
1400                                 };
1401
1402                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1403                                         mux {
1404                                                 groups = "i2c_ao_sck_8";
1405                                                 function = "i2c_ao";
1406                                                 bias-disable;
1407                                         };
1408                                 };
1409
1410                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1411                                         mux {
1412                                                 groups = "i2c_ao_sck_10";
1413                                                 function = "i2c_ao";
1414                                                 bias-disable;
1415                                         };
1416                                 };
1417
1418                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1419                                         mux {
1420                                                 groups = "i2c_ao_sda_5";
1421                                                 function = "i2c_ao";
1422                                                 bias-disable;
1423                                         };
1424                                 };
1425
1426                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1427                                         mux {
1428                                                 groups = "i2c_ao_sda_9";
1429                                                 function = "i2c_ao";
1430                                                 bias-disable;
1431                                         };
1432                                 };
1433
1434                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1435                                         mux {
1436                                                 groups = "i2c_ao_sda_11";
1437                                                 function = "i2c_ao";
1438                                                 bias-disable;
1439                                         };
1440                                 };
1441
1442                                 remote_input_ao_pins: remote_input_ao {
1443                                         mux {
1444                                                 groups = "remote_input_ao";
1445                                                 function = "remote_input_ao";
1446                                                 bias-disable;
1447                                         };
1448                                 };
1449
1450                                 uart_ao_a_pins: uart_ao_a {
1451                                         mux {
1452                                                 groups = "uart_ao_tx_a",
1453                                                          "uart_ao_rx_a";
1454                                                 function = "uart_ao_a";
1455                                                 bias-disable;
1456                                         };
1457                                 };
1458
1459                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1460                                         mux {
1461                                                 groups = "uart_ao_cts_a",
1462                                                          "uart_ao_rts_a";
1463                                                 function = "uart_ao_a";
1464                                                 bias-disable;
1465                                         };
1466                                 };
1467
1468                                 uart_ao_b_pins: uart_ao_b {
1469                                         mux {
1470                                                 groups = "uart_ao_tx_b",
1471                                                          "uart_ao_rx_b";
1472                                                 function = "uart_ao_b";
1473                                                 bias-disable;
1474                                         };
1475                                 };
1476
1477                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1478                                         mux {
1479                                                 groups = "uart_ao_cts_b",
1480                                                          "uart_ao_rts_b";
1481                                                 function = "uart_ao_b";
1482                                                 bias-disable;
1483                                         };
1484                                 };
1485                         };
1486
1487                         sec_AO: ao-secure@140 {
1488                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1489                                 reg = <0x0 0x140 0x0 0x140>;
1490                                 amlogic,has-chip-id;
1491                         };
1492
1493                         pwm_AO_cd: pwm@2000 {
1494                                 compatible = "amlogic,meson-axg-ao-pwm";
1495                                 reg = <0x0 0x02000  0x0 0x20>;
1496                                 #pwm-cells = <3>;
1497                                 status = "disabled";
1498                         };
1499
1500                         uart_AO: serial@3000 {
1501                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1502                                 reg = <0x0 0x3000 0x0 0x18>;
1503                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1504                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1505                                 clock-names = "xtal", "pclk", "baud";
1506                                 status = "disabled";
1507                         };
1508
1509                         uart_AO_B: serial@4000 {
1510                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1511                                 reg = <0x0 0x4000 0x0 0x18>;
1512                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1513                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1514                                 clock-names = "xtal", "pclk", "baud";
1515                                 status = "disabled";
1516                         };
1517
1518                         i2c_AO: i2c@5000 {
1519                                 compatible = "amlogic,meson-axg-i2c";
1520                                 reg = <0x0 0x05000 0x0 0x20>;
1521                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1522                                 clocks = <&clkc CLKID_AO_I2C>;
1523                                 #address-cells = <1>;
1524                                 #size-cells = <0>;
1525                                 status = "disabled";
1526                         };
1527
1528                         pwm_AO_ab: pwm@7000 {
1529                                 compatible = "amlogic,meson-axg-ao-pwm";
1530                                 reg = <0x0 0x07000 0x0 0x20>;
1531                                 #pwm-cells = <3>;
1532                                 status = "disabled";
1533                         };
1534
1535                         ir: ir@8000 {
1536                                 compatible = "amlogic,meson-gxbb-ir";
1537                                 reg = <0x0 0x8000 0x0 0x20>;
1538                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1539                                 status = "disabled";
1540                         };
1541
1542                         saradc: adc@9000 {
1543                                 compatible = "amlogic,meson-axg-saradc",
1544                                         "amlogic,meson-saradc";
1545                                 reg = <0x0 0x9000 0x0 0x38>;
1546                                 #io-channel-cells = <1>;
1547                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1548                                 clocks = <&xtal>,
1549                                          <&clkc_AO CLKID_AO_SAR_ADC>,
1550                                          <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1551                                          <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1552                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1553                                 status = "disabled";
1554                         };
1555                 };
1556
1557                 gic: interrupt-controller@ffc01000 {
1558                         compatible = "arm,gic-400";
1559                         reg = <0x0 0xffc01000 0 0x1000>,
1560                               <0x0 0xffc02000 0 0x2000>,
1561                               <0x0 0xffc04000 0 0x2000>,
1562                               <0x0 0xffc06000 0 0x2000>;
1563                         interrupt-controller;
1564                         interrupts = <GIC_PPI 9
1565                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1566                         #interrupt-cells = <3>;
1567                         #address-cells = <0>;
1568                 };
1569
1570                 cbus: bus@ffd00000 {
1571                         compatible = "simple-bus";
1572                         reg = <0x0 0xffd00000 0x0 0x25000>;
1573                         #address-cells = <2>;
1574                         #size-cells = <2>;
1575                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1576
1577                         reset: reset-controller@1004 {
1578                                 compatible = "amlogic,meson-axg-reset";
1579                                 reg = <0x0 0x01004 0x0 0x9c>;
1580                                 #reset-cells = <1>;
1581                         };
1582
1583                         gpio_intc: interrupt-controller@f080 {
1584                                 compatible = "amlogic,meson-axg-gpio-intc",
1585                                              "amlogic,meson-gpio-intc";
1586                                 reg = <0x0 0xf080 0x0 0x10>;
1587                                 interrupt-controller;
1588                                 #interrupt-cells = <2>;
1589                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1590                         };
1591
1592                         watchdog@f0d0 {
1593                                 compatible = "amlogic,meson-gxbb-wdt";
1594                                 reg = <0x0 0xf0d0 0x0 0x10>;
1595                                 clocks = <&xtal>;
1596                         };
1597
1598                         pwm_ab: pwm@1b000 {
1599                                 compatible = "amlogic,meson-axg-ee-pwm";
1600                                 reg = <0x0 0x1b000 0x0 0x20>;
1601                                 #pwm-cells = <3>;
1602                                 status = "disabled";
1603                         };
1604
1605                         pwm_cd: pwm@1a000 {
1606                                 compatible = "amlogic,meson-axg-ee-pwm";
1607                                 reg = <0x0 0x1a000 0x0 0x20>;
1608                                 #pwm-cells = <3>;
1609                                 status = "disabled";
1610                         };
1611
1612                         spicc0: spi@13000 {
1613                                 compatible = "amlogic,meson-axg-spicc";
1614                                 reg = <0x0 0x13000 0x0 0x3c>;
1615                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1616                                 clocks = <&clkc CLKID_SPICC0>;
1617                                 clock-names = "core";
1618                                 #address-cells = <1>;
1619                                 #size-cells = <0>;
1620                                 status = "disabled";
1621                         };
1622
1623                         spicc1: spi@15000 {
1624                                 compatible = "amlogic,meson-axg-spicc";
1625                                 reg = <0x0 0x15000 0x0 0x3c>;
1626                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1627                                 clocks = <&clkc CLKID_SPICC1>;
1628                                 clock-names = "core";
1629                                 #address-cells = <1>;
1630                                 #size-cells = <0>;
1631                                 status = "disabled";
1632                         };
1633
1634                         clk_msr: clock-measure@18000 {
1635                                 compatible = "amlogic,meson-axg-clk-measure";
1636                                 reg = <0x0 0x18000 0x0 0x10>;
1637                         };
1638
1639                         i2c3: i2c@1c000 {
1640                                 compatible = "amlogic,meson-axg-i2c";
1641                                 reg = <0x0 0x1c000 0x0 0x20>;
1642                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1643                                 clocks = <&clkc CLKID_I2C>;
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646                                 status = "disabled";
1647                         };
1648
1649                         i2c2: i2c@1d000 {
1650                                 compatible = "amlogic,meson-axg-i2c";
1651                                 reg = <0x0 0x1d000 0x0 0x20>;
1652                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1653                                 clocks = <&clkc CLKID_I2C>;
1654                                 #address-cells = <1>;
1655                                 #size-cells = <0>;
1656                                 status = "disabled";
1657                         };
1658
1659                         i2c1: i2c@1e000 {
1660                                 compatible = "amlogic,meson-axg-i2c";
1661                                 reg = <0x0 0x1e000 0x0 0x20>;
1662                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1663                                 clocks = <&clkc CLKID_I2C>;
1664                                 #address-cells = <1>;
1665                                 #size-cells = <0>;
1666                                 status = "disabled";
1667                         };
1668
1669                         i2c0: i2c@1f000 {
1670                                 compatible = "amlogic,meson-axg-i2c";
1671                                 reg = <0x0 0x1f000 0x0 0x20>;
1672                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1673                                 clocks = <&clkc CLKID_I2C>;
1674                                 #address-cells = <1>;
1675                                 #size-cells = <0>;
1676                                 status = "disabled";
1677                         };
1678
1679                         uart_B: serial@23000 {
1680                                 compatible = "amlogic,meson-gx-uart";
1681                                 reg = <0x0 0x23000 0x0 0x18>;
1682                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1683                                 status = "disabled";
1684                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1685                                 clock-names = "xtal", "pclk", "baud";
1686                         };
1687
1688                         uart_A: serial@24000 {
1689                                 compatible = "amlogic,meson-gx-uart";
1690                                 reg = <0x0 0x24000 0x0 0x18>;
1691                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1692                                 status = "disabled";
1693                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1694                                 clock-names = "xtal", "pclk", "baud";
1695                         };
1696                 };
1697
1698                 apb: bus@ffe00000 {
1699                         compatible = "simple-bus";
1700                         reg = <0x0 0xffe00000 0x0 0x200000>;
1701                         #address-cells = <2>;
1702                         #size-cells = <2>;
1703                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1704
1705                         sd_emmc_b: sd@5000 {
1706                                 compatible = "amlogic,meson-axg-mmc";
1707                                 reg = <0x0 0x5000 0x0 0x800>;
1708                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1709                                 status = "disabled";
1710                                 clocks = <&clkc CLKID_SD_EMMC_B>,
1711                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
1712                                         <&clkc CLKID_FCLK_DIV2>;
1713                                 clock-names = "core", "clkin0", "clkin1";
1714                                 resets = <&reset RESET_SD_EMMC_B>;
1715                         };
1716
1717                         sd_emmc_c: mmc@7000 {
1718                                 compatible = "amlogic,meson-axg-mmc";
1719                                 reg = <0x0 0x7000 0x0 0x800>;
1720                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1721                                 status = "disabled";
1722                                 clocks = <&clkc CLKID_SD_EMMC_C>,
1723                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
1724                                         <&clkc CLKID_FCLK_DIV2>;
1725                                 clock-names = "core", "clkin0", "clkin1";
1726                                 resets = <&reset RESET_SD_EMMC_C>;
1727                         };
1728                 };
1729
1730                 sram: sram@fffc0000 {
1731                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1732                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1733                         #address-cells = <1>;
1734                         #size-cells = <1>;
1735                         ranges = <0 0x0 0xfffc0000 0x20000>;
1736
1737                         cpu_scp_lpri: scp-shmem@13000 {
1738                                 compatible = "amlogic,meson-axg-scp-shmem";
1739                                 reg = <0x13000 0x400>;
1740                         };
1741
1742                         cpu_scp_hpri: scp-shmem@13400 {
1743                                 compatible = "amlogic,meson-axg-scp-shmem";
1744                                 reg = <0x13400 0x400>;
1745                         };
1746                 };
1747         };
1748
1749         timer {
1750                 compatible = "arm,armv8-timer";
1751                 interrupts = <GIC_PPI 13
1752                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1753                              <GIC_PPI 14
1754                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1755                              <GIC_PPI 11
1756                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1757                              <GIC_PPI 10
1758                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1759         };
1760
1761         xtal: xtal-clk {
1762                 compatible = "fixed-clock";
1763                 clock-frequency = <24000000>;
1764                 clock-output-names = "xtal";
1765                 #clock-cells = <0>;
1766         };
1767 };