arch/arm64/boot/dts/amlogic/meson-axg-s400.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "meson-axg.dtsi"
   9
  10 / {
  11         compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
  12         model = "Amlogic Meson AXG S400 Development Board";
  13
  14         aliases {
  15                 serial0 = &uart_AO;
  16                 serial1 = &uart_A;
  17         };
  18
  19         vddio_boot: regulator-vddio_boot {
  20                 compatible = "regulator-fixed";
  21                 regulator-name = "VDDIO_BOOT";
  22                 regulator-min-microvolt = <1800000>;
  23                 regulator-max-microvolt = <1800000>;
  24         };
  25
  26         vddao_3v3: regulator-vddao_3v3 {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "VDDAO_3V3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31         };
  32
  33         vddio_ao18: regulator-vddio_ao18 {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "VDDIO_AO18";
  36                 regulator-min-microvolt = <1800000>;
  37                 regulator-max-microvolt = <1800000>;
  38         };
  39
  40         vcc_3v3: regulator-vcc_3v3 {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "VCC_3V3";
  43                 regulator-min-microvolt = <3300000>;
  44                 regulator-max-microvolt = <3300000>;
  45         };
  46
  47         emmc_pwrseq: emmc-pwrseq {
  48                 compatible = "mmc-pwrseq-emmc";
  49                 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
  50         };
  51
  52         sdio_pwrseq: sdio-pwrseq {
  53                 compatible = "mmc-pwrseq-simple";
  54                 reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
  55                 clocks = <&wifi32k>;
  56                 clock-names = "ext_clock";
  57         };
  58
  59         wifi32k: wifi32k {
  60                 compatible = "pwm-clock";
  61                 #clock-cells = <0>;
  62                 clock-frequency = <32768>;
  63                 pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
  64         };
  65 };
  66
  67 &ethmac {
  68         status = "okay";
  69         phy-mode = "rgmii";
  70         pinctrl-0 = <&eth_rgmii_y_pins>;
  71         pinctrl-names = "default";
  72 };
  73
  74 &uart_A {
  75         status = "okay";
  76         pinctrl-0 = <&uart_a_pins>;
  77         pinctrl-names = "default";
  78 };
  79
  80 &uart_AO {
  81         status = "okay";
  82         pinctrl-0 = <&uart_ao_a_pins>;
  83         pinctrl-names = "default";
  84 };
  85
  86 &ir {
  87         status = "okay";
  88         pinctrl-0 = <&remote_input_ao_pins>;
  89         pinctrl-names = "default";
  90 };
  91
  92 &i2c1 {
  93         status = "okay";
  94         pinctrl-0 = <&i2c1_z_pins>;
  95         pinctrl-names = "default";
  96 };
  97
  98 &i2c_AO {
  99         status = "okay";
 100         pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
 101         pinctrl-names = "default";
 102 };
 103
 104 &pwm_ab {
 105         status = "okay";
 106         pinctrl-0 = <&pwm_a_x20_pins>;
 107         pinctrl-names = "default";
 108 };
 109
 110 /* emmc storage */
 111 &sd_emmc_c {
 112         status = "okay";
 113         pinctrl-0 = <&emmc_pins>;
 114         pinctrl-1 = <&emmc_clk_gate_pins>;
 115         pinctrl-names = "default", "clk-gate";
 116
 117         bus-width = <8>;
 118         cap-sd-highspeed;
 119         cap-mmc-highspeed;
 120         max-frequency = <180000000>;
 121         non-removable;
 122         disable-wp;
 123         mmc-ddr-1_8v;
 124         mmc-hs200-1_8v;
 125
 126         vmmc-supply = <&vcc_3v3>;
 127         vqmmc-supply = <&vddio_boot>;
 128 };
 129
 130 /* wifi module */
 131 &sd_emmc_b {
 132         status = "okay";
 133         #address-cells = <1>;
 134         #size-cells = <0>;
 135
 136         pinctrl-0 = <&sdio_pins>;
 137         pinctrl-1 = <&sdio_clk_gate_pins>;
 138         pinctrl-names = "default", "clk-gate";
 139
 140         bus-width = <4>;
 141         cap-sd-highspeed;
 142         max-frequency = <100000000>;
 143         non-removable;
 144         disable-wp;
 145
 146         mmc-pwrseq = <&sdio_pwrseq>;
 147
 148         vmmc-supply = <&vddao_3v3>;
 149         vqmmc-supply = <&vddio_boot>;
 150
 151         brcmf: wifi@1 {
 152                 reg = <1>;
 153                 compatible = "brcm,bcm4329-fmac";
 154         };
 155 };