arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DTS file for AMD Seattle SoC
   4  *
   5  * Copyright (C) 2014 Advanced Micro Devices, Inc.
   6  */
   7
   8 / {
   9         compatible = "amd,seattle";
  10         interrupt-parent = <&gic0>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         gic0: interrupt-controller@e1101000 {
  15                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  16                 interrupt-controller;
  17                 #interrupt-cells = <3>;
  18                 #address-cells = <2>;
  19                 #size-cells = <2>;
  20                 reg = <0x0 0xe1110000 0 0x1000>,
  21                       <0x0 0xe112f000 0 0x2000>,
  22                       <0x0 0xe1140000 0 0x2000>,
  23                       <0x0 0xe1160000 0 0x2000>;
  24                 interrupts = <1 9 0xf04>;
  25                 ranges = <0 0 0 0xe1100000 0 0x100000>;
  26                 v2m0: v2m@e0080000 {
  27                         compatible = "arm,gic-v2m-frame";
  28                         msi-controller;
  29                         reg = <0x0 0x00080000 0 0x1000>;
  30                 };
  31         };
  32
  33         timer {
  34                 compatible = "arm,armv8-timer";
  35                 interrupts = <1 13 0xff04>,
  36                              <1 14 0xff04>,
  37                              <1 11 0xff04>,
  38                              <1 10 0xff04>;
  39         };
  40
  41         pmu {
  42                 compatible = "arm,armv8-pmuv3";
  43                 interrupts = <0 7 4>,
  44                              <0 8 4>,
  45                              <0 9 4>,
  46                              <0 10 4>,
  47                              <0 11 4>,
  48                              <0 12 4>,
  49                              <0 13 4>,
  50                              <0 14 4>;
  51         };
  52
  53         smb0: smb {
  54                 compatible = "simple-bus";
  55                 #address-cells = <2>;
  56                 #size-cells = <2>;
  57                 ranges;
  58
  59                 /*
  60                  * dma-ranges is 40-bit address space containing:
  61                  * - GICv2m MSI register is at 0xe0080000
  62                  * - DRAM range [0x8000000000 to 0xffffffffff]
  63                  */
  64                 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  65
  66                 /include/ "amd-seattle-clks.dtsi"
  67
  68                 sata0: sata@e0300000 {
  69                         compatible = "snps,dwc-ahci";
  70                         reg = <0 0xe0300000 0 0xf0000>;
  71                         interrupts = <0 355 4>;
  72                         clocks = <&sataclk_333mhz>;
  73                         dma-coherent;
  74                 };
  75
  76                 /* This is for Rev B only */
  77                 sata1: sata@e0d00000 {
  78                         status = "disabled";
  79                         compatible = "snps,dwc-ahci";
  80                         reg = <0 0xe0d00000 0 0xf0000>;
  81                         interrupts = <0 354 4>;
  82                         clocks = <&sataclk_333mhz>;
  83                         dma-coherent;
  84                 };
  85
  86                 i2c0: i2c@e1000000 {
  87                         status = "disabled";
  88                         compatible = "snps,designware-i2c";
  89                         reg = <0 0xe1000000 0 0x1000>;
  90                         interrupts = <0 357 4>;
  91                         clocks = <&miscclk_250mhz>;
  92                 };
  93
  94                 i2c1: i2c@e0050000 {
  95                         status = "disabled";
  96                         compatible = "snps,designware-i2c";
  97                         reg = <0 0xe0050000 0 0x1000>;
  98                         interrupts = <0 340 4>;
  99                         clocks = <&miscclk_250mhz>;
 100                 };
 101
 102                 serial0: serial@e1010000 {
 103                         compatible = "arm,pl011", "arm,primecell";
 104                         reg = <0 0xe1010000 0 0x1000>;
 105                         interrupts = <0 328 4>;
 106                         clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
 107                         clock-names = "uartclk", "apb_pclk";
 108                 };
 109
 110                 spi0: ssp@e1020000 {
 111                         status = "disabled";
 112                         compatible = "arm,pl022", "arm,primecell";
 113                         reg = <0 0xe1020000 0 0x1000>;
 114                         spi-controller;
 115                         interrupts = <0 330 4>;
 116                         clocks = <&uartspiclk_100mhz>;
 117                         clock-names = "apb_pclk";
 118                 };
 119
 120                 spi1: ssp@e1030000 {
 121                         status = "disabled";
 122                         compatible = "arm,pl022", "arm,primecell";
 123                         reg = <0 0xe1030000 0 0x1000>;
 124                         spi-controller;
 125                         interrupts = <0 329 4>;
 126                         clocks = <&uartspiclk_100mhz>;
 127                         clock-names = "apb_pclk";
 128                         num-cs = <1>;
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                 };
 132
 133                 gpio0: gpio@e1040000 { /* Not available to OS for B0 */
 134                         status = "disabled";
 135                         compatible = "arm,pl061", "arm,primecell";
 136                         #gpio-cells = <2>;
 137                         reg = <0 0xe1040000 0 0x1000>;
 138                         gpio-controller;
 139                         interrupts = <0 359 4>;
 140                         interrupt-controller;
 141                         #interrupt-cells = <2>;
 142                         clocks = <&miscclk_250mhz>;
 143                         clock-names = "apb_pclk";
 144                 };
 145
 146                 gpio1: gpio@e1050000 { /* [0:7] */
 147                         status = "disabled";
 148                         compatible = "arm,pl061", "arm,primecell";
 149                         #gpio-cells = <2>;
 150                         reg = <0 0xe1050000 0 0x1000>;
 151                         gpio-controller;
 152                         interrupt-controller;
 153                         #interrupt-cells = <2>;
 154                         interrupts = <0 358 4>;
 155                         clocks = <&miscclk_250mhz>;
 156                         clock-names = "apb_pclk";
 157                 };
 158
 159                 gpio2: gpio@e0020000 { /* [8:15] */
 160                         status = "disabled";
 161                         compatible = "arm,pl061", "arm,primecell";
 162                         #gpio-cells = <2>;
 163                         reg = <0 0xe0020000 0 0x1000>;
 164                         gpio-controller;
 165                         interrupt-controller;
 166                         #interrupt-cells = <2>;
 167                         interrupts = <0 366 4>;
 168                         clocks = <&miscclk_250mhz>;
 169                         clock-names = "apb_pclk";
 170                 };
 171
 172                 gpio3: gpio@e0030000 { /* [16:23] */
 173                         status = "disabled";
 174                         compatible = "arm,pl061", "arm,primecell";
 175                         #gpio-cells = <2>;
 176                         reg = <0 0xe0030000 0 0x1000>;
 177                         gpio-controller;
 178                         interrupt-controller;
 179                         #interrupt-cells = <2>;
 180                         interrupts = <0 365 4>;
 181                         clocks = <&miscclk_250mhz>;
 182                         clock-names = "apb_pclk";
 183                 };
 184
 185                 gpio4: gpio@e0080000 { /* [24] */
 186                         status = "disabled";
 187                         compatible = "arm,pl061", "arm,primecell";
 188                         #gpio-cells = <2>;
 189                         reg = <0 0xe0080000 0 0x1000>;
 190                         gpio-controller;
 191                         interrupt-controller;
 192                         #interrupt-cells = <2>;
 193                         interrupts = <0 361 4>;
 194                         clocks = <&miscclk_250mhz>;
 195                         clock-names = "apb_pclk";
 196                 };
 197
 198                 ccp0: ccp@e0100000 {
 199                         status = "disabled";
 200                         compatible = "amd,ccp-seattle-v1a";
 201                         reg = <0 0xe0100000 0 0x10000>;
 202                         interrupts = <0 3 4>;
 203                         dma-coherent;
 204                 };
 205
 206                 pcie0: pcie@f0000000 {
 207                         compatible = "pci-host-ecam-generic";
 208                         #address-cells = <3>;
 209                         #size-cells = <2>;
 210                         #interrupt-cells = <1>;
 211                         device_type = "pci";
 212                         bus-range = <0 0x7f>;
 213                         msi-parent = <&v2m0>;
 214                         reg = <0 0xf0000000 0 0x10000000>;
 215
 216                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 217                         interrupt-map =
 218                                 <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
 219                                 <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
 220                                 <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
 221                                 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
 222
 223                         dma-coherent;
 224                         dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
 225                         ranges =
 226                                 /* I/O Memory (size=64K) */
 227                                 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
 228                                 /* 32-bit MMIO (size=2G) */
 229                                 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
 230                                 /* 64-bit MMIO (size= 124G) */
 231                                 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
 232                 };
 233
 234                 /* Perf CCN504 PMU */
 235                 ccn: ccn@e8000000 {
 236                         compatible = "arm,ccn-504";
 237                         reg = <0x0 0xe8000000 0 0x1000000>;
 238                         interrupts = <0 380 4>;
 239                 };
 240
 241                 ipmi_kcs: kcs@e0010000 {
 242                         status = "disabled";
 243                         compatible = "ipmi-kcs";
 244                         device_type = "ipmi";
 245                         reg = <0x0 0xe0010000 0 0x8>;
 246                         interrupts = <0 389 4>;
 247                         reg-size = <1>;
 248                         reg-spacing = <4>;
 249                 };
 250         };
 251 };