2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
32 compatible = "arm,cortex-a53", "arm,armv8";
34 enable-method = "psci";
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
61 compatible = "arm,armv8-pmuv3";
62 interrupts = <0 120 8>,
66 interrupt-affinity = <&cpu0>,
70 interrupt-parent = <&intc>;
74 compatible = "arm,psci-0.2";
79 compatible = "arm,gic-400", "arm,cortex-a15-gic";
80 #interrupt-cells = <3>;
82 reg = <0x0 0xfffc1000 0x0 0x1000>,
83 <0x0 0xfffc2000 0x0 0x2000>,
84 <0x0 0xfffc4000 0x0 0x2000>,
85 <0x0 0xfffc6000 0x0 0x2000>;
91 compatible = "simple-bus";
93 interrupt-parent = <&intc>;
94 ranges = <0 0 0 0xffffffff>;
96 clkmgr: clock-controller@ffd10000 {
97 compatible = "intel,stratix10-clkmgr";
98 reg = <0xffd10000 0x1000>;
103 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
105 compatible = "fixed-clock";
108 cb_intosc_ls_clk: cb-intosc-ls-clk {
110 compatible = "fixed-clock";
113 f2s_free_clk: f2s-free-clk {
115 compatible = "fixed-clock";
120 compatible = "fixed-clock";
125 compatible = "fixed-clock";
126 clock-frequency = <200000000>;
130 gmac0: ethernet@ff800000 {
131 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
132 reg = <0xff800000 0x2000>;
133 interrupts = <0 90 4>;
134 interrupt-names = "macirq";
135 mac-address = [00 00 00 00 00 00];
136 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
137 reset-names = "stmmaceth", "stmmaceth-ocp";
138 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
139 clock-names = "stmmaceth";
140 tx-fifo-depth = <16384>;
141 rx-fifo-depth = <16384>;
145 gmac1: ethernet@ff802000 {
146 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
147 reg = <0xff802000 0x2000>;
148 interrupts = <0 91 4>;
149 interrupt-names = "macirq";
150 mac-address = [00 00 00 00 00 00];
151 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
152 reset-names = "stmmaceth", "stmmaceth-ocp";
153 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
154 clock-names = "stmmaceth";
155 tx-fifo-depth = <16384>;
156 rx-fifo-depth = <16384>;
160 gmac2: ethernet@ff804000 {
161 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
162 reg = <0xff804000 0x2000>;
163 interrupts = <0 92 4>;
164 interrupt-names = "macirq";
165 mac-address = [00 00 00 00 00 00];
166 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
167 reset-names = "stmmaceth", "stmmaceth-ocp";
168 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
169 clock-names = "stmmaceth";
170 tx-fifo-depth = <16384>;
171 rx-fifo-depth = <16384>;
175 gpio0: gpio@ffc03200 {
176 #address-cells = <1>;
178 compatible = "snps,dw-apb-gpio";
179 reg = <0xffc03200 0x100>;
180 resets = <&rst GPIO0_RESET>;
183 porta: gpio-controller@0 {
184 compatible = "snps,dw-apb-gpio-port";
187 snps,nr-gpios = <24>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 interrupts = <0 110 4>;
195 gpio1: gpio@ffc03300 {
196 #address-cells = <1>;
198 compatible = "snps,dw-apb-gpio";
199 reg = <0xffc03300 0x100>;
200 resets = <&rst GPIO1_RESET>;
203 portb: gpio-controller@0 {
204 compatible = "snps,dw-apb-gpio-port";
207 snps,nr-gpios = <24>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
211 interrupts = <0 111 4>;
216 #address-cells = <1>;
218 compatible = "snps,designware-i2c";
219 reg = <0xffc02800 0x100>;
220 interrupts = <0 103 4>;
221 resets = <&rst I2C0_RESET>;
222 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
227 #address-cells = <1>;
229 compatible = "snps,designware-i2c";
230 reg = <0xffc02900 0x100>;
231 interrupts = <0 104 4>;
232 resets = <&rst I2C1_RESET>;
233 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
238 #address-cells = <1>;
240 compatible = "snps,designware-i2c";
241 reg = <0xffc02a00 0x100>;
242 interrupts = <0 105 4>;
243 resets = <&rst I2C2_RESET>;
244 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
249 #address-cells = <1>;
251 compatible = "snps,designware-i2c";
252 reg = <0xffc02b00 0x100>;
253 interrupts = <0 106 4>;
254 resets = <&rst I2C3_RESET>;
255 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
260 #address-cells = <1>;
262 compatible = "snps,designware-i2c";
263 reg = <0xffc02c00 0x100>;
264 interrupts = <0 107 4>;
265 resets = <&rst I2C4_RESET>;
266 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
270 mmc: dwmmc0@ff808000 {
271 #address-cells = <1>;
273 compatible = "altr,socfpga-dw-mshc";
274 reg = <0xff808000 0x1000>;
275 interrupts = <0 96 4>;
276 fifo-depth = <0x400>;
277 resets = <&rst SDMMC_RESET>;
278 reset-names = "reset";
279 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
280 <&clkmgr STRATIX10_SDMMC_CLK>;
281 clock-names = "biu", "ciu";
285 ocram: sram@ffe00000 {
286 compatible = "mmio-sram";
287 reg = <0xffe00000 0x100000>;
290 pdma: pdma@ffda0000 {
291 compatible = "arm,pl330", "arm,primecell";
292 reg = <0xffda0000 0x1000>;
293 interrupts = <0 81 4>,
304 #dma-requests = <32>;
305 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
306 clock-names = "apb_pclk";
309 rst: rstmgr@ffd11000 {
311 compatible = "altr,rst-mgr";
312 reg = <0xffd11000 0x1000>;
313 altr,modrst-offset = <0x20>;
317 compatible = "snps,dw-apb-ssi";
318 #address-cells = <1>;
320 reg = <0xffda4000 0x1000>;
321 interrupts = <0 99 4>;
322 resets = <&rst SPIM0_RESET>;
325 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
330 compatible = "snps,dw-apb-ssi";
331 #address-cells = <1>;
333 reg = <0xffda5000 0x1000>;
334 interrupts = <0 100 4>;
335 resets = <&rst SPIM1_RESET>;
338 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
342 sysmgr: sysmgr@ffd12000 {
343 compatible = "altr,sys-mgr", "syscon";
344 reg = <0xffd12000 0x228>;
349 compatible = "arm,armv8-timer";
350 interrupts = <1 13 0xf08>,
356 timer0: timer0@ffc03000 {
357 compatible = "snps,dw-apb-timer";
358 interrupts = <0 113 4>;
359 reg = <0xffc03000 0x100>;
360 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
361 clock-names = "timer";
364 timer1: timer1@ffc03100 {
365 compatible = "snps,dw-apb-timer";
366 interrupts = <0 114 4>;
367 reg = <0xffc03100 0x100>;
368 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
369 clock-names = "timer";
372 timer2: timer2@ffd00000 {
373 compatible = "snps,dw-apb-timer";
374 interrupts = <0 115 4>;
375 reg = <0xffd00000 0x100>;
376 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
377 clock-names = "timer";
380 timer3: timer3@ffd00100 {
381 compatible = "snps,dw-apb-timer";
382 interrupts = <0 116 4>;
383 reg = <0xffd00100 0x100>;
384 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
385 clock-names = "timer";
388 uart0: serial0@ffc02000 {
389 compatible = "snps,dw-apb-uart";
390 reg = <0xffc02000 0x100>;
391 interrupts = <0 108 4>;
394 resets = <&rst UART0_RESET>;
395 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
399 uart1: serial1@ffc02100 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0xffc02100 0x100>;
402 interrupts = <0 109 4>;
405 resets = <&rst UART1_RESET>;
406 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
412 compatible = "usb-nop-xceiv";
417 compatible = "snps,dwc2";
418 reg = <0xffb00000 0x40000>;
419 interrupts = <0 93 4>;
421 phy-names = "usb2-phy";
422 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
423 reset-names = "dwc2", "dwc2-ecc";
424 clocks = <&clkmgr STRATIX10_USB_CLK>;
429 compatible = "snps,dwc2";
430 reg = <0xffb40000 0x40000>;
431 interrupts = <0 94 4>;
433 phy-names = "usb2-phy";
434 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
435 reset-names = "dwc2", "dwc2-ecc";
436 clocks = <&clkmgr STRATIX10_USB_CLK>;
440 watchdog0: watchdog@ffd00200 {
441 compatible = "snps,dw-wdt";
442 reg = <0xffd00200 0x100>;
443 interrupts = <0 117 4>;
444 resets = <&rst WATCHDOG0_RESET>;
445 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
449 watchdog1: watchdog@ffd00300 {
450 compatible = "snps,dw-wdt";
451 reg = <0xffd00300 0x100>;
452 interrupts = <0 118 4>;
453 resets = <&rst WATCHDOG1_RESET>;
454 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
458 watchdog2: watchdog@ffd00400 {
459 compatible = "snps,dw-wdt";
460 reg = <0xffd00400 0x100>;
461 interrupts = <0 125 4>;
462 resets = <&rst WATCHDOG2_RESET>;
463 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
467 watchdog3: watchdog@ffd00500 {
468 compatible = "snps,dw-wdt";
469 reg = <0xffd00500 0x100>;
470 interrupts = <0 126 4>;
471 resets = <&rst WATCHDOG3_RESET>;
472 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
477 compatible = "altr,sdr-ctl", "syscon";
478 reg = <0xf8011100 0xc0>;
482 compatible = "altr,socfpga-a10-ecc-manager";
483 altr,sysmgr-syscon = <&sysmgr>;
484 #address-cells = <1>;
486 interrupts = <0 15 4>, <0 95 4>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
492 compatible = "altr,sdram-edac-s10";
493 altr,sdr-syscon = <&sdr>;
494 interrupts = <16 4>, <48 4>;
498 compatible = "altr,socfpga-usb-ecc";
499 reg = <0xff8c4000 0x100>;
500 altr,ecc-parent = <&usb0>;
505 emac0-rx-ecc@ff8c0000 {
506 compatible = "altr,socfpga-eth-mac-ecc";
507 reg = <0xff8c0000 0x100>;
508 altr,ecc-parent = <&gmac0>;
513 emac0-tx-ecc@ff8c0400 {
514 compatible = "altr,socfpga-eth-mac-ecc";
515 reg = <0xff8c0400 0x100>;
516 altr,ecc-parent = <&gmac0>;
524 compatible = "cdns,qspi-nor";
525 #address-cells = <1>;
527 reg = <0xff8d2000 0x100>,
528 <0xff900000 0x100000>;
529 interrupts = <0 3 4>;
530 cdns,fifo-depth = <128>;
531 cdns,fifo-width = <4>;
532 cdns,trigger-address = <0x00000000>;
533 clocks = <&qspi_clk>;