1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun8i-de2.h>
10 #include <dt-bindings/clock/sun8i-tcon-top.h>
11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 #include <dt-bindings/reset/sun8i-de2.h>
16 interrupt-parent = <&gic>;
25 compatible = "arm,cortex-a53";
28 enable-method = "psci";
32 compatible = "arm,cortex-a53";
35 enable-method = "psci";
39 compatible = "arm,cortex-a53";
42 enable-method = "psci";
46 compatible = "arm,cortex-a53";
49 enable-method = "psci";
54 compatible = "allwinner,sun50i-h6-display-engine";
55 allwinner,pipelines = <&mixer0>;
61 compatible = "fixed-clock";
62 clock-frequency = <24000000>;
63 clock-output-names = "osc24M";
66 ext_osc32k: ext_osc32k_clk {
68 compatible = "fixed-clock";
69 clock-frequency = <32768>;
70 clock-output-names = "ext_osc32k";
74 compatible = "arm,psci-0.2";
79 compatible = "arm,armv8-timer";
80 interrupts = <GIC_PPI 13
81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
85 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
87 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
91 compatible = "simple-bus";
97 compatible = "allwinner,sun50i-h6-de3",
98 "allwinner,sun50i-a64-de2";
99 reg = <0x1000000 0x400000>;
100 allwinner,sram = <&de2_sram 1>;
101 #address-cells = <1>;
103 ranges = <0 0x1000000 0x400000>;
105 display_clocks: clock@0 {
106 compatible = "allwinner,sun50i-h6-de3-clk";
108 clocks = <&ccu CLK_DE>,
112 resets = <&ccu RST_BUS_DE>;
117 mixer0: mixer@100000 {
118 compatible = "allwinner,sun50i-h6-de3-mixer-0";
119 reg = <0x100000 0x100000>;
120 clocks = <&display_clocks CLK_BUS_MIXER0>,
121 <&display_clocks CLK_MIXER0>;
124 resets = <&display_clocks RST_MIXER0>;
127 #address-cells = <1>;
133 mixer0_out_tcon_top_mixer0: endpoint {
134 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
141 video-codec@1c0e000 {
142 compatible = "allwinner,sun50i-h6-video-engine";
143 reg = <0x01c0e000 0x2000>;
144 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
146 clock-names = "ahb", "mod", "ram";
147 resets = <&ccu RST_BUS_VE>;
148 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
149 allwinner,sram = <&ve_sram 1>;
152 syscon: syscon@3000000 {
153 compatible = "allwinner,sun50i-h6-system-control",
154 "allwinner,sun50i-a64-system-control";
155 reg = <0x03000000 0x1000>;
156 #address-cells = <1>;
161 compatible = "mmio-sram";
162 reg = <0x00028000 0x1e000>;
163 #address-cells = <1>;
165 ranges = <0 0x00028000 0x1e000>;
167 de2_sram: sram-section@0 {
168 compatible = "allwinner,sun50i-h6-sram-c",
169 "allwinner,sun50i-a64-sram-c";
170 reg = <0x0000 0x1e000>;
174 sram_c1: sram@1a00000 {
175 compatible = "mmio-sram";
176 reg = <0x01a00000 0x200000>;
177 #address-cells = <1>;
179 ranges = <0 0x01a00000 0x200000>;
181 ve_sram: sram-section@0 {
182 compatible = "allwinner,sun50i-h6-sram-c1",
183 "allwinner,sun4i-a10-sram-c1";
184 reg = <0x000000 0x200000>;
190 compatible = "allwinner,sun50i-h6-ccu";
191 reg = <0x03001000 0x1000>;
192 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
193 clock-names = "hosc", "losc", "iosc";
198 dma: dma-controller@3002000 {
199 compatible = "allwinner,sun50i-h6-dma";
200 reg = <0x03002000 0x1000>;
201 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
203 clock-names = "bus", "mbus";
206 resets = <&ccu RST_BUS_DMA>;
211 compatible = "allwinner,sun50i-h6-sid";
212 reg = <0x03006000 0x400>;
215 watchdog: watchdog@30090a0 {
216 compatible = "allwinner,sun50i-h6-wdt",
217 "allwinner,sun6i-a31-wdt";
218 reg = <0x030090a0 0x20>;
219 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
221 /* Broken on some H6 boards */
225 pio: pinctrl@300b000 {
226 compatible = "allwinner,sun50i-h6-pinctrl";
227 reg = <0x0300b000 0x400>;
228 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
233 clock-names = "apb", "hosc", "losc";
236 interrupt-controller;
237 #interrupt-cells = <3>;
239 ext_rgmii_pins: rgmii-pins {
240 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
241 "PD5", "PD7", "PD8", "PD9", "PD10",
242 "PD11", "PD12", "PD13", "PD19", "PD20";
244 drive-strength = <40>;
247 hdmi_pins: hdmi-pins {
248 pins = "PH8", "PH9", "PH10";
252 i2c0_pins: i2c0-pins {
253 pins = "PD25", "PD26";
257 i2c1_pins: i2c1-pins {
262 i2c2_pins: i2c2-pins {
263 pins = "PD23", "PD24";
267 mmc0_pins: mmc0-pins {
268 pins = "PF0", "PF1", "PF2", "PF3",
271 drive-strength = <30>;
276 mmc1_pins: mmc1-pins {
277 pins = "PG0", "PG1", "PG2", "PG3",
280 drive-strength = <30>;
284 mmc2_pins: mmc2-pins {
285 pins = "PC1", "PC4", "PC5", "PC6",
286 "PC7", "PC8", "PC9", "PC10",
287 "PC11", "PC12", "PC13", "PC14";
289 drive-strength = <30>;
293 spdif_tx_pin: spdif-tx-pin {
298 uart0_ph_pins: uart0-ph-pins {
304 gic: interrupt-controller@3021000 {
305 compatible = "arm,gic-400";
306 reg = <0x03021000 0x1000>,
310 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
311 interrupt-controller;
312 #interrupt-cells = <3>;
316 compatible = "allwinner,sun50i-h6-mmc",
317 "allwinner,sun50i-a64-mmc";
318 reg = <0x04020000 0x1000>;
319 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
320 clock-names = "ahb", "mmc";
321 resets = <&ccu RST_BUS_MMC0>;
323 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&mmc0_pins>;
327 #address-cells = <1>;
332 compatible = "allwinner,sun50i-h6-mmc",
333 "allwinner,sun50i-a64-mmc";
334 reg = <0x04021000 0x1000>;
335 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
336 clock-names = "ahb", "mmc";
337 resets = <&ccu RST_BUS_MMC1>;
339 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&mmc1_pins>;
343 #address-cells = <1>;
348 compatible = "allwinner,sun50i-h6-emmc",
349 "allwinner,sun50i-a64-emmc";
350 reg = <0x04022000 0x1000>;
351 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
352 clock-names = "ahb", "mmc";
353 resets = <&ccu RST_BUS_MMC2>;
355 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&mmc2_pins>;
359 #address-cells = <1>;
363 uart0: serial@5000000 {
364 compatible = "snps,dw-apb-uart";
365 reg = <0x05000000 0x400>;
366 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&ccu CLK_BUS_UART0>;
370 resets = <&ccu RST_BUS_UART0>;
374 uart1: serial@5000400 {
375 compatible = "snps,dw-apb-uart";
376 reg = <0x05000400 0x400>;
377 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&ccu CLK_BUS_UART1>;
381 resets = <&ccu RST_BUS_UART1>;
385 uart2: serial@5000800 {
386 compatible = "snps,dw-apb-uart";
387 reg = <0x05000800 0x400>;
388 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&ccu CLK_BUS_UART2>;
392 resets = <&ccu RST_BUS_UART2>;
396 uart3: serial@5000c00 {
397 compatible = "snps,dw-apb-uart";
398 reg = <0x05000c00 0x400>;
399 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&ccu CLK_BUS_UART3>;
403 resets = <&ccu RST_BUS_UART3>;
408 compatible = "allwinner,sun50i-h6-i2c",
409 "allwinner,sun6i-a31-i2c";
410 reg = <0x05002000 0x400>;
411 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&ccu CLK_BUS_I2C0>;
413 resets = <&ccu RST_BUS_I2C0>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&i2c0_pins>;
417 #address-cells = <1>;
422 compatible = "allwinner,sun50i-h6-i2c",
423 "allwinner,sun6i-a31-i2c";
424 reg = <0x05002400 0x400>;
425 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&ccu CLK_BUS_I2C1>;
427 resets = <&ccu RST_BUS_I2C1>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c1_pins>;
431 #address-cells = <1>;
436 compatible = "allwinner,sun50i-h6-i2c",
437 "allwinner,sun6i-a31-i2c";
438 reg = <0x05002800 0x400>;
439 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&ccu CLK_BUS_I2C2>;
441 resets = <&ccu RST_BUS_I2C2>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2c2_pins>;
445 #address-cells = <1>;
449 emac: ethernet@5020000 {
450 compatible = "allwinner,sun50i-h6-emac",
451 "allwinner,sun50i-a64-emac";
453 reg = <0x05020000 0x10000>;
454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-names = "macirq";
456 resets = <&ccu RST_BUS_EMAC>;
457 reset-names = "stmmaceth";
458 clocks = <&ccu CLK_BUS_EMAC>;
459 clock-names = "stmmaceth";
463 compatible = "snps,dwmac-mdio";
464 #address-cells = <1>;
469 spdif: spdif@5093000 {
470 #sound-dai-cells = <0>;
471 compatible = "allwinner,sun50i-h6-spdif";
472 reg = <0x05093000 0x400>;
473 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
475 clock-names = "apb", "spdif";
476 resets = <&ccu RST_BUS_SPDIF>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&spdif_tx_pin>;
484 usb2otg: usb@5100000 {
485 compatible = "allwinner,sun50i-h6-musb",
486 "allwinner,sun8i-a33-musb";
487 reg = <0x05100000 0x0400>;
488 clocks = <&ccu CLK_BUS_OTG>;
489 resets = <&ccu RST_BUS_OTG>;
490 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-names = "mc";
494 extcon = <&usb2phy 0>;
498 usb2phy: phy@5100400 {
499 compatible = "allwinner,sun50i-h6-usb-phy";
500 reg = <0x05100400 0x24>,
503 reg-names = "phy_ctrl",
506 clocks = <&ccu CLK_USB_PHY0>,
508 clock-names = "usb0_phy",
510 resets = <&ccu RST_USB_PHY0>,
512 reset-names = "usb0_reset",
519 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
520 reg = <0x05101000 0x100>;
521 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&ccu CLK_BUS_OHCI0>,
523 <&ccu CLK_BUS_EHCI0>,
524 <&ccu CLK_USB_OHCI0>;
525 resets = <&ccu RST_BUS_OHCI0>,
526 <&ccu RST_BUS_EHCI0>;
531 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
532 reg = <0x05101400 0x100>;
533 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&ccu CLK_BUS_OHCI0>,
535 <&ccu CLK_USB_OHCI0>;
536 resets = <&ccu RST_BUS_OHCI0>;
541 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
542 reg = <0x05311000 0x100>;
543 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&ccu CLK_BUS_OHCI3>,
545 <&ccu CLK_BUS_EHCI3>,
546 <&ccu CLK_USB_OHCI3>;
547 resets = <&ccu RST_BUS_OHCI3>,
548 <&ccu RST_BUS_EHCI3>;
554 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
555 reg = <0x05311400 0x100>;
556 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&ccu CLK_BUS_OHCI3>,
558 <&ccu CLK_USB_OHCI3>;
559 resets = <&ccu RST_BUS_OHCI3>;
565 compatible = "allwinner,sun50i-h6-dw-hdmi";
566 reg = <0x06000000 0x10000>;
568 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
570 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
571 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
572 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
574 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
575 reset-names = "ctrl", "hdcp";
578 pinctrl-names = "default";
579 pinctrl-0 = <&hdmi_pins>;
583 #address-cells = <1>;
589 hdmi_in_tcon_top: endpoint {
590 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
600 hdmi_phy: hdmi-phy@6010000 {
601 compatible = "allwinner,sun50i-h6-hdmi-phy";
602 reg = <0x06010000 0x10000>;
603 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
604 clock-names = "bus", "mod";
605 resets = <&ccu RST_BUS_HDMI>;
610 tcon_top: tcon-top@6510000 {
611 compatible = "allwinner,sun50i-h6-tcon-top";
612 reg = <0x06510000 0x1000>;
613 clocks = <&ccu CLK_BUS_TCON_TOP>,
617 clock-output-names = "tcon-top-tv0";
618 resets = <&ccu RST_BUS_TCON_TOP>;
623 #address-cells = <1>;
626 tcon_top_mixer0_in: port@0 {
627 #address-cells = <1>;
631 tcon_top_mixer0_in_mixer0: endpoint@0 {
633 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
637 tcon_top_mixer0_out: port@1 {
638 #address-cells = <1>;
642 tcon_top_mixer0_out_tcon_tv: endpoint@2 {
644 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
648 tcon_top_hdmi_in: port@4 {
649 #address-cells = <1>;
653 tcon_top_hdmi_in_tcon_tv: endpoint@0 {
655 remote-endpoint = <&tcon_tv_out_tcon_top>;
659 tcon_top_hdmi_out: port@5 {
662 tcon_top_hdmi_out_hdmi: endpoint {
663 remote-endpoint = <&hdmi_in_tcon_top>;
669 tcon_tv: lcd-controller@6515000 {
670 compatible = "allwinner,sun50i-h6-tcon-tv",
671 "allwinner,sun8i-r40-tcon-tv";
672 reg = <0x06515000 0x1000>;
673 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&ccu CLK_BUS_TCON_TV0>,
675 <&tcon_top CLK_TCON_TOP_TV0>;
678 resets = <&ccu RST_BUS_TCON_TV0>;
682 #address-cells = <1>;
688 tcon_tv_in_tcon_top_mixer0: endpoint {
689 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
693 tcon_tv_out: port@1 {
694 #address-cells = <1>;
698 tcon_tv_out_tcon_top: endpoint@1 {
700 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
707 compatible = "allwinner,sun50i-h6-rtc";
708 reg = <0x07000000 0x400>;
709 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
711 clock-output-names = "osc32k", "osc32k-out", "iosc";
712 clocks = <&ext_osc32k>;
716 r_ccu: clock@7010000 {
717 compatible = "allwinner,sun50i-h6-r-ccu";
718 reg = <0x07010000 0x400>;
719 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
720 <&ccu CLK_PLL_PERIPH0>;
721 clock-names = "hosc", "losc", "iosc", "pll-periph";
726 r_watchdog: watchdog@7020400 {
727 compatible = "allwinner,sun50i-h6-wdt",
728 "allwinner,sun6i-a31-wdt";
729 reg = <0x07020400 0x20>;
730 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
734 r_intc: interrupt-controller@7021000 {
735 compatible = "allwinner,sun50i-h6-r-intc",
736 "allwinner,sun6i-a31-r-intc";
737 interrupt-controller;
738 #interrupt-cells = <2>;
739 reg = <0x07021000 0x400>;
740 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
743 r_pio: pinctrl@7022000 {
744 compatible = "allwinner,sun50i-h6-r-pinctrl";
745 reg = <0x07022000 0x400>;
746 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
749 clock-names = "apb", "hosc", "losc";
752 interrupt-controller;
753 #interrupt-cells = <3>;
755 r_i2c_pins: r-i2c-pins {
760 r_ir_rx_pin: r-ir-rx-pin {
762 function = "s_cir_rx";
767 compatible = "allwinner,sun50i-h6-ir",
768 "allwinner,sun6i-a31-ir";
769 reg = <0x07040000 0x400>;
770 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&r_ccu CLK_R_APB1_IR>,
773 clock-names = "apb", "ir";
774 resets = <&r_ccu RST_R_APB1_IR>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&r_ir_rx_pin>;
781 compatible = "allwinner,sun50i-h6-i2c",
782 "allwinner,sun6i-a31-i2c";
783 reg = <0x07081400 0x400>;
784 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&r_ccu CLK_R_APB2_I2C>;
786 resets = <&r_ccu RST_R_APB2_I2C>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&r_i2c_pins>;
790 #address-cells = <1>;