arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi

   1 /*
   2  * Copyright (C) 2016 ARM Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <arm/sunxi-h3-h5.dtsi>
  44
  45 / {
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         compatible = "arm,cortex-a53";
  52                         device_type = "cpu";
  53                         reg = <0>;
  54                         enable-method = "psci";
  55                 };
  56
  57                 cpu@1 {
  58                         compatible = "arm,cortex-a53";
  59                         device_type = "cpu";
  60                         reg = <1>;
  61                         enable-method = "psci";
  62                 };
  63
  64                 cpu@2 {
  65                         compatible = "arm,cortex-a53";
  66                         device_type = "cpu";
  67                         reg = <2>;
  68                         enable-method = "psci";
  69                 };
  70
  71                 cpu@3 {
  72                         compatible = "arm,cortex-a53";
  73                         device_type = "cpu";
  74                         reg = <3>;
  75                         enable-method = "psci";
  76                 };
  77         };
  78
  79         psci {
  80                 compatible = "arm,psci-0.2";
  81                 method = "smc";
  82         };
  83
  84         timer {
  85                 compatible = "arm,armv8-timer";
  86                 interrupts = <GIC_PPI 13
  87                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 14
  89                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 11
  91                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10
  93                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  94         };
  95
  96         soc {
  97                 syscon: system-control@1c00000 {
  98                         compatible = "allwinner,sun50i-h5-system-control";
  99                         reg = <0x01c00000 0x1000>;
 100                         #address-cells = <1>;
 101                         #size-cells = <1>;
 102                         ranges;
 103
 104                         sram_c1: sram@18000 {
 105                                 compatible = "mmio-sram";
 106                                 reg = <0x00018000 0x1c000>;
 107                                 #address-cells = <1>;
 108                                 #size-cells = <1>;
 109                                 ranges = <0 0x00018000 0x1c000>;
 110
 111                                 ve_sram: sram-section@0 {
 112                                         compatible = "allwinner,sun50i-h5-sram-c1",
 113                                                      "allwinner,sun4i-a10-sram-c1";
 114                                         reg = <0x000000 0x1c000>;
 115                                 };
 116                         };
 117                 };
 118
 119                 video-codec@1c0e000 {
 120                         compatible = "allwinner,sun50i-h5-video-engine";
 121                         reg = <0x01c0e000 0x1000>;
 122                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 123                                  <&ccu CLK_DRAM_VE>;
 124                         clock-names = "ahb", "mod", "ram";
 125                         resets = <&ccu RST_BUS_VE>;
 126                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 127                         allwinner,sram = <&ve_sram 1>;
 128                 };
 129
 130                 mali: gpu@1e80000 {
 131                         compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
 132                         reg = <0x01e80000 0x30000>;
 133                         /*
 134                          * While the datasheet lists an interrupt for the
 135                          * PMU, the actual silicon does not have the PMU
 136                          * block. Reads all return zero, and writes are
 137                          * ignored.
 138                          */
 139                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 141                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 144                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 147                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "gp",
 152                                           "gpmmu",
 153                                           "pp",
 154                                           "pp0",
 155                                           "ppmmu0",
 156                                           "pp1",
 157                                           "ppmmu1",
 158                                           "pp2",
 159                                           "ppmmu2",
 160                                           "pp3",
 161                                           "ppmmu3",
 162                                           "pmu";
 163                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 164                         clock-names = "bus", "core";
 165                         resets = <&ccu RST_BUS_GPU>;
 166
 167                         assigned-clocks = <&ccu CLK_GPU>;
 168                         assigned-clock-rates = <384000000>;
 169                 };
 170         };
 171 };
 172
 173 &ccu {
 174         compatible = "allwinner,sun50i-h5-ccu";
 175 };
 176
 177 &display_clocks {
 178         compatible = "allwinner,sun50i-h5-de2-clk";
 179 };
 180
 181 &mmc0 {
 182         compatible = "allwinner,sun50i-h5-mmc",
 183                      "allwinner,sun50i-a64-mmc";
 184         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 185         clock-names = "ahb", "mmc";
 186 };
 187
 188 &mmc1 {
 189         compatible = "allwinner,sun50i-h5-mmc",
 190                      "allwinner,sun50i-a64-mmc";
 191         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 192         clock-names = "ahb", "mmc";
 193 };
 194
 195 &mmc2 {
 196         compatible = "allwinner,sun50i-h5-emmc",
 197                      "allwinner,sun50i-a64-emmc";
 198         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 199         clock-names = "ahb", "mmc";
 200 };
 201
 202 &pio {
 203         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 204                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 205                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 206         compatible = "allwinner,sun50i-h5-pinctrl";
 207 };
 208
 209 &rtc {
 210         compatible = "allwinner,sun50i-h5-rtc";
 211 };