arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

   1 /*
   2  * Copyright (C) 2016 ARM Ltd.
   3  * based on the Allwinner H3 dtsi:
   4  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
  46 #include <dt-bindings/clock/sun8i-r-ccu.h>
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu0: cpu@0 {
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         device_type = "cpu";
  62                         reg = <0>;
  63                         enable-method = "psci";
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         device_type = "cpu";
  69                         reg = <1>;
  70                         enable-method = "psci";
  71                 };
  72
  73                 cpu2: cpu@2 {
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         device_type = "cpu";
  76                         reg = <2>;
  77                         enable-method = "psci";
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         device_type = "cpu";
  83                         reg = <3>;
  84                         enable-method = "psci";
  85                 };
  86         };
  87
  88         osc24M: osc24M_clk {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <24000000>;
  92                 clock-output-names = "osc24M";
  93         };
  94
  95         osc32k: osc32k_clk {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99                 clock-output-names = "osc32k";
 100         };
 101
 102         iosc: internal-osc-clk {
 103                 #clock-cells = <0>;
 104                 compatible = "fixed-clock";
 105                 clock-frequency = <16000000>;
 106                 clock-accuracy = <300000000>;
 107                 clock-output-names = "iosc";
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         timer {
 116                 compatible = "arm,armv8-timer";
 117                 interrupts = <GIC_PPI 13
 118                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 119                              <GIC_PPI 14
 120                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 121                              <GIC_PPI 11
 122                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 123                              <GIC_PPI 10
 124                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 125         };
 126
 127         soc {
 128                 compatible = "simple-bus";
 129                 #address-cells = <1>;
 130                 #size-cells = <1>;
 131                 ranges;
 132
 133                 syscon: syscon@1c00000 {
 134                         compatible = "allwinner,sun50i-a64-system-controller",
 135                                 "syscon";
 136                         reg = <0x01c00000 0x1000>;
 137                 };
 138
 139                 mmc0: mmc@1c0f000 {
 140                         compatible = "allwinner,sun50i-a64-mmc";
 141                         reg = <0x01c0f000 0x1000>;
 142                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 143                         clock-names = "ahb", "mmc";
 144                         resets = <&ccu RST_BUS_MMC0>;
 145                         reset-names = "ahb";
 146                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 147                         max-frequency = <150000000>;
 148                         status = "disabled";
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                 };
 152
 153                 mmc1: mmc@1c10000 {
 154                         compatible = "allwinner,sun50i-a64-mmc";
 155                         reg = <0x01c10000 0x1000>;
 156                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 157                         clock-names = "ahb", "mmc";
 158                         resets = <&ccu RST_BUS_MMC1>;
 159                         reset-names = "ahb";
 160                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 161                         max-frequency = <150000000>;
 162                         status = "disabled";
 163                         #address-cells = <1>;
 164                         #size-cells = <0>;
 165                 };
 166
 167                 mmc2: mmc@1c11000 {
 168                         compatible = "allwinner,sun50i-a64-emmc";
 169                         reg = <0x01c11000 0x1000>;
 170                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 171                         clock-names = "ahb", "mmc";
 172                         resets = <&ccu RST_BUS_MMC2>;
 173                         reset-names = "ahb";
 174                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 175                         max-frequency = <200000000>;
 176                         status = "disabled";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                 };
 180
 181                 usb_otg: usb@01c19000 {
 182                         compatible = "allwinner,sun8i-a33-musb";
 183                         reg = <0x01c19000 0x0400>;
 184                         clocks = <&ccu CLK_BUS_OTG>;
 185                         resets = <&ccu RST_BUS_OTG>;
 186                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 187                         interrupt-names = "mc";
 188                         phys = <&usbphy 0>;
 189                         phy-names = "usb";
 190                         extcon = <&usbphy 0>;
 191                         status = "disabled";
 192                 };
 193
 194                 usbphy: phy@01c19400 {
 195                         compatible = "allwinner,sun50i-a64-usb-phy";
 196                         reg = <0x01c19400 0x14>,
 197                               <0x01c1a800 0x4>,
 198                               <0x01c1b800 0x4>;
 199                         reg-names = "phy_ctrl",
 200                                     "pmu0",
 201                                     "pmu1";
 202                         clocks = <&ccu CLK_USB_PHY0>,
 203                                  <&ccu CLK_USB_PHY1>;
 204                         clock-names = "usb0_phy",
 205                                       "usb1_phy";
 206                         resets = <&ccu RST_USB_PHY0>,
 207                                  <&ccu RST_USB_PHY1>;
 208                         reset-names = "usb0_reset",
 209                                       "usb1_reset";
 210                         status = "disabled";
 211                         #phy-cells = <1>;
 212                 };
 213
 214                 ehci0: usb@01c1a000 {
 215                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 216                         reg = <0x01c1a000 0x100>;
 217                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&ccu CLK_BUS_OHCI0>,
 219                                  <&ccu CLK_BUS_EHCI0>,
 220                                  <&ccu CLK_USB_OHCI0>;
 221                         resets = <&ccu RST_BUS_OHCI0>,
 222                                  <&ccu RST_BUS_EHCI0>;
 223                         status = "disabled";
 224                 };
 225
 226                 ohci0: usb@01c1a400 {
 227                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 228                         reg = <0x01c1a400 0x100>;
 229                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 230                         clocks = <&ccu CLK_BUS_OHCI0>,
 231                                  <&ccu CLK_USB_OHCI0>;
 232                         resets = <&ccu RST_BUS_OHCI0>;
 233                         status = "disabled";
 234                 };
 235
 236                 ehci1: usb@01c1b000 {
 237                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 238                         reg = <0x01c1b000 0x100>;
 239                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 240                         clocks = <&ccu CLK_BUS_OHCI1>,
 241                                  <&ccu CLK_BUS_EHCI1>,
 242                                  <&ccu CLK_USB_OHCI1>;
 243                         resets = <&ccu RST_BUS_OHCI1>,
 244                                  <&ccu RST_BUS_EHCI1>;
 245                         phys = <&usbphy 1>;
 246                         phy-names = "usb";
 247                         status = "disabled";
 248                 };
 249
 250                 ohci1: usb@01c1b400 {
 251                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 252                         reg = <0x01c1b400 0x100>;
 253                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&ccu CLK_BUS_OHCI1>,
 255                                  <&ccu CLK_USB_OHCI1>;
 256                         resets = <&ccu RST_BUS_OHCI1>;
 257                         phys = <&usbphy 1>;
 258                         phy-names = "usb";
 259                         status = "disabled";
 260                 };
 261
 262                 ccu: clock@01c20000 {
 263                         compatible = "allwinner,sun50i-a64-ccu";
 264                         reg = <0x01c20000 0x400>;
 265                         clocks = <&osc24M>, <&osc32k>;
 266                         clock-names = "hosc", "losc";
 267                         #clock-cells = <1>;
 268                         #reset-cells = <1>;
 269                 };
 270
 271                 pio: pinctrl@1c20800 {
 272                         compatible = "allwinner,sun50i-a64-pinctrl";
 273                         reg = <0x01c20800 0x400>;
 274                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 277                         clocks = <&ccu 58>;
 278                         gpio-controller;
 279                         #gpio-cells = <3>;
 280                         interrupt-controller;
 281                         #interrupt-cells = <3>;
 282
 283                         i2c1_pins: i2c1_pins {
 284                                 pins = "PH2", "PH3";
 285                                 function = "i2c1";
 286                         };
 287
 288                         mmc0_pins: mmc0-pins {
 289                                 pins = "PF0", "PF1", "PF2", "PF3",
 290                                        "PF4", "PF5";
 291                                 function = "mmc0";
 292                                 drive-strength = <30>;
 293                                 bias-pull-up;
 294                         };
 295
 296                         mmc1_pins: mmc1-pins {
 297                                 pins = "PG0", "PG1", "PG2", "PG3",
 298                                        "PG4", "PG5";
 299                                 function = "mmc1";
 300                                 drive-strength = <30>;
 301                                 bias-pull-up;
 302                         };
 303
 304                         mmc2_pins: mmc2-pins {
 305                                 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
 306                                        "PC10","PC11", "PC12", "PC13",
 307                                        "PC14", "PC15", "PC16";
 308                                 function = "mmc2";
 309                                 drive-strength = <30>;
 310                                 bias-pull-up;
 311                         };
 312
 313                         rmii_pins: rmii_pins {
 314                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 315                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 316                                 function = "emac";
 317                                 drive-strength = <40>;
 318                         };
 319
 320                         rgmii_pins: rgmii_pins {
 321                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 322                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 323                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 324                                 function = "emac";
 325                                 drive-strength = <40>;
 326                         };
 327
 328                         uart0_pins_a: uart0@0 {
 329                                 pins = "PB8", "PB9";
 330                                 function = "uart0";
 331                         };
 332
 333                         uart1_pins: uart1_pins {
 334                                 pins = "PG6", "PG7";
 335                                 function = "uart1";
 336                         };
 337
 338                         uart1_rts_cts_pins: uart1_rts_cts_pins {
 339                                 pins = "PG8", "PG9";
 340                                 function = "uart1";
 341                         };
 342
 343                         uart2_pins: uart2-pins {
 344                                 pins = "PB0", "PB1";
 345                                 function = "uart2";
 346                         };
 347
 348                         uart3_pins: uart3-pins {
 349                                 pins = "PD0", "PD1";
 350                                 function = "uart3";
 351                         };
 352
 353                         uart4_pins: uart4-pins {
 354                                 pins = "PD2", "PD3";
 355                                 function = "uart4";
 356                         };
 357
 358                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 359                                 pins = "PD4", "PD5";
 360                                 function = "uart4";
 361                         };
 362                 };
 363
 364                 uart0: serial@1c28000 {
 365                         compatible = "snps,dw-apb-uart";
 366                         reg = <0x01c28000 0x400>;
 367                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 368                         reg-shift = <2>;
 369                         reg-io-width = <4>;
 370                         clocks = <&ccu CLK_BUS_UART0>;
 371                         resets = <&ccu RST_BUS_UART0>;
 372                         status = "disabled";
 373                 };
 374
 375                 uart1: serial@1c28400 {
 376                         compatible = "snps,dw-apb-uart";
 377                         reg = <0x01c28400 0x400>;
 378                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 379                         reg-shift = <2>;
 380                         reg-io-width = <4>;
 381                         clocks = <&ccu CLK_BUS_UART1>;
 382                         resets = <&ccu RST_BUS_UART1>;
 383                         status = "disabled";
 384                 };
 385
 386                 uart2: serial@1c28800 {
 387                         compatible = "snps,dw-apb-uart";
 388                         reg = <0x01c28800 0x400>;
 389                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 390                         reg-shift = <2>;
 391                         reg-io-width = <4>;
 392                         clocks = <&ccu CLK_BUS_UART2>;
 393                         resets = <&ccu RST_BUS_UART2>;
 394                         status = "disabled";
 395                 };
 396
 397                 uart3: serial@1c28c00 {
 398                         compatible = "snps,dw-apb-uart";
 399                         reg = <0x01c28c00 0x400>;
 400                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 401                         reg-shift = <2>;
 402                         reg-io-width = <4>;
 403                         clocks = <&ccu CLK_BUS_UART3>;
 404                         resets = <&ccu RST_BUS_UART3>;
 405                         status = "disabled";
 406                 };
 407
 408                 uart4: serial@1c29000 {
 409                         compatible = "snps,dw-apb-uart";
 410                         reg = <0x01c29000 0x400>;
 411                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 412                         reg-shift = <2>;
 413                         reg-io-width = <4>;
 414                         clocks = <&ccu CLK_BUS_UART4>;
 415                         resets = <&ccu RST_BUS_UART4>;
 416                         status = "disabled";
 417                 };
 418
 419                 i2c0: i2c@1c2ac00 {
 420                         compatible = "allwinner,sun6i-a31-i2c";
 421                         reg = <0x01c2ac00 0x400>;
 422                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&ccu CLK_BUS_I2C0>;
 424                         resets = <&ccu RST_BUS_I2C0>;
 425                         status = "disabled";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                 };
 429
 430                 i2c1: i2c@1c2b000 {
 431                         compatible = "allwinner,sun6i-a31-i2c";
 432                         reg = <0x01c2b000 0x400>;
 433                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&ccu CLK_BUS_I2C1>;
 435                         resets = <&ccu RST_BUS_I2C1>;
 436                         status = "disabled";
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                 };
 440
 441                 i2c2: i2c@1c2b400 {
 442                         compatible = "allwinner,sun6i-a31-i2c";
 443                         reg = <0x01c2b400 0x400>;
 444                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&ccu CLK_BUS_I2C2>;
 446                         resets = <&ccu RST_BUS_I2C2>;
 447                         status = "disabled";
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                 };
 451
 452                 gic: interrupt-controller@1c81000 {
 453                         compatible = "arm,gic-400";
 454                         reg = <0x01c81000 0x1000>,
 455                               <0x01c82000 0x2000>,
 456                               <0x01c84000 0x2000>,
 457                               <0x01c86000 0x2000>;
 458                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 459                         interrupt-controller;
 460                         #interrupt-cells = <3>;
 461                 };
 462
 463                 rtc: rtc@1f00000 {
 464                         compatible = "allwinner,sun6i-a31-rtc";
 465                         reg = <0x01f00000 0x54>;
 466                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 467                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 468                 };
 469
 470                 r_ccu: clock@1f01400 {
 471                         compatible = "allwinner,sun50i-a64-r-ccu";
 472                         reg = <0x01f01400 0x100>;
 473                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 474                                  <&ccu 11>;
 475                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 476                         #clock-cells = <1>;
 477                         #reset-cells = <1>;
 478                 };
 479
 480                 r_pio: pinctrl@01f02c00 {
 481                         compatible = "allwinner,sun50i-a64-r-pinctrl";
 482                         reg = <0x01f02c00 0x400>;
 483                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 485                         clock-names = "apb", "hosc", "losc";
 486                         gpio-controller;
 487                         #gpio-cells = <3>;
 488                         interrupt-controller;
 489                         #interrupt-cells = <3>;
 490
 491                         r_rsb_pins: rsb@0 {
 492                                 pins = "PL0", "PL1";
 493                                 function = "s_rsb";
 494                         };
 495                 };
 496
 497                 r_rsb: rsb@1f03400 {
 498                         compatible = "allwinner,sun8i-a23-rsb";
 499                         reg = <0x01f03400 0x400>;
 500                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&r_ccu 6>;
 502                         clock-frequency = <3000000>;
 503                         resets = <&r_ccu 2>;
 504                         pinctrl-names = "default";
 505                         pinctrl-0 = <&r_rsb_pins>;
 506                         status = "disabled";
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                 };
 510         };
 511 };