3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_SUPPORTS_MEMORY_FAILURE
27 select ARCH_SUPPORTS_ATOMIC_RMW
28 select ARCH_SUPPORTS_NUMA_BALANCING
29 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
30 select ARCH_WANT_FRAME_POINTERS
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
35 select AUDIT_ARCH_COMPAT_GENERIC
36 select ARM_GIC_V2M if PCI
38 select ARM_GIC_V3_ITS if PCI
40 select BUILDTIME_EXTABLE_SORT
41 select CLONE_BACKWARDS
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select DCACHE_WORD_ACCESS
47 select GENERIC_ALLOCATOR
48 select GENERIC_ARCH_TOPOLOGY
49 select GENERIC_CLOCKEVENTS
50 select GENERIC_CLOCKEVENTS_BROADCAST
51 select GENERIC_CPU_AUTOPROBE
52 select GENERIC_EARLY_IOREMAP
53 select GENERIC_IDLE_POLL_SETUP
54 select GENERIC_IRQ_PROBE
55 select GENERIC_IRQ_SHOW
56 select GENERIC_IRQ_SHOW_LEVEL
57 select GENERIC_PCI_IOMAP
58 select GENERIC_SCHED_CLOCK
59 select GENERIC_SMP_IDLE_THREAD
60 select GENERIC_STRNCPY_FROM_USER
61 select GENERIC_STRNLEN_USER
62 select GENERIC_TIME_VSYSCALL
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ACPI_APEI if (ACPI && EFI)
66 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
67 select HAVE_ARCH_AUDITSYSCALL
68 select HAVE_ARCH_BITREVERSE
69 select HAVE_ARCH_HUGE_VMAP
70 select HAVE_ARCH_JUMP_LABEL
71 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
73 select HAVE_ARCH_MMAP_RND_BITS
74 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
75 select HAVE_ARCH_SECCOMP_FILTER
76 select HAVE_ARCH_TRACEHOOK
77 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
78 select HAVE_ARCH_VMAP_STACK
81 select HAVE_C_RECORDMCOUNT
82 select HAVE_CC_STACKPROTECTOR
83 select HAVE_CMPXCHG_DOUBLE
84 select HAVE_CMPXCHG_LOCAL
85 select HAVE_CONTEXT_TRACKING
86 select HAVE_DEBUG_BUGVERBOSE
87 select HAVE_DEBUG_KMEMLEAK
88 select HAVE_DMA_API_DEBUG
89 select HAVE_DMA_CONTIGUOUS
90 select HAVE_DYNAMIC_FTRACE
91 select HAVE_EFFICIENT_UNALIGNED_ACCESS
92 select HAVE_FTRACE_MCOUNT_RECORD
93 select HAVE_FUNCTION_TRACER
94 select HAVE_FUNCTION_GRAPH_TRACER
95 select HAVE_GCC_PLUGINS
96 select HAVE_GENERIC_DMA_COHERENT
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS
98 select HAVE_IRQ_TIME_ACCOUNTING
100 select HAVE_MEMBLOCK_NODE_MAP if NUMA
101 select HAVE_NMI if ACPI_APEI_SEA
102 select HAVE_PATA_PLATFORM
103 select HAVE_PERF_EVENTS
104 select HAVE_PERF_REGS
105 select HAVE_PERF_USER_STACK_DUMP
106 select HAVE_REGS_AND_STACK_ACCESS_API
107 select HAVE_RCU_TABLE_FREE
108 select HAVE_SYSCALL_TRACEPOINTS
110 select HAVE_KRETPROBES
111 select IOMMU_DMA if IOMMU_SUPPORT
113 select IRQ_FORCED_THREADING
114 select MODULES_USE_ELF_RELA
117 select OF_EARLY_FLATTREE
118 select OF_RESERVED_MEM
119 select PCI_ECAM if ACPI
123 select SYSCTL_EXCEPTION_TRACE
124 select THREAD_INFO_IN_TASK
126 ARM 64-bit (AArch64) Linux support.
131 config ARCH_PHYS_ADDR_T_64BIT
137 config ARM64_PAGE_SHIFT
139 default 16 if ARM64_64K_PAGES
140 default 14 if ARM64_16K_PAGES
143 config ARM64_CONT_SHIFT
145 default 5 if ARM64_64K_PAGES
146 default 7 if ARM64_16K_PAGES
149 config ARCH_MMAP_RND_BITS_MIN
150 default 14 if ARM64_64K_PAGES
151 default 16 if ARM64_16K_PAGES
154 # max bits determined by the following formula:
155 # VA_BITS - PAGE_SHIFT - 3
156 config ARCH_MMAP_RND_BITS_MAX
157 default 19 if ARM64_VA_BITS=36
158 default 24 if ARM64_VA_BITS=39
159 default 27 if ARM64_VA_BITS=42
160 default 30 if ARM64_VA_BITS=47
161 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
162 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
163 default 33 if ARM64_VA_BITS=48
164 default 14 if ARM64_64K_PAGES
165 default 16 if ARM64_16K_PAGES
168 config ARCH_MMAP_RND_COMPAT_BITS_MIN
169 default 7 if ARM64_64K_PAGES
170 default 9 if ARM64_16K_PAGES
173 config ARCH_MMAP_RND_COMPAT_BITS_MAX
179 config STACKTRACE_SUPPORT
182 config ILLEGAL_POINTER_VALUE
184 default 0xdead000000000000
186 config LOCKDEP_SUPPORT
189 config TRACE_IRQFLAGS_SUPPORT
192 config RWSEM_XCHGADD_ALGORITHM
199 config GENERIC_BUG_RELATIVE_POINTERS
201 depends on GENERIC_BUG
203 config GENERIC_HWEIGHT
209 config GENERIC_CALIBRATE_DELAY
215 config HAVE_GENERIC_GUP
218 config ARCH_DMA_ADDR_T_64BIT
221 config NEED_DMA_MAP_STATE
224 config NEED_SG_DMA_LENGTH
236 config KERNEL_MODE_NEON
239 config FIX_EARLYCON_MEM
242 config PGTABLE_LEVELS
244 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
245 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
246 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
247 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
248 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
249 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
251 config ARCH_SUPPORTS_UPROBES
254 config ARCH_PROC_KCORE_TEXT
257 source "init/Kconfig"
259 source "kernel/Kconfig.freezer"
261 source "arch/arm64/Kconfig.platforms"
268 This feature enables support for PCI bus system. If you say Y
269 here, the kernel will include drivers and infrastructure code
270 to support PCI bus devices.
275 config PCI_DOMAINS_GENERIC
281 source "drivers/pci/Kconfig"
285 menu "Kernel Features"
287 menu "ARM errata workarounds via the alternatives framework"
289 config ARM64_ERRATUM_826319
290 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
293 This option adds an alternative code sequence to work around ARM
294 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
295 AXI master interface and an L2 cache.
297 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
298 and is unable to accept a certain write via this interface, it will
299 not progress on read data presented on the read data channel and the
302 The workaround promotes data cache clean instructions to
303 data cache clean-and-invalidate.
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
310 config ARM64_ERRATUM_827319
311 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
314 This option adds an alternative code sequence to work around ARM
315 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
316 master interface and an L2 cache.
318 Under certain conditions this erratum can cause a clean line eviction
319 to occur at the same time as another transaction to the same address
320 on the AMBA 5 CHI interface, which can cause data corruption if the
321 interconnect reorders the two transactions.
323 The workaround promotes data cache clean instructions to
324 data cache clean-and-invalidate.
325 Please note that this does not necessarily enable the workaround,
326 as it depends on the alternative framework, which will only patch
327 the kernel if an affected CPU is detected.
331 config ARM64_ERRATUM_824069
332 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
335 This option adds an alternative code sequence to work around ARM
336 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
337 to a coherent interconnect.
339 If a Cortex-A53 processor is executing a store or prefetch for
340 write instruction at the same time as a processor in another
341 cluster is executing a cache maintenance operation to the same
342 address, then this erratum might cause a clean cache line to be
343 incorrectly marked as dirty.
345 The workaround promotes data cache clean instructions to
346 data cache clean-and-invalidate.
347 Please note that this option does not necessarily enable the
348 workaround, as it depends on the alternative framework, which will
349 only patch the kernel if an affected CPU is detected.
353 config ARM64_ERRATUM_819472
354 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
357 This option adds an alternative code sequence to work around ARM
358 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
359 present when it is connected to a coherent interconnect.
361 If the processor is executing a load and store exclusive sequence at
362 the same time as a processor in another cluster is executing a cache
363 maintenance operation to the same address, then this erratum might
364 cause data corruption.
366 The workaround promotes data cache clean instructions to
367 data cache clean-and-invalidate.
368 Please note that this does not necessarily enable the workaround,
369 as it depends on the alternative framework, which will only patch
370 the kernel if an affected CPU is detected.
374 config ARM64_ERRATUM_832075
375 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
378 This option adds an alternative code sequence to work around ARM
379 erratum 832075 on Cortex-A57 parts up to r1p2.
381 Affected Cortex-A57 parts might deadlock when exclusive load/store
382 instructions to Write-Back memory are mixed with Device loads.
384 The workaround is to promote device loads to use Load-Acquire
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_834220
393 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
397 This option adds an alternative code sequence to work around ARM
398 erratum 834220 on Cortex-A57 parts up to r1p2.
400 Affected Cortex-A57 parts might report a Stage 2 translation
401 fault as the result of a Stage 1 fault for load crossing a
402 page boundary when there is a permission or device memory
403 alignment fault at Stage 1 and a translation fault at Stage 2.
405 The workaround is to verify that the Stage 1 translation
406 doesn't generate a fault before handling the Stage 2 fault.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
413 config ARM64_ERRATUM_845719
414 bool "Cortex-A53: 845719: a load might read incorrect data"
418 This option adds an alternative code sequence to work around ARM
419 erratum 845719 on Cortex-A53 parts up to r0p4.
421 When running a compat (AArch32) userspace on an affected Cortex-A53
422 part, a load at EL0 from a virtual address that matches the bottom 32
423 bits of the virtual address used by a recent load at (AArch64) EL1
424 might return incorrect data.
426 The workaround is to write the contextidr_el1 register on exception
427 return to a 32-bit task.
428 Please note that this does not necessarily enable the workaround,
429 as it depends on the alternative framework, which will only patch
430 the kernel if an affected CPU is detected.
434 config ARM64_ERRATUM_843419
435 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
437 select ARM64_MODULE_CMODEL_LARGE if MODULES
439 This option links the kernel with '--fix-cortex-a53-843419' and
440 builds modules using the large memory model in order to avoid the use
441 of the ADRP instruction, which can cause a subsequent memory access
442 to use an incorrect address on Cortex-A53 parts up to r0p4.
446 config CAVIUM_ERRATUM_22375
447 bool "Cavium erratum 22375, 24313"
450 Enable workaround for erratum 22375, 24313.
452 This implements two gicv3-its errata workarounds for ThunderX. Both
453 with small impact affecting only ITS table allocation.
455 erratum 22375: only alloc 8MB table size
456 erratum 24313: ignore memory access type
458 The fixes are in ITS initialization and basically ignore memory access
459 type and table size provided by the TYPER and BASER registers.
463 config CAVIUM_ERRATUM_23144
464 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
468 ITS SYNC command hang for cross node io and collections/cpu mapping.
472 config CAVIUM_ERRATUM_23154
473 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
476 The gicv3 of ThunderX requires a modified version for
477 reading the IAR status to ensure data synchronization
478 (access to icc_iar1_el1 is not sync'ed before and after).
482 config CAVIUM_ERRATUM_27456
483 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
486 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
487 instructions may cause the icache to become corrupted if it
488 contains data for a non-current ASID. The fix is to
489 invalidate the icache when changing the mm context.
493 config CAVIUM_ERRATUM_30115
494 bool "Cavium erratum 30115: Guest may disable interrupts in host"
497 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
498 1.2, and T83 Pass 1.0, KVM guest execution may disable
499 interrupts in host. Trapping both GICv3 group-0 and group-1
500 accesses sidesteps the issue.
504 config QCOM_FALKOR_ERRATUM_1003
505 bool "Falkor E1003: Incorrect translation due to ASID change"
507 select ARM64_PAN if ARM64_SW_TTBR0_PAN
509 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
510 and BADDR are changed together in TTBRx_EL1. The workaround for this
511 issue is to use a reserved ASID in cpu_do_switch_mm() before
512 switching to the new ASID. Saying Y here selects ARM64_PAN if
513 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
514 maintaining the E1003 workaround in the software PAN emulation code
515 would be an unnecessary complication. The affected Falkor v1 CPU
516 implements ARMv8.1 hardware PAN support and using hardware PAN
517 support versus software PAN emulation is mutually exclusive at
522 config QCOM_FALKOR_ERRATUM_1009
523 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
526 On Falkor v1, the CPU may prematurely complete a DSB following a
527 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
528 one more time to fix the issue.
532 config QCOM_QDF2400_ERRATUM_0065
533 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
536 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
537 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
538 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
547 default ARM64_4K_PAGES
549 Page size (translation granule) configuration.
551 config ARM64_4K_PAGES
554 This feature enables 4KB pages support.
556 config ARM64_16K_PAGES
559 The system will use 16KB pages support. AArch32 emulation
560 requires applications compiled with 16K (or a multiple of 16K)
563 config ARM64_64K_PAGES
566 This feature enables 64KB pages support (4KB by default)
567 allowing only two levels of page tables and faster TLB
568 look-up. AArch32 emulation requires applications compiled
569 with 64K aligned segments.
574 prompt "Virtual address space size"
575 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
576 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
577 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
579 Allows choosing one of multiple possible virtual address
580 space sizes. The level of translation table is determined by
581 a combination of page size and virtual address space size.
583 config ARM64_VA_BITS_36
584 bool "36-bit" if EXPERT
585 depends on ARM64_16K_PAGES
587 config ARM64_VA_BITS_39
589 depends on ARM64_4K_PAGES
591 config ARM64_VA_BITS_42
593 depends on ARM64_64K_PAGES
595 config ARM64_VA_BITS_47
597 depends on ARM64_16K_PAGES
599 config ARM64_VA_BITS_48
606 default 36 if ARM64_VA_BITS_36
607 default 39 if ARM64_VA_BITS_39
608 default 42 if ARM64_VA_BITS_42
609 default 47 if ARM64_VA_BITS_47
610 default 48 if ARM64_VA_BITS_48
612 config CPU_BIG_ENDIAN
613 bool "Build big-endian kernel"
615 Say Y if you plan on running a kernel in big-endian mode.
618 bool "Multi-core scheduler support"
620 Multi-core scheduler support improves the CPU scheduler's decision
621 making when dealing with multi-core CPU chips at a cost of slightly
622 increased overhead in some places. If unsure say N here.
625 bool "SMT scheduler support"
627 Improves the CPU scheduler's decision making when dealing with
628 MultiThreading at a cost of slightly increased overhead in some
629 places. If unsure say N here.
632 int "Maximum number of CPUs (2-4096)"
634 # These have to remain sorted largest to smallest
638 bool "Support for hot-pluggable CPUs"
639 select GENERIC_IRQ_MIGRATION
641 Say Y here to experiment with turning CPUs off and on. CPUs
642 can be controlled through /sys/devices/system/cpu.
644 # Common NUMA Features
646 bool "Numa Memory Allocation and Scheduler Support"
647 select ACPI_NUMA if ACPI
650 Enable NUMA (Non Uniform Memory Access) support.
652 The kernel will try to allocate memory used by a CPU on the
653 local memory of the CPU and add some more
654 NUMA awareness to the kernel.
657 int "Maximum NUMA Nodes (as a power of 2)"
660 depends on NEED_MULTIPLE_NODES
662 Specify the maximum number of NUMA Nodes available on the target
663 system. Increases memory reserved to accommodate various tables.
665 config USE_PERCPU_NUMA_NODE_ID
669 config HAVE_SETUP_PER_CPU_AREA
673 config NEED_PER_CPU_EMBED_FIRST_CHUNK
681 source kernel/Kconfig.preempt
682 source kernel/Kconfig.hz
684 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
687 config ARCH_HAS_HOLES_MEMORYMODEL
688 def_bool y if SPARSEMEM
690 config ARCH_SPARSEMEM_ENABLE
692 select SPARSEMEM_VMEMMAP_ENABLE
694 config ARCH_SPARSEMEM_DEFAULT
695 def_bool ARCH_SPARSEMEM_ENABLE
697 config ARCH_SELECT_MEMORY_MODEL
698 def_bool ARCH_SPARSEMEM_ENABLE
700 config HAVE_ARCH_PFN_VALID
701 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
703 config HW_PERF_EVENTS
707 config SYS_SUPPORTS_HUGETLBFS
710 config ARCH_WANT_HUGE_PMD_SHARE
711 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
713 config ARCH_HAS_CACHE_LINE_SIZE
719 bool "Enable seccomp to safely compute untrusted bytecode"
721 This kernel feature is useful for number crunching applications
722 that may need to compute untrusted bytecode during their
723 execution. By using pipes or other transports made available to
724 the process as file descriptors supporting the read/write
725 syscalls, it's possible to isolate those applications in
726 their own address space using seccomp. Once seccomp is
727 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
728 and the task is only allowed to execute a few safe syscalls
729 defined by each seccomp mode.
732 bool "Enable paravirtualization code"
734 This changes the kernel so it can modify itself when it is run
735 under a hypervisor, potentially improving performance significantly
736 over full virtualization.
738 config PARAVIRT_TIME_ACCOUNTING
739 bool "Paravirtual steal time accounting"
743 Select this option to enable fine granularity task steal time
744 accounting. Time spent executing other tasks in parallel with
745 the current vCPU is discounted from the vCPU power. To account for
746 that, there can be a small performance impact.
748 If in doubt, say N here.
751 depends on PM_SLEEP_SMP
753 bool "kexec system call"
755 kexec is a system call that implements the ability to shutdown your
756 current kernel, and to start another kernel. It is like a reboot
757 but it is independent of the system firmware. And like a reboot
758 you can start any kernel with it, not just Linux.
761 bool "Build kdump crash kernel"
763 Generate crash dump after being started by kexec. This should
764 be normally only set in special crash dump kernels which are
765 loaded in the main kernel with kexec-tools into a specially
766 reserved region and then later executed after a crash by
769 For more details see Documentation/kdump/kdump.txt
776 bool "Xen guest support on ARM64"
777 depends on ARM64 && OF
781 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
783 config FORCE_MAX_ZONEORDER
785 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
786 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
789 The kernel memory allocator divides physically contiguous memory
790 blocks into "zones", where each zone is a power of two number of
791 pages. This option selects the largest power of two that the kernel
792 keeps in the memory allocator. If you need to allocate very large
793 blocks of physically contiguous memory, then you may need to
796 This config option is actually maximum order plus one. For example,
797 a value of 11 means that the largest free memory block is 2^10 pages.
799 We make sure that we can allocate upto a HugePage size for each configuration.
801 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
803 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
804 4M allocations matching the default size used by generic code.
806 menuconfig ARMV8_DEPRECATED
807 bool "Emulate deprecated/obsolete ARMv8 instructions"
810 Legacy software support may require certain instructions
811 that have been deprecated or obsoleted in the architecture.
813 Enable this config to enable selective emulation of these
821 bool "Emulate SWP/SWPB instructions"
823 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
824 they are always undefined. Say Y here to enable software
825 emulation of these instructions for userspace using LDXR/STXR.
827 In some older versions of glibc [<=2.8] SWP is used during futex
828 trylock() operations with the assumption that the code will not
829 be preempted. This invalid assumption may be more likely to fail
830 with SWP emulation enabled, leading to deadlock of the user
833 NOTE: when accessing uncached shared regions, LDXR/STXR rely
834 on an external transaction monitoring block called a global
835 monitor to maintain update atomicity. If your system does not
836 implement a global monitor, this option can cause programs that
837 perform SWP operations to uncached memory to deadlock.
841 config CP15_BARRIER_EMULATION
842 bool "Emulate CP15 Barrier instructions"
844 The CP15 barrier instructions - CP15ISB, CP15DSB, and
845 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
846 strongly recommended to use the ISB, DSB, and DMB
847 instructions instead.
849 Say Y here to enable software emulation of these
850 instructions for AArch32 userspace code. When this option is
851 enabled, CP15 barrier usage is traced which can help
852 identify software that needs updating.
856 config SETEND_EMULATION
857 bool "Emulate SETEND instruction"
859 The SETEND instruction alters the data-endianness of the
860 AArch32 EL0, and is deprecated in ARMv8.
862 Say Y here to enable software emulation of the instruction
863 for AArch32 userspace code.
865 Note: All the cpus on the system must have mixed endian support at EL0
866 for this feature to be enabled. If a new CPU - which doesn't support mixed
867 endian - is hotplugged in after this feature has been enabled, there could
868 be unexpected results in the applications.
873 config ARM64_SW_TTBR0_PAN
874 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
876 Enabling this option prevents the kernel from accessing
877 user-space memory directly by pointing TTBR0_EL1 to a reserved
878 zeroed area and reserved ASID. The user access routines
879 restore the valid TTBR0_EL1 temporarily.
881 menu "ARMv8.1 architectural features"
883 config ARM64_HW_AFDBM
884 bool "Support for hardware updates of the Access and Dirty page flags"
887 The ARMv8.1 architecture extensions introduce support for
888 hardware updates of the access and dirty information in page
889 table entries. When enabled in TCR_EL1 (HA and HD bits) on
890 capable processors, accesses to pages with PTE_AF cleared will
891 set this bit instead of raising an access flag fault.
892 Similarly, writes to read-only pages with the DBM bit set will
893 clear the read-only bit (AP[2]) instead of raising a
896 Kernels built with this configuration option enabled continue
897 to work on pre-ARMv8.1 hardware and the performance impact is
898 minimal. If unsure, say Y.
901 bool "Enable support for Privileged Access Never (PAN)"
904 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
905 prevents the kernel or hypervisor from accessing user-space (EL0)
908 Choosing this option will cause any unprotected (not using
909 copy_to_user et al) memory access to fail with a permission fault.
911 The feature is detected at runtime, and will remain as a 'nop'
912 instruction if the cpu does not implement the feature.
914 config ARM64_LSE_ATOMICS
915 bool "Atomic instructions"
917 As part of the Large System Extensions, ARMv8.1 introduces new
918 atomic instructions that are designed specifically to scale in
921 Say Y here to make use of these instructions for the in-kernel
922 atomic routines. This incurs a small overhead on CPUs that do
923 not support these instructions and requires the kernel to be
924 built with binutils >= 2.25.
927 bool "Enable support for Virtualization Host Extensions (VHE)"
930 Virtualization Host Extensions (VHE) allow the kernel to run
931 directly at EL2 (instead of EL1) on processors that support
932 it. This leads to better performance for KVM, as they reduce
933 the cost of the world switch.
935 Selecting this option allows the VHE feature to be detected
936 at runtime, and does not affect processors that do not
937 implement this feature.
941 menu "ARMv8.2 architectural features"
944 bool "Enable support for User Access Override (UAO)"
947 User Access Override (UAO; part of the ARMv8.2 Extensions)
948 causes the 'unprivileged' variant of the load/store instructions to
949 be overriden to be privileged.
951 This option changes get_user() and friends to use the 'unprivileged'
952 variant of the load/store instructions. This ensures that user-space
953 really did have access to the supplied memory. When addr_limit is
954 set to kernel memory the UAO bit will be set, allowing privileged
955 access to kernel memory.
957 Choosing this option will cause copy_to_user() et al to use user-space
960 The feature is detected at runtime, the kernel will use the
961 regular load/store instructions if the cpu does not implement the
965 bool "Enable support for persistent memory"
966 select ARCH_HAS_PMEM_API
967 select ARCH_HAS_UACCESS_FLUSHCACHE
969 Say Y to enable support for the persistent memory API based on the
970 ARMv8.2 DCPoP feature.
972 The feature is detected at runtime, and the kernel will use DC CVAC
973 operations if DC CVAP is not supported (following the behaviour of
974 DC CVAP itself if the system does not define a point of persistence).
978 config ARM64_MODULE_CMODEL_LARGE
981 config ARM64_MODULE_PLTS
983 select ARM64_MODULE_CMODEL_LARGE
984 select HAVE_MOD_ARCH_SPECIFIC
989 This builds the kernel as a Position Independent Executable (PIE),
990 which retains all relocation metadata required to relocate the
991 kernel binary at runtime to a different virtual address than the
992 address it was linked at.
993 Since AArch64 uses the RELA relocation format, this requires a
994 relocation pass at runtime even if the kernel is loaded at the
995 same address it was linked at.
997 config RANDOMIZE_BASE
998 bool "Randomize the address of the kernel image"
999 select ARM64_MODULE_PLTS if MODULES
1002 Randomizes the virtual address at which the kernel image is
1003 loaded, as a security feature that deters exploit attempts
1004 relying on knowledge of the location of kernel internals.
1006 It is the bootloader's job to provide entropy, by passing a
1007 random u64 value in /chosen/kaslr-seed at kernel entry.
1009 When booting via the UEFI stub, it will invoke the firmware's
1010 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1011 to the kernel proper. In addition, it will randomise the physical
1012 location of the kernel Image as well.
1016 config RANDOMIZE_MODULE_REGION_FULL
1017 bool "Randomize the module region independently from the core kernel"
1018 depends on RANDOMIZE_BASE
1021 Randomizes the location of the module region without considering the
1022 location of the core kernel. This way, it is impossible for modules
1023 to leak information about the location of core kernel data structures
1024 but it does imply that function calls between modules and the core
1025 kernel will need to be resolved via veneers in the module PLT.
1027 When this option is not set, the module region will be randomized over
1028 a limited range that contains the [_stext, _etext] interval of the
1029 core kernel, so branch relocations are always in range.
1035 config ARM64_ACPI_PARKING_PROTOCOL
1036 bool "Enable support for the ARM64 ACPI parking protocol"
1039 Enable support for the ARM64 ACPI parking protocol. If disabled
1040 the kernel will not allow booting through the ARM64 ACPI parking
1041 protocol even if the corresponding data is present in the ACPI
1045 string "Default kernel command string"
1048 Provide a set of default command-line options at build time by
1049 entering them here. As a minimum, you should specify the the
1050 root device (e.g. root=/dev/nfs).
1052 config CMDLINE_FORCE
1053 bool "Always use the default kernel command string"
1055 Always use the default kernel command string, even if the boot
1056 loader passes other arguments to the kernel.
1057 This is useful if you cannot or don't want to change the
1058 command-line options your boot loader passes to the kernel.
1064 bool "UEFI runtime support"
1065 depends on OF && !CPU_BIG_ENDIAN
1068 select EFI_PARAMS_FROM_FDT
1069 select EFI_RUNTIME_WRAPPERS
1074 This option provides support for runtime services provided
1075 by UEFI firmware (such as non-volatile variables, realtime
1076 clock, and platform reset). A UEFI stub is also provided to
1077 allow the kernel to be booted as an EFI application. This
1078 is only useful on systems that have UEFI firmware.
1081 bool "Enable support for SMBIOS (DMI) tables"
1085 This enables SMBIOS/DMI feature for systems.
1087 This option is only useful on systems that have UEFI firmware.
1088 However, even with this option, the resultant kernel should
1089 continue to boot on existing non-UEFI platforms.
1093 menu "Userspace binary formats"
1095 source "fs/Kconfig.binfmt"
1098 bool "Kernel support for 32-bit EL0"
1099 depends on ARM64_4K_PAGES || EXPERT
1100 select COMPAT_BINFMT_ELF if BINFMT_ELF
1102 select OLD_SIGSUSPEND3
1103 select COMPAT_OLD_SIGACTION
1105 This option enables support for a 32-bit EL0 running under a 64-bit
1106 kernel at EL1. AArch32-specific components such as system calls,
1107 the user helper functions, VFP support and the ptrace interface are
1108 handled appropriately by the kernel.
1110 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1111 that you will only be able to execute AArch32 binaries that were compiled
1112 with page size aligned segments.
1114 If you want to execute 32-bit userspace applications, say Y.
1116 config SYSVIPC_COMPAT
1118 depends on COMPAT && SYSVIPC
1122 menu "Power management options"
1124 source "kernel/power/Kconfig"
1126 config ARCH_HIBERNATION_POSSIBLE
1130 config ARCH_HIBERNATION_HEADER
1132 depends on HIBERNATION
1134 config ARCH_SUSPEND_POSSIBLE
1139 menu "CPU Power Management"
1141 source "drivers/cpuidle/Kconfig"
1143 source "drivers/cpufreq/Kconfig"
1147 source "net/Kconfig"
1149 source "drivers/Kconfig"
1151 source "drivers/firmware/Kconfig"
1153 source "drivers/acpi/Kconfig"
1157 source "arch/arm64/kvm/Kconfig"
1159 source "arch/arm64/Kconfig.debug"
1161 source "security/Kconfig"
1163 source "crypto/Kconfig"
1165 source "arch/arm64/crypto/Kconfig"
1168 source "lib/Kconfig"