1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE
23 select ARCH_HAS_KEEPINITRD
24 select ARCH_HAS_MEMBARRIER_SYNC_CORE
25 select ARCH_HAS_PTE_DEVMAP
26 select ARCH_HAS_PTE_SPECIAL
27 select ARCH_HAS_SETUP_DMA_OPS
28 select ARCH_HAS_SET_DIRECT_MAP
29 select ARCH_HAS_SET_MEMORY
30 select ARCH_HAS_STRICT_KERNEL_RWX
31 select ARCH_HAS_STRICT_MODULE_RWX
32 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
33 select ARCH_HAS_SYNC_DMA_FOR_CPU
34 select ARCH_HAS_SYSCALL_WRAPPER
35 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
36 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
37 select ARCH_HAVE_NMI_SAFE_CMPXCHG
38 select ARCH_INLINE_READ_LOCK if !PREEMPT
39 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
54 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
64 select ARCH_KEEP_MEMBLOCK
65 select ARCH_USE_CMPXCHG_LOCKREF
66 select ARCH_USE_QUEUED_RWLOCKS
67 select ARCH_USE_QUEUED_SPINLOCKS
68 select ARCH_SUPPORTS_MEMORY_FAILURE
69 select ARCH_SUPPORTS_ATOMIC_RMW
70 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
71 select ARCH_SUPPORTS_NUMA_BALANCING
72 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
73 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
74 select ARCH_WANT_FRAME_POINTERS
75 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
76 select ARCH_HAS_UBSAN_SANITIZE_ALL
80 select AUDIT_ARCH_COMPAT_GENERIC
81 select ARM_GIC_V2M if PCI
83 select ARM_GIC_V3_ITS if PCI
85 select BUILDTIME_EXTABLE_SORT
86 select CLONE_BACKWARDS
88 select CPU_PM if (SUSPEND || CPU_IDLE)
90 select DCACHE_WORD_ACCESS
91 select DMA_DIRECT_REMAP
94 select GENERIC_ALLOCATOR
95 select GENERIC_ARCH_TOPOLOGY
96 select GENERIC_CLOCKEVENTS
97 select GENERIC_CLOCKEVENTS_BROADCAST
98 select GENERIC_CPU_AUTOPROBE
99 select GENERIC_CPU_VULNERABILITIES
100 select GENERIC_EARLY_IOREMAP
101 select GENERIC_IDLE_POLL_SETUP
102 select GENERIC_IRQ_MULTI_HANDLER
103 select GENERIC_IRQ_PROBE
104 select GENERIC_IRQ_SHOW
105 select GENERIC_IRQ_SHOW_LEVEL
106 select GENERIC_PCI_IOMAP
107 select GENERIC_SCHED_CLOCK
108 select GENERIC_SMP_IDLE_THREAD
109 select GENERIC_STRNCPY_FROM_USER
110 select GENERIC_STRNLEN_USER
111 select GENERIC_TIME_VSYSCALL
112 select GENERIC_GETTIMEOFDAY
113 select HANDLE_DOMAIN_IRQ
114 select HARDIRQS_SW_RESEND
116 select HAVE_ACPI_APEI if (ACPI && EFI)
117 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
118 select HAVE_ARCH_AUDITSYSCALL
119 select HAVE_ARCH_BITREVERSE
120 select HAVE_ARCH_HUGE_VMAP
121 select HAVE_ARCH_JUMP_LABEL
122 select HAVE_ARCH_JUMP_LABEL_RELATIVE
123 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
124 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
125 select HAVE_ARCH_KGDB
126 select HAVE_ARCH_MMAP_RND_BITS
127 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
128 select HAVE_ARCH_PREL32_RELOCATIONS
129 select HAVE_ARCH_SECCOMP_FILTER
130 select HAVE_ARCH_STACKLEAK
131 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
132 select HAVE_ARCH_TRACEHOOK
133 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
134 select HAVE_ARCH_VMAP_STACK
135 select HAVE_ARM_SMCCC
136 select HAVE_ASM_MODVERSIONS
138 select HAVE_C_RECORDMCOUNT
139 select HAVE_CMPXCHG_DOUBLE
140 select HAVE_CMPXCHG_LOCAL
141 select HAVE_CONTEXT_TRACKING
142 select HAVE_DEBUG_BUGVERBOSE
143 select HAVE_DEBUG_KMEMLEAK
144 select HAVE_DMA_CONTIGUOUS
145 select HAVE_DYNAMIC_FTRACE
146 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
147 if $(cc-option,-fpatchable-function-entry=2)
148 select HAVE_EFFICIENT_UNALIGNED_ACCESS
150 select HAVE_FTRACE_MCOUNT_RECORD
151 select HAVE_FUNCTION_TRACER
152 select HAVE_FUNCTION_ERROR_INJECTION
153 select HAVE_FUNCTION_GRAPH_TRACER
154 select HAVE_GCC_PLUGINS
155 select HAVE_HW_BREAKPOINT if PERF_EVENTS
156 select HAVE_IRQ_TIME_ACCOUNTING
157 select HAVE_MEMBLOCK_NODE_MAP if NUMA
159 select HAVE_PATA_PLATFORM
160 select HAVE_PERF_EVENTS
161 select HAVE_PERF_REGS
162 select HAVE_PERF_USER_STACK_DUMP
163 select HAVE_REGS_AND_STACK_ACCESS_API
164 select HAVE_FUNCTION_ARG_ACCESS_API
165 select HAVE_RCU_TABLE_FREE
167 select HAVE_STACKPROTECTOR
168 select HAVE_SYSCALL_TRACEPOINTS
170 select HAVE_KRETPROBES
171 select HAVE_GENERIC_VDSO
172 select IOMMU_DMA if IOMMU_SUPPORT
174 select IRQ_FORCED_THREADING
175 select MODULES_USE_ELF_RELA
176 select NEED_DMA_MAP_STATE
177 select NEED_SG_DMA_LENGTH
179 select OF_EARLY_FLATTREE
180 select PCI_DOMAINS_GENERIC if PCI
181 select PCI_ECAM if (ACPI && PCI)
182 select PCI_SYSCALL if PCI
188 select SYSCTL_EXCEPTION_TRACE
189 select THREAD_INFO_IN_TASK
191 ARM 64-bit (AArch64) Linux support.
199 config ARM64_PAGE_SHIFT
201 default 16 if ARM64_64K_PAGES
202 default 14 if ARM64_16K_PAGES
205 config ARM64_CONT_SHIFT
207 default 5 if ARM64_64K_PAGES
208 default 7 if ARM64_16K_PAGES
211 config ARCH_MMAP_RND_BITS_MIN
212 default 14 if ARM64_64K_PAGES
213 default 16 if ARM64_16K_PAGES
216 # max bits determined by the following formula:
217 # VA_BITS - PAGE_SHIFT - 3
218 config ARCH_MMAP_RND_BITS_MAX
219 default 19 if ARM64_VA_BITS=36
220 default 24 if ARM64_VA_BITS=39
221 default 27 if ARM64_VA_BITS=42
222 default 30 if ARM64_VA_BITS=47
223 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
224 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
225 default 33 if ARM64_VA_BITS=48
226 default 14 if ARM64_64K_PAGES
227 default 16 if ARM64_16K_PAGES
230 config ARCH_MMAP_RND_COMPAT_BITS_MIN
231 default 7 if ARM64_64K_PAGES
232 default 9 if ARM64_16K_PAGES
235 config ARCH_MMAP_RND_COMPAT_BITS_MAX
241 config STACKTRACE_SUPPORT
244 config ILLEGAL_POINTER_VALUE
246 default 0xdead000000000000
248 config LOCKDEP_SUPPORT
251 config TRACE_IRQFLAGS_SUPPORT
258 config GENERIC_BUG_RELATIVE_POINTERS
260 depends on GENERIC_BUG
262 config GENERIC_HWEIGHT
268 config GENERIC_CALIBRATE_DELAY
272 bool "Support DMA zone" if EXPERT
276 bool "Support DMA32 zone" if EXPERT
279 config ARCH_ENABLE_MEMORY_HOTPLUG
285 config KERNEL_MODE_NEON
288 config FIX_EARLYCON_MEM
291 config PGTABLE_LEVELS
293 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
294 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
295 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
296 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
297 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
298 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
300 config ARCH_SUPPORTS_UPROBES
303 config ARCH_PROC_KCORE_TEXT
306 config KASAN_SHADOW_OFFSET
309 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
310 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
311 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
312 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
313 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
314 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
315 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
316 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
317 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
318 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
319 default 0xffffffffffffffff
321 source "arch/arm64/Kconfig.platforms"
323 menu "Kernel Features"
325 menu "ARM errata workarounds via the alternatives framework"
327 config ARM64_WORKAROUND_CLEAN_CACHE
330 config ARM64_ERRATUM_826319
331 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
333 select ARM64_WORKAROUND_CLEAN_CACHE
335 This option adds an alternative code sequence to work around ARM
336 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
337 AXI master interface and an L2 cache.
339 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
340 and is unable to accept a certain write via this interface, it will
341 not progress on read data presented on the read data channel and the
344 The workaround promotes data cache clean instructions to
345 data cache clean-and-invalidate.
346 Please note that this does not necessarily enable the workaround,
347 as it depends on the alternative framework, which will only patch
348 the kernel if an affected CPU is detected.
352 config ARM64_ERRATUM_827319
353 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
355 select ARM64_WORKAROUND_CLEAN_CACHE
357 This option adds an alternative code sequence to work around ARM
358 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
359 master interface and an L2 cache.
361 Under certain conditions this erratum can cause a clean line eviction
362 to occur at the same time as another transaction to the same address
363 on the AMBA 5 CHI interface, which can cause data corruption if the
364 interconnect reorders the two transactions.
366 The workaround promotes data cache clean instructions to
367 data cache clean-and-invalidate.
368 Please note that this does not necessarily enable the workaround,
369 as it depends on the alternative framework, which will only patch
370 the kernel if an affected CPU is detected.
374 config ARM64_ERRATUM_824069
375 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
377 select ARM64_WORKAROUND_CLEAN_CACHE
379 This option adds an alternative code sequence to work around ARM
380 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
381 to a coherent interconnect.
383 If a Cortex-A53 processor is executing a store or prefetch for
384 write instruction at the same time as a processor in another
385 cluster is executing a cache maintenance operation to the same
386 address, then this erratum might cause a clean cache line to be
387 incorrectly marked as dirty.
389 The workaround promotes data cache clean instructions to
390 data cache clean-and-invalidate.
391 Please note that this option does not necessarily enable the
392 workaround, as it depends on the alternative framework, which will
393 only patch the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_819472
398 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
400 select ARM64_WORKAROUND_CLEAN_CACHE
402 This option adds an alternative code sequence to work around ARM
403 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
404 present when it is connected to a coherent interconnect.
406 If the processor is executing a load and store exclusive sequence at
407 the same time as a processor in another cluster is executing a cache
408 maintenance operation to the same address, then this erratum might
409 cause data corruption.
411 The workaround promotes data cache clean instructions to
412 data cache clean-and-invalidate.
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
419 config ARM64_ERRATUM_832075
420 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
423 This option adds an alternative code sequence to work around ARM
424 erratum 832075 on Cortex-A57 parts up to r1p2.
426 Affected Cortex-A57 parts might deadlock when exclusive load/store
427 instructions to Write-Back memory are mixed with Device loads.
429 The workaround is to promote device loads to use Load-Acquire
431 Please note that this does not necessarily enable the workaround,
432 as it depends on the alternative framework, which will only patch
433 the kernel if an affected CPU is detected.
437 config ARM64_ERRATUM_834220
438 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
442 This option adds an alternative code sequence to work around ARM
443 erratum 834220 on Cortex-A57 parts up to r1p2.
445 Affected Cortex-A57 parts might report a Stage 2 translation
446 fault as the result of a Stage 1 fault for load crossing a
447 page boundary when there is a permission or device memory
448 alignment fault at Stage 1 and a translation fault at Stage 2.
450 The workaround is to verify that the Stage 1 translation
451 doesn't generate a fault before handling the Stage 2 fault.
452 Please note that this does not necessarily enable the workaround,
453 as it depends on the alternative framework, which will only patch
454 the kernel if an affected CPU is detected.
458 config ARM64_ERRATUM_845719
459 bool "Cortex-A53: 845719: a load might read incorrect data"
463 This option adds an alternative code sequence to work around ARM
464 erratum 845719 on Cortex-A53 parts up to r0p4.
466 When running a compat (AArch32) userspace on an affected Cortex-A53
467 part, a load at EL0 from a virtual address that matches the bottom 32
468 bits of the virtual address used by a recent load at (AArch64) EL1
469 might return incorrect data.
471 The workaround is to write the contextidr_el1 register on exception
472 return to a 32-bit task.
473 Please note that this does not necessarily enable the workaround,
474 as it depends on the alternative framework, which will only patch
475 the kernel if an affected CPU is detected.
479 config ARM64_ERRATUM_843419
480 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
482 select ARM64_MODULE_PLTS if MODULES
484 This option links the kernel with '--fix-cortex-a53-843419' and
485 enables PLT support to replace certain ADRP instructions, which can
486 cause subsequent memory accesses to use an incorrect address on
487 Cortex-A53 parts up to r0p4.
491 config ARM64_ERRATUM_1024718
492 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
495 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
497 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
498 update of the hardware dirty bit when the DBM/AP bits are updated
499 without a break-before-make. The workaround is to disable the usage
500 of hardware DBM locally on the affected cores. CPUs not affected by
501 this erratum will continue to use the feature.
505 config ARM64_ERRATUM_1418040
506 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
510 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
511 errata 1188873 and 1418040.
513 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
514 cause register corruption when accessing the timer registers
515 from AArch32 userspace.
519 config ARM64_ERRATUM_1165522
520 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
523 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
525 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
526 corrupted TLBs by speculating an AT instruction during a guest
531 config ARM64_ERRATUM_1286807
532 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
534 select ARM64_WORKAROUND_REPEAT_TLBI
536 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
538 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
539 address for a cacheable mapping of a location is being
540 accessed by a core while another core is remapping the virtual
541 address to a new physical page using the recommended
542 break-before-make sequence, then under very rare circumstances
543 TLBI+DSB completes before a read using the translation being
544 invalidated has been observed by other observers. The
545 workaround repeats the TLBI+DSB operation.
547 config ARM64_ERRATUM_1319367
548 bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
551 This option adds work arounds for ARM Cortex-A57 erratum 1319537
552 and A72 erratum 1319367
554 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
555 speculating an AT instruction during a guest context switch.
559 config ARM64_ERRATUM_1463225
560 bool "Cortex-A76: Software Step might prevent interrupt recognition"
563 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
565 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
566 of a system call instruction (SVC) can prevent recognition of
567 subsequent interrupts when software stepping is disabled in the
568 exception handler of the system call and either kernel debugging
569 is enabled or VHE is in use.
571 Work around the erratum by triggering a dummy step exception
572 when handling a system call from a task that is being stepped
573 in a VHE configuration of the kernel.
577 config ARM64_ERRATUM_1542419
578 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
581 This option adds a workaround for ARM Neoverse-N1 erratum
584 Affected Neoverse-N1 cores could execute a stale instruction when
585 modified by another CPU. The workaround depends on a firmware
588 Workaround the issue by hiding the DIC feature from EL0. This
589 forces user-space to perform cache maintenance.
593 config CAVIUM_ERRATUM_22375
594 bool "Cavium erratum 22375, 24313"
597 Enable workaround for errata 22375 and 24313.
599 This implements two gicv3-its errata workarounds for ThunderX. Both
600 with a small impact affecting only ITS table allocation.
602 erratum 22375: only alloc 8MB table size
603 erratum 24313: ignore memory access type
605 The fixes are in ITS initialization and basically ignore memory access
606 type and table size provided by the TYPER and BASER registers.
610 config CAVIUM_ERRATUM_23144
611 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
615 ITS SYNC command hang for cross node io and collections/cpu mapping.
619 config CAVIUM_ERRATUM_23154
620 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
623 The gicv3 of ThunderX requires a modified version for
624 reading the IAR status to ensure data synchronization
625 (access to icc_iar1_el1 is not sync'ed before and after).
629 config CAVIUM_ERRATUM_27456
630 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
633 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
634 instructions may cause the icache to become corrupted if it
635 contains data for a non-current ASID. The fix is to
636 invalidate the icache when changing the mm context.
640 config CAVIUM_ERRATUM_30115
641 bool "Cavium erratum 30115: Guest may disable interrupts in host"
644 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
645 1.2, and T83 Pass 1.0, KVM guest execution may disable
646 interrupts in host. Trapping both GICv3 group-0 and group-1
647 accesses sidesteps the issue.
651 config CAVIUM_TX2_ERRATUM_219
652 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
655 On Cavium ThunderX2, a load, store or prefetch instruction between a
656 TTBR update and the corresponding context synchronizing operation can
657 cause a spurious Data Abort to be delivered to any hardware thread in
660 Work around the issue by avoiding the problematic code sequence and
661 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
662 trap handler performs the corresponding register access, skips the
663 instruction and ensures context synchronization by virtue of the
668 config QCOM_FALKOR_ERRATUM_1003
669 bool "Falkor E1003: Incorrect translation due to ASID change"
672 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
673 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
674 in TTBR1_EL1, this situation only occurs in the entry trampoline and
675 then only for entries in the walk cache, since the leaf translation
676 is unchanged. Work around the erratum by invalidating the walk cache
677 entries for the trampoline before entering the kernel proper.
679 config ARM64_WORKAROUND_REPEAT_TLBI
682 config QCOM_FALKOR_ERRATUM_1009
683 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
685 select ARM64_WORKAROUND_REPEAT_TLBI
687 On Falkor v1, the CPU may prematurely complete a DSB following a
688 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
689 one more time to fix the issue.
693 config QCOM_QDF2400_ERRATUM_0065
694 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
697 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
698 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
699 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
703 config SOCIONEXT_SYNQUACER_PREITS
704 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
707 Socionext Synquacer SoCs implement a separate h/w block to generate
708 MSI doorbell writes with non-zero values for the device ID.
712 config HISILICON_ERRATUM_161600802
713 bool "Hip07 161600802: Erroneous redistributor VLPI base"
716 The HiSilicon Hip07 SoC uses the wrong redistributor base
717 when issued ITS commands such as VMOVP and VMAPP, and requires
718 a 128kB offset to be applied to the target address in this commands.
722 config QCOM_FALKOR_ERRATUM_E1041
723 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
726 Falkor CPU may speculatively fetch instructions from an improper
727 memory location when MMU translation is changed from SCTLR_ELn[M]=1
728 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
732 config FUJITSU_ERRATUM_010001
733 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
736 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
737 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
738 accesses may cause undefined fault (Data abort, DFSC=0b111111).
739 This fault occurs under a specific hardware condition when a
740 load/store instruction performs an address translation using:
741 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
742 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
743 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
744 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
746 The workaround is to ensure these bits are clear in TCR_ELx.
747 The workaround only affects the Fujitsu-A64FX.
756 default ARM64_4K_PAGES
758 Page size (translation granule) configuration.
760 config ARM64_4K_PAGES
763 This feature enables 4KB pages support.
765 config ARM64_16K_PAGES
768 The system will use 16KB pages support. AArch32 emulation
769 requires applications compiled with 16K (or a multiple of 16K)
772 config ARM64_64K_PAGES
775 This feature enables 64KB pages support (4KB by default)
776 allowing only two levels of page tables and faster TLB
777 look-up. AArch32 emulation requires applications compiled
778 with 64K aligned segments.
783 prompt "Virtual address space size"
784 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
785 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
786 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
788 Allows choosing one of multiple possible virtual address
789 space sizes. The level of translation table is determined by
790 a combination of page size and virtual address space size.
792 config ARM64_VA_BITS_36
793 bool "36-bit" if EXPERT
794 depends on ARM64_16K_PAGES
796 config ARM64_VA_BITS_39
798 depends on ARM64_4K_PAGES
800 config ARM64_VA_BITS_42
802 depends on ARM64_64K_PAGES
804 config ARM64_VA_BITS_47
806 depends on ARM64_16K_PAGES
808 config ARM64_VA_BITS_48
811 config ARM64_VA_BITS_52
813 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
815 Enable 52-bit virtual addressing for userspace when explicitly
816 requested via a hint to mmap(). The kernel will also use 52-bit
817 virtual addresses for its own mappings (provided HW support for
818 this feature is available, otherwise it reverts to 48-bit).
820 NOTE: Enabling 52-bit virtual addressing in conjunction with
821 ARMv8.3 Pointer Authentication will result in the PAC being
822 reduced from 7 bits to 3 bits, which may have a significant
823 impact on its susceptibility to brute-force attacks.
825 If unsure, select 48-bit virtual addressing instead.
829 config ARM64_FORCE_52BIT
830 bool "Force 52-bit virtual addresses for userspace"
831 depends on ARM64_VA_BITS_52 && EXPERT
833 For systems with 52-bit userspace VAs enabled, the kernel will attempt
834 to maintain compatibility with older software by providing 48-bit VAs
835 unless a hint is supplied to mmap.
837 This configuration option disables the 48-bit compatibility logic, and
838 forces all userspace addresses to be 52-bit on HW that supports it. One
839 should only enable this configuration option for stress testing userspace
840 memory management code. If unsure say N here.
844 default 36 if ARM64_VA_BITS_36
845 default 39 if ARM64_VA_BITS_39
846 default 42 if ARM64_VA_BITS_42
847 default 47 if ARM64_VA_BITS_47
848 default 48 if ARM64_VA_BITS_48
849 default 52 if ARM64_VA_BITS_52
852 prompt "Physical address space size"
853 default ARM64_PA_BITS_48
855 Choose the maximum physical address range that the kernel will
858 config ARM64_PA_BITS_48
861 config ARM64_PA_BITS_52
862 bool "52-bit (ARMv8.2)"
863 depends on ARM64_64K_PAGES
864 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
866 Enable support for a 52-bit physical address space, introduced as
867 part of the ARMv8.2-LPA extension.
869 With this enabled, the kernel will also continue to work on CPUs that
870 do not support ARMv8.2-LPA, but with some added memory overhead (and
871 minor performance overhead).
877 default 48 if ARM64_PA_BITS_48
878 default 52 if ARM64_PA_BITS_52
882 default CPU_LITTLE_ENDIAN
884 Select the endianness of data accesses performed by the CPU. Userspace
885 applications will need to be compiled and linked for the endianness
886 that is selected here.
888 config CPU_BIG_ENDIAN
889 bool "Build big-endian kernel"
891 Say Y if you plan on running a kernel with a big-endian userspace.
893 config CPU_LITTLE_ENDIAN
894 bool "Build little-endian kernel"
896 Say Y if you plan on running a kernel with a little-endian userspace.
897 This is usually the case for distributions targeting arm64.
902 bool "Multi-core scheduler support"
904 Multi-core scheduler support improves the CPU scheduler's decision
905 making when dealing with multi-core CPU chips at a cost of slightly
906 increased overhead in some places. If unsure say N here.
909 bool "SMT scheduler support"
911 Improves the CPU scheduler's decision making when dealing with
912 MultiThreading at a cost of slightly increased overhead in some
913 places. If unsure say N here.
916 int "Maximum number of CPUs (2-4096)"
921 bool "Support for hot-pluggable CPUs"
922 select GENERIC_IRQ_MIGRATION
924 Say Y here to experiment with turning CPUs off and on. CPUs
925 can be controlled through /sys/devices/system/cpu.
927 # Common NUMA Features
929 bool "Numa Memory Allocation and Scheduler Support"
930 select ACPI_NUMA if ACPI
933 Enable NUMA (Non Uniform Memory Access) support.
935 The kernel will try to allocate memory used by a CPU on the
936 local memory of the CPU and add some more
937 NUMA awareness to the kernel.
940 int "Maximum NUMA Nodes (as a power of 2)"
943 depends on NEED_MULTIPLE_NODES
945 Specify the maximum number of NUMA Nodes available on the target
946 system. Increases memory reserved to accommodate various tables.
948 config USE_PERCPU_NUMA_NODE_ID
952 config HAVE_SETUP_PER_CPU_AREA
956 config NEED_PER_CPU_EMBED_FIRST_CHUNK
963 source "kernel/Kconfig.hz"
965 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
968 config ARCH_SPARSEMEM_ENABLE
970 select SPARSEMEM_VMEMMAP_ENABLE
972 config ARCH_SPARSEMEM_DEFAULT
973 def_bool ARCH_SPARSEMEM_ENABLE
975 config ARCH_SELECT_MEMORY_MODEL
976 def_bool ARCH_SPARSEMEM_ENABLE
978 config ARCH_FLATMEM_ENABLE
981 config HAVE_ARCH_PFN_VALID
984 config HW_PERF_EVENTS
988 config SYS_SUPPORTS_HUGETLBFS
991 config ARCH_WANT_HUGE_PMD_SHARE
993 config ARCH_HAS_CACHE_LINE_SIZE
996 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
997 def_bool y if PGTABLE_LEVELS > 2
1000 bool "Enable seccomp to safely compute untrusted bytecode"
1002 This kernel feature is useful for number crunching applications
1003 that may need to compute untrusted bytecode during their
1004 execution. By using pipes or other transports made available to
1005 the process as file descriptors supporting the read/write
1006 syscalls, it's possible to isolate those applications in
1007 their own address space using seccomp. Once seccomp is
1008 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1009 and the task is only allowed to execute a few safe syscalls
1010 defined by each seccomp mode.
1013 bool "Enable paravirtualization code"
1015 This changes the kernel so it can modify itself when it is run
1016 under a hypervisor, potentially improving performance significantly
1017 over full virtualization.
1019 config PARAVIRT_TIME_ACCOUNTING
1020 bool "Paravirtual steal time accounting"
1023 Select this option to enable fine granularity task steal time
1024 accounting. Time spent executing other tasks in parallel with
1025 the current vCPU is discounted from the vCPU power. To account for
1026 that, there can be a small performance impact.
1028 If in doubt, say N here.
1031 depends on PM_SLEEP_SMP
1033 bool "kexec system call"
1035 kexec is a system call that implements the ability to shutdown your
1036 current kernel, and to start another kernel. It is like a reboot
1037 but it is independent of the system firmware. And like a reboot
1038 you can start any kernel with it, not just Linux.
1041 bool "kexec file based system call"
1044 This is new version of kexec system call. This system call is
1045 file based and takes file descriptors as system call argument
1046 for kernel and initramfs as opposed to list of segments as
1047 accepted by previous system call.
1050 bool "Verify kernel signature during kexec_file_load() syscall"
1051 depends on KEXEC_FILE
1053 Select this option to verify a signature with loaded kernel
1054 image. If configured, any attempt of loading a image without
1055 valid signature will fail.
1057 In addition to that option, you need to enable signature
1058 verification for the corresponding kernel image type being
1059 loaded in order for this to work.
1061 config KEXEC_IMAGE_VERIFY_SIG
1062 bool "Enable Image signature verification support"
1064 depends on KEXEC_SIG
1065 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1067 Enable Image signature verification support.
1069 comment "Support for PE file signature verification disabled"
1070 depends on KEXEC_SIG
1071 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1074 bool "Build kdump crash kernel"
1076 Generate crash dump after being started by kexec. This should
1077 be normally only set in special crash dump kernels which are
1078 loaded in the main kernel with kexec-tools into a specially
1079 reserved region and then later executed after a crash by
1082 For more details see Documentation/admin-guide/kdump/kdump.rst
1089 bool "Xen guest support on ARM64"
1090 depends on ARM64 && OF
1094 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1096 config FORCE_MAX_ZONEORDER
1098 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1099 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1102 The kernel memory allocator divides physically contiguous memory
1103 blocks into "zones", where each zone is a power of two number of
1104 pages. This option selects the largest power of two that the kernel
1105 keeps in the memory allocator. If you need to allocate very large
1106 blocks of physically contiguous memory, then you may need to
1107 increase this value.
1109 This config option is actually maximum order plus one. For example,
1110 a value of 11 means that the largest free memory block is 2^10 pages.
1112 We make sure that we can allocate upto a HugePage size for each configuration.
1114 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1116 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1117 4M allocations matching the default size used by generic code.
1119 config UNMAP_KERNEL_AT_EL0
1120 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1123 Speculation attacks against some high-performance processors can
1124 be used to bypass MMU permission checks and leak kernel data to
1125 userspace. This can be defended against by unmapping the kernel
1126 when running in userspace, mapping it back in on exception entry
1127 via a trampoline page in the vector table.
1131 config HARDEN_BRANCH_PREDICTOR
1132 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1135 Speculation attacks against some high-performance processors rely on
1136 being able to manipulate the branch predictor for a victim context by
1137 executing aliasing branches in the attacker context. Such attacks
1138 can be partially mitigated against by clearing internal branch
1139 predictor state and limiting the prediction logic in some situations.
1141 This config option will take CPU-specific actions to harden the
1142 branch predictor against aliasing attacks and may rely on specific
1143 instruction sequences or control bits being set by the system
1148 config HARDEN_EL2_VECTORS
1149 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1152 Speculation attacks against some high-performance processors can
1153 be used to leak privileged information such as the vector base
1154 register, resulting in a potential defeat of the EL2 layout
1157 This config option will map the vectors to a fixed location,
1158 independent of the EL2 code mapping, so that revealing VBAR_EL2
1159 to an attacker does not give away any extra information. This
1160 only gets enabled on affected CPUs.
1165 bool "Speculative Store Bypass Disable" if EXPERT
1168 This enables mitigation of the bypassing of previous stores
1169 by speculative loads.
1173 config RODATA_FULL_DEFAULT_ENABLED
1174 bool "Apply r/o permissions of VM areas also to their linear aliases"
1177 Apply read-only attributes of VM areas to the linear alias of
1178 the backing pages as well. This prevents code or read-only data
1179 from being modified (inadvertently or intentionally) via another
1180 mapping of the same memory page. This additional enhancement can
1181 be turned off at runtime by passing rodata=[off|on] (and turned on
1182 with rodata=full if this option is set to 'n')
1184 This requires the linear region to be mapped down to pages,
1185 which may adversely affect performance in some cases.
1187 config ARM64_SW_TTBR0_PAN
1188 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1190 Enabling this option prevents the kernel from accessing
1191 user-space memory directly by pointing TTBR0_EL1 to a reserved
1192 zeroed area and reserved ASID. The user access routines
1193 restore the valid TTBR0_EL1 temporarily.
1195 config ARM64_TAGGED_ADDR_ABI
1196 bool "Enable the tagged user addresses syscall ABI"
1199 When this option is enabled, user applications can opt in to a
1200 relaxed ABI via prctl() allowing tagged addresses to be passed
1201 to system calls as pointer arguments. For details, see
1202 Documentation/arm64/tagged-address-abi.rst.
1205 bool "Kernel support for 32-bit EL0"
1206 depends on ARM64_4K_PAGES || EXPERT
1207 select COMPAT_BINFMT_ELF if BINFMT_ELF
1209 select OLD_SIGSUSPEND3
1210 select COMPAT_OLD_SIGACTION
1212 This option enables support for a 32-bit EL0 running under a 64-bit
1213 kernel at EL1. AArch32-specific components such as system calls,
1214 the user helper functions, VFP support and the ptrace interface are
1215 handled appropriately by the kernel.
1217 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1218 that you will only be able to execute AArch32 binaries that were compiled
1219 with page size aligned segments.
1221 If you want to execute 32-bit userspace applications, say Y.
1225 config KUSER_HELPERS
1226 bool "Enable kuser helpers page for 32-bit applications"
1229 Warning: disabling this option may break 32-bit user programs.
1231 Provide kuser helpers to compat tasks. The kernel provides
1232 helper code to userspace in read only form at a fixed location
1233 to allow userspace to be independent of the CPU type fitted to
1234 the system. This permits binaries to be run on ARMv4 through
1235 to ARMv8 without modification.
1237 See Documentation/arm/kernel_user_helpers.rst for details.
1239 However, the fixed address nature of these helpers can be used
1240 by ROP (return orientated programming) authors when creating
1243 If all of the binaries and libraries which run on your platform
1244 are built specifically for your platform, and make no use of
1245 these helpers, then you can turn this option off to hinder
1246 such exploits. However, in that case, if a binary or library
1247 relying on those helpers is run, it will not function correctly.
1249 Say N here only if you are absolutely certain that you do not
1250 need these helpers; otherwise, the safe option is to say Y.
1253 bool "Enable vDSO for 32-bit applications"
1254 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1255 select GENERIC_COMPAT_VDSO
1258 Place in the process address space of 32-bit applications an
1259 ELF shared object providing fast implementations of gettimeofday
1262 You must have a 32-bit build of glibc 2.22 or later for programs
1263 to seamlessly take advantage of this.
1265 menuconfig ARMV8_DEPRECATED
1266 bool "Emulate deprecated/obsolete ARMv8 instructions"
1269 Legacy software support may require certain instructions
1270 that have been deprecated or obsoleted in the architecture.
1272 Enable this config to enable selective emulation of these
1279 config SWP_EMULATION
1280 bool "Emulate SWP/SWPB instructions"
1282 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1283 they are always undefined. Say Y here to enable software
1284 emulation of these instructions for userspace using LDXR/STXR.
1286 In some older versions of glibc [<=2.8] SWP is used during futex
1287 trylock() operations with the assumption that the code will not
1288 be preempted. This invalid assumption may be more likely to fail
1289 with SWP emulation enabled, leading to deadlock of the user
1292 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1293 on an external transaction monitoring block called a global
1294 monitor to maintain update atomicity. If your system does not
1295 implement a global monitor, this option can cause programs that
1296 perform SWP operations to uncached memory to deadlock.
1300 config CP15_BARRIER_EMULATION
1301 bool "Emulate CP15 Barrier instructions"
1303 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1304 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1305 strongly recommended to use the ISB, DSB, and DMB
1306 instructions instead.
1308 Say Y here to enable software emulation of these
1309 instructions for AArch32 userspace code. When this option is
1310 enabled, CP15 barrier usage is traced which can help
1311 identify software that needs updating.
1315 config SETEND_EMULATION
1316 bool "Emulate SETEND instruction"
1318 The SETEND instruction alters the data-endianness of the
1319 AArch32 EL0, and is deprecated in ARMv8.
1321 Say Y here to enable software emulation of the instruction
1322 for AArch32 userspace code.
1324 Note: All the cpus on the system must have mixed endian support at EL0
1325 for this feature to be enabled. If a new CPU - which doesn't support mixed
1326 endian - is hotplugged in after this feature has been enabled, there could
1327 be unexpected results in the applications.
1334 menu "ARMv8.1 architectural features"
1336 config ARM64_HW_AFDBM
1337 bool "Support for hardware updates of the Access and Dirty page flags"
1340 The ARMv8.1 architecture extensions introduce support for
1341 hardware updates of the access and dirty information in page
1342 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1343 capable processors, accesses to pages with PTE_AF cleared will
1344 set this bit instead of raising an access flag fault.
1345 Similarly, writes to read-only pages with the DBM bit set will
1346 clear the read-only bit (AP[2]) instead of raising a
1349 Kernels built with this configuration option enabled continue
1350 to work on pre-ARMv8.1 hardware and the performance impact is
1351 minimal. If unsure, say Y.
1354 bool "Enable support for Privileged Access Never (PAN)"
1357 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1358 prevents the kernel or hypervisor from accessing user-space (EL0)
1361 Choosing this option will cause any unprotected (not using
1362 copy_to_user et al) memory access to fail with a permission fault.
1364 The feature is detected at runtime, and will remain as a 'nop'
1365 instruction if the cpu does not implement the feature.
1367 config ARM64_LSE_ATOMICS
1368 bool "Atomic instructions"
1369 depends on JUMP_LABEL
1372 As part of the Large System Extensions, ARMv8.1 introduces new
1373 atomic instructions that are designed specifically to scale in
1376 Say Y here to make use of these instructions for the in-kernel
1377 atomic routines. This incurs a small overhead on CPUs that do
1378 not support these instructions and requires the kernel to be
1379 built with binutils >= 2.25 in order for the new instructions
1383 bool "Enable support for Virtualization Host Extensions (VHE)"
1386 Virtualization Host Extensions (VHE) allow the kernel to run
1387 directly at EL2 (instead of EL1) on processors that support
1388 it. This leads to better performance for KVM, as they reduce
1389 the cost of the world switch.
1391 Selecting this option allows the VHE feature to be detected
1392 at runtime, and does not affect processors that do not
1393 implement this feature.
1397 menu "ARMv8.2 architectural features"
1400 bool "Enable support for User Access Override (UAO)"
1403 User Access Override (UAO; part of the ARMv8.2 Extensions)
1404 causes the 'unprivileged' variant of the load/store instructions to
1405 be overridden to be privileged.
1407 This option changes get_user() and friends to use the 'unprivileged'
1408 variant of the load/store instructions. This ensures that user-space
1409 really did have access to the supplied memory. When addr_limit is
1410 set to kernel memory the UAO bit will be set, allowing privileged
1411 access to kernel memory.
1413 Choosing this option will cause copy_to_user() et al to use user-space
1416 The feature is detected at runtime, the kernel will use the
1417 regular load/store instructions if the cpu does not implement the
1421 bool "Enable support for persistent memory"
1422 select ARCH_HAS_PMEM_API
1423 select ARCH_HAS_UACCESS_FLUSHCACHE
1425 Say Y to enable support for the persistent memory API based on the
1426 ARMv8.2 DCPoP feature.
1428 The feature is detected at runtime, and the kernel will use DC CVAC
1429 operations if DC CVAP is not supported (following the behaviour of
1430 DC CVAP itself if the system does not define a point of persistence).
1432 config ARM64_RAS_EXTN
1433 bool "Enable support for RAS CPU Extensions"
1436 CPUs that support the Reliability, Availability and Serviceability
1437 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1438 errors, classify them and report them to software.
1440 On CPUs with these extensions system software can use additional
1441 barriers to determine if faults are pending and read the
1442 classification from a new set of registers.
1444 Selecting this feature will allow the kernel to use these barriers
1445 and access the new registers if the system supports the extension.
1446 Platform RAS features may additionally depend on firmware support.
1449 bool "Enable support for Common Not Private (CNP) translations"
1451 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1453 Common Not Private (CNP) allows translation table entries to
1454 be shared between different PEs in the same inner shareable
1455 domain, so the hardware can use this fact to optimise the
1456 caching of such entries in the TLB.
1458 Selecting this option allows the CNP feature to be detected
1459 at runtime, and does not affect PEs that do not implement
1464 menu "ARMv8.3 architectural features"
1466 config ARM64_PTR_AUTH
1467 bool "Enable support for pointer authentication"
1469 depends on !KVM || ARM64_VHE
1471 Pointer authentication (part of the ARMv8.3 Extensions) provides
1472 instructions for signing and authenticating pointers against secret
1473 keys, which can be used to mitigate Return Oriented Programming (ROP)
1476 This option enables these instructions at EL0 (i.e. for userspace).
1478 Choosing this option will cause the kernel to initialise secret keys
1479 for each process at exec() time, with these keys being
1480 context-switched along with the process.
1482 The feature is detected at runtime. If the feature is not present in
1483 hardware it will not be advertised to userspace/KVM guest nor will it
1484 be enabled. However, KVM guest also require VHE mode and hence
1485 CONFIG_ARM64_VHE=y option to use this feature.
1490 bool "ARM Scalable Vector Extension support"
1492 depends on !KVM || ARM64_VHE
1494 The Scalable Vector Extension (SVE) is an extension to the AArch64
1495 execution state which complements and extends the SIMD functionality
1496 of the base architecture to support much larger vectors and to enable
1497 additional vectorisation opportunities.
1499 To enable use of this extension on CPUs that implement it, say Y.
1501 On CPUs that support the SVE2 extensions, this option will enable
1504 Note that for architectural reasons, firmware _must_ implement SVE
1505 support when running on SVE capable hardware. The required support
1508 * version 1.5 and later of the ARM Trusted Firmware
1509 * the AArch64 boot wrapper since commit 5e1261e08abf
1510 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1512 For other firmware implementations, consult the firmware documentation
1515 If you need the kernel to boot on SVE-capable hardware with broken
1516 firmware, you may need to say N here until you get your firmware
1517 fixed. Otherwise, you may experience firmware panics or lockups when
1518 booting the kernel. If unsure and you are not observing these
1519 symptoms, you should assume that it is safe to say Y.
1521 CPUs that support SVE are architecturally required to support the
1522 Virtualization Host Extensions (VHE), so the kernel makes no
1523 provision for supporting SVE alongside KVM without VHE enabled.
1524 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1525 KVM in the same kernel image.
1527 config ARM64_MODULE_PLTS
1528 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1530 select HAVE_MOD_ARCH_SPECIFIC
1532 Allocate PLTs when loading modules so that jumps and calls whose
1533 targets are too far away for their relative offsets to be encoded
1534 in the instructions themselves can be bounced via veneers in the
1535 module's PLT. This allows modules to be allocated in the generic
1536 vmalloc area after the dedicated module memory area has been
1539 When running with address space randomization (KASLR), the module
1540 region itself may be too far away for ordinary relative jumps and
1541 calls, and so in that case, module PLTs are required and cannot be
1544 Specific errata workaround(s) might also force module PLTs to be
1545 enabled (ARM64_ERRATUM_843419).
1547 config ARM64_PSEUDO_NMI
1548 bool "Support for NMI-like interrupts"
1549 select CONFIG_ARM_GIC_V3
1551 Adds support for mimicking Non-Maskable Interrupts through the use of
1552 GIC interrupt priority. This support requires version 3 or later of
1555 This high priority configuration for interrupts needs to be
1556 explicitly enabled by setting the kernel parameter
1557 "irqchip.gicv3_pseudo_nmi" to 1.
1562 config ARM64_DEBUG_PRIORITY_MASKING
1563 bool "Debug interrupt priority masking"
1565 This adds runtime checks to functions enabling/disabling
1566 interrupts when using priority masking. The additional checks verify
1567 the validity of ICC_PMR_EL1 when calling concerned functions.
1574 select ARCH_HAS_RELR
1576 This builds the kernel as a Position Independent Executable (PIE),
1577 which retains all relocation metadata required to relocate the
1578 kernel binary at runtime to a different virtual address than the
1579 address it was linked at.
1580 Since AArch64 uses the RELA relocation format, this requires a
1581 relocation pass at runtime even if the kernel is loaded at the
1582 same address it was linked at.
1584 config RANDOMIZE_BASE
1585 bool "Randomize the address of the kernel image"
1586 select ARM64_MODULE_PLTS if MODULES
1589 Randomizes the virtual address at which the kernel image is
1590 loaded, as a security feature that deters exploit attempts
1591 relying on knowledge of the location of kernel internals.
1593 It is the bootloader's job to provide entropy, by passing a
1594 random u64 value in /chosen/kaslr-seed at kernel entry.
1596 When booting via the UEFI stub, it will invoke the firmware's
1597 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1598 to the kernel proper. In addition, it will randomise the physical
1599 location of the kernel Image as well.
1603 config RANDOMIZE_MODULE_REGION_FULL
1604 bool "Randomize the module region over a 4 GB range"
1605 depends on RANDOMIZE_BASE
1608 Randomizes the location of the module region inside a 4 GB window
1609 covering the core kernel. This way, it is less likely for modules
1610 to leak information about the location of core kernel data structures
1611 but it does imply that function calls between modules and the core
1612 kernel will need to be resolved via veneers in the module PLT.
1614 When this option is not set, the module region will be randomized over
1615 a limited range that contains the [_stext, _etext] interval of the
1616 core kernel, so branch relocations are always in range.
1618 config CC_HAVE_STACKPROTECTOR_SYSREG
1619 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1621 config STACKPROTECTOR_PER_TASK
1623 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1629 config ARM64_ACPI_PARKING_PROTOCOL
1630 bool "Enable support for the ARM64 ACPI parking protocol"
1633 Enable support for the ARM64 ACPI parking protocol. If disabled
1634 the kernel will not allow booting through the ARM64 ACPI parking
1635 protocol even if the corresponding data is present in the ACPI
1639 string "Default kernel command string"
1642 Provide a set of default command-line options at build time by
1643 entering them here. As a minimum, you should specify the the
1644 root device (e.g. root=/dev/nfs).
1646 config CMDLINE_FORCE
1647 bool "Always use the default kernel command string"
1648 depends on CMDLINE != ""
1650 Always use the default kernel command string, even if the boot
1651 loader passes other arguments to the kernel.
1652 This is useful if you cannot or don't want to change the
1653 command-line options your boot loader passes to the kernel.
1659 bool "UEFI runtime support"
1660 depends on OF && !CPU_BIG_ENDIAN
1661 depends on KERNEL_MODE_NEON
1662 select ARCH_SUPPORTS_ACPI
1665 select EFI_PARAMS_FROM_FDT
1666 select EFI_RUNTIME_WRAPPERS
1671 This option provides support for runtime services provided
1672 by UEFI firmware (such as non-volatile variables, realtime
1673 clock, and platform reset). A UEFI stub is also provided to
1674 allow the kernel to be booted as an EFI application. This
1675 is only useful on systems that have UEFI firmware.
1678 bool "Enable support for SMBIOS (DMI) tables"
1682 This enables SMBIOS/DMI feature for systems.
1684 This option is only useful on systems that have UEFI firmware.
1685 However, even with this option, the resultant kernel should
1686 continue to boot on existing non-UEFI platforms.
1690 config SYSVIPC_COMPAT
1692 depends on COMPAT && SYSVIPC
1694 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1696 depends on HUGETLB_PAGE && MIGRATION
1698 menu "Power management options"
1700 source "kernel/power/Kconfig"
1702 config ARCH_HIBERNATION_POSSIBLE
1706 config ARCH_HIBERNATION_HEADER
1708 depends on HIBERNATION
1710 config ARCH_SUSPEND_POSSIBLE
1715 menu "CPU Power Management"
1717 source "drivers/cpuidle/Kconfig"
1719 source "drivers/cpufreq/Kconfig"
1723 source "drivers/firmware/Kconfig"
1725 source "drivers/acpi/Kconfig"
1727 source "arch/arm64/kvm/Kconfig"
1730 source "arch/arm64/crypto/Kconfig"