3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_SUPPORTS_MEMORY_FAILURE
27 select ARCH_SUPPORTS_ATOMIC_RMW
28 select ARCH_SUPPORTS_NUMA_BALANCING
29 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
30 select ARCH_WANT_FRAME_POINTERS
31 select ARCH_HAS_UBSAN_SANITIZE_ALL
35 select AUDIT_ARCH_COMPAT_GENERIC
36 select ARM_GIC_V2M if PCI
38 select ARM_GIC_V3_ITS if PCI
40 select BUILDTIME_EXTABLE_SORT
41 select CLONE_BACKWARDS
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select DCACHE_WORD_ACCESS
47 select GENERIC_ALLOCATOR
48 select GENERIC_ARCH_TOPOLOGY
49 select GENERIC_CLOCKEVENTS
50 select GENERIC_CLOCKEVENTS_BROADCAST
51 select GENERIC_CPU_AUTOPROBE
52 select GENERIC_EARLY_IOREMAP
53 select GENERIC_IDLE_POLL_SETUP
54 select GENERIC_IRQ_PROBE
55 select GENERIC_IRQ_SHOW
56 select GENERIC_IRQ_SHOW_LEVEL
57 select GENERIC_PCI_IOMAP
58 select GENERIC_SCHED_CLOCK
59 select GENERIC_SMP_IDLE_THREAD
60 select GENERIC_STRNCPY_FROM_USER
61 select GENERIC_STRNLEN_USER
62 select GENERIC_TIME_VSYSCALL
63 select HANDLE_DOMAIN_IRQ
64 select HARDIRQS_SW_RESEND
65 select HAVE_ACPI_APEI if (ACPI && EFI)
66 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
67 select HAVE_ARCH_AUDITSYSCALL
68 select HAVE_ARCH_BITREVERSE
69 select HAVE_ARCH_HUGE_VMAP
70 select HAVE_ARCH_JUMP_LABEL
71 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
73 select HAVE_ARCH_MMAP_RND_BITS
74 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
75 select HAVE_ARCH_SECCOMP_FILTER
76 select HAVE_ARCH_TRACEHOOK
77 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
78 select HAVE_ARCH_VMAP_STACK
81 select HAVE_C_RECORDMCOUNT
82 select HAVE_CC_STACKPROTECTOR
83 select HAVE_CMPXCHG_DOUBLE
84 select HAVE_CMPXCHG_LOCAL
85 select HAVE_CONTEXT_TRACKING
86 select HAVE_DEBUG_BUGVERBOSE
87 select HAVE_DEBUG_KMEMLEAK
88 select HAVE_DMA_API_DEBUG
89 select HAVE_DMA_CONTIGUOUS
90 select HAVE_DYNAMIC_FTRACE
91 select HAVE_EFFICIENT_UNALIGNED_ACCESS
92 select HAVE_FTRACE_MCOUNT_RECORD
93 select HAVE_FUNCTION_TRACER
94 select HAVE_FUNCTION_GRAPH_TRACER
95 select HAVE_GCC_PLUGINS
96 select HAVE_GENERIC_DMA_COHERENT
97 select HAVE_HW_BREAKPOINT if PERF_EVENTS
98 select HAVE_IRQ_TIME_ACCOUNTING
100 select HAVE_MEMBLOCK_NODE_MAP if NUMA
102 select HAVE_PATA_PLATFORM
103 select HAVE_PERF_EVENTS
104 select HAVE_PERF_REGS
105 select HAVE_PERF_USER_STACK_DUMP
106 select HAVE_REGS_AND_STACK_ACCESS_API
107 select HAVE_RCU_TABLE_FREE
108 select HAVE_SYSCALL_TRACEPOINTS
110 select HAVE_KRETPROBES
111 select IOMMU_DMA if IOMMU_SUPPORT
113 select IRQ_FORCED_THREADING
114 select MODULES_USE_ELF_RELA
117 select OF_EARLY_FLATTREE
118 select OF_RESERVED_MEM
119 select PCI_ECAM if ACPI
124 select SYSCTL_EXCEPTION_TRACE
125 select THREAD_INFO_IN_TASK
127 ARM 64-bit (AArch64) Linux support.
132 config ARCH_PHYS_ADDR_T_64BIT
138 config ARM64_PAGE_SHIFT
140 default 16 if ARM64_64K_PAGES
141 default 14 if ARM64_16K_PAGES
144 config ARM64_CONT_SHIFT
146 default 5 if ARM64_64K_PAGES
147 default 7 if ARM64_16K_PAGES
150 config ARCH_MMAP_RND_BITS_MIN
151 default 14 if ARM64_64K_PAGES
152 default 16 if ARM64_16K_PAGES
155 # max bits determined by the following formula:
156 # VA_BITS - PAGE_SHIFT - 3
157 config ARCH_MMAP_RND_BITS_MAX
158 default 19 if ARM64_VA_BITS=36
159 default 24 if ARM64_VA_BITS=39
160 default 27 if ARM64_VA_BITS=42
161 default 30 if ARM64_VA_BITS=47
162 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
163 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
164 default 33 if ARM64_VA_BITS=48
165 default 14 if ARM64_64K_PAGES
166 default 16 if ARM64_16K_PAGES
169 config ARCH_MMAP_RND_COMPAT_BITS_MIN
170 default 7 if ARM64_64K_PAGES
171 default 9 if ARM64_16K_PAGES
174 config ARCH_MMAP_RND_COMPAT_BITS_MAX
180 config STACKTRACE_SUPPORT
183 config ILLEGAL_POINTER_VALUE
185 default 0xdead000000000000
187 config LOCKDEP_SUPPORT
190 config TRACE_IRQFLAGS_SUPPORT
193 config RWSEM_XCHGADD_ALGORITHM
200 config GENERIC_BUG_RELATIVE_POINTERS
202 depends on GENERIC_BUG
204 config GENERIC_HWEIGHT
210 config GENERIC_CALIBRATE_DELAY
216 config HAVE_GENERIC_GUP
219 config ARCH_DMA_ADDR_T_64BIT
222 config NEED_DMA_MAP_STATE
225 config NEED_SG_DMA_LENGTH
237 config KERNEL_MODE_NEON
240 config FIX_EARLYCON_MEM
243 config PGTABLE_LEVELS
245 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
246 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
247 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
248 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
249 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
250 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
252 config ARCH_SUPPORTS_UPROBES
255 config ARCH_PROC_KCORE_TEXT
258 source "init/Kconfig"
260 source "kernel/Kconfig.freezer"
262 source "arch/arm64/Kconfig.platforms"
269 This feature enables support for PCI bus system. If you say Y
270 here, the kernel will include drivers and infrastructure code
271 to support PCI bus devices.
276 config PCI_DOMAINS_GENERIC
282 source "drivers/pci/Kconfig"
286 menu "Kernel Features"
288 menu "ARM errata workarounds via the alternatives framework"
290 config ARM64_ERRATUM_826319
291 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
294 This option adds an alternative code sequence to work around ARM
295 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
296 AXI master interface and an L2 cache.
298 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
299 and is unable to accept a certain write via this interface, it will
300 not progress on read data presented on the read data channel and the
303 The workaround promotes data cache clean instructions to
304 data cache clean-and-invalidate.
305 Please note that this does not necessarily enable the workaround,
306 as it depends on the alternative framework, which will only patch
307 the kernel if an affected CPU is detected.
311 config ARM64_ERRATUM_827319
312 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
315 This option adds an alternative code sequence to work around ARM
316 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
317 master interface and an L2 cache.
319 Under certain conditions this erratum can cause a clean line eviction
320 to occur at the same time as another transaction to the same address
321 on the AMBA 5 CHI interface, which can cause data corruption if the
322 interconnect reorders the two transactions.
324 The workaround promotes data cache clean instructions to
325 data cache clean-and-invalidate.
326 Please note that this does not necessarily enable the workaround,
327 as it depends on the alternative framework, which will only patch
328 the kernel if an affected CPU is detected.
332 config ARM64_ERRATUM_824069
333 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
336 This option adds an alternative code sequence to work around ARM
337 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
338 to a coherent interconnect.
340 If a Cortex-A53 processor is executing a store or prefetch for
341 write instruction at the same time as a processor in another
342 cluster is executing a cache maintenance operation to the same
343 address, then this erratum might cause a clean cache line to be
344 incorrectly marked as dirty.
346 The workaround promotes data cache clean instructions to
347 data cache clean-and-invalidate.
348 Please note that this option does not necessarily enable the
349 workaround, as it depends on the alternative framework, which will
350 only patch the kernel if an affected CPU is detected.
354 config ARM64_ERRATUM_819472
355 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
358 This option adds an alternative code sequence to work around ARM
359 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
360 present when it is connected to a coherent interconnect.
362 If the processor is executing a load and store exclusive sequence at
363 the same time as a processor in another cluster is executing a cache
364 maintenance operation to the same address, then this erratum might
365 cause data corruption.
367 The workaround promotes data cache clean instructions to
368 data cache clean-and-invalidate.
369 Please note that this does not necessarily enable the workaround,
370 as it depends on the alternative framework, which will only patch
371 the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_832075
376 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
379 This option adds an alternative code sequence to work around ARM
380 erratum 832075 on Cortex-A57 parts up to r1p2.
382 Affected Cortex-A57 parts might deadlock when exclusive load/store
383 instructions to Write-Back memory are mixed with Device loads.
385 The workaround is to promote device loads to use Load-Acquire
387 Please note that this does not necessarily enable the workaround,
388 as it depends on the alternative framework, which will only patch
389 the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_834220
394 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
398 This option adds an alternative code sequence to work around ARM
399 erratum 834220 on Cortex-A57 parts up to r1p2.
401 Affected Cortex-A57 parts might report a Stage 2 translation
402 fault as the result of a Stage 1 fault for load crossing a
403 page boundary when there is a permission or device memory
404 alignment fault at Stage 1 and a translation fault at Stage 2.
406 The workaround is to verify that the Stage 1 translation
407 doesn't generate a fault before handling the Stage 2 fault.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
414 config ARM64_ERRATUM_845719
415 bool "Cortex-A53: 845719: a load might read incorrect data"
419 This option adds an alternative code sequence to work around ARM
420 erratum 845719 on Cortex-A53 parts up to r0p4.
422 When running a compat (AArch32) userspace on an affected Cortex-A53
423 part, a load at EL0 from a virtual address that matches the bottom 32
424 bits of the virtual address used by a recent load at (AArch64) EL1
425 might return incorrect data.
427 The workaround is to write the contextidr_el1 register on exception
428 return to a 32-bit task.
429 Please note that this does not necessarily enable the workaround,
430 as it depends on the alternative framework, which will only patch
431 the kernel if an affected CPU is detected.
435 config ARM64_ERRATUM_843419
436 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
438 select ARM64_MODULE_CMODEL_LARGE if MODULES
440 This option links the kernel with '--fix-cortex-a53-843419' and
441 builds modules using the large memory model in order to avoid the use
442 of the ADRP instruction, which can cause a subsequent memory access
443 to use an incorrect address on Cortex-A53 parts up to r0p4.
447 config CAVIUM_ERRATUM_22375
448 bool "Cavium erratum 22375, 24313"
451 Enable workaround for erratum 22375, 24313.
453 This implements two gicv3-its errata workarounds for ThunderX. Both
454 with small impact affecting only ITS table allocation.
456 erratum 22375: only alloc 8MB table size
457 erratum 24313: ignore memory access type
459 The fixes are in ITS initialization and basically ignore memory access
460 type and table size provided by the TYPER and BASER registers.
464 config CAVIUM_ERRATUM_23144
465 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
469 ITS SYNC command hang for cross node io and collections/cpu mapping.
473 config CAVIUM_ERRATUM_23154
474 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
477 The gicv3 of ThunderX requires a modified version for
478 reading the IAR status to ensure data synchronization
479 (access to icc_iar1_el1 is not sync'ed before and after).
483 config CAVIUM_ERRATUM_27456
484 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
487 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
488 instructions may cause the icache to become corrupted if it
489 contains data for a non-current ASID. The fix is to
490 invalidate the icache when changing the mm context.
494 config CAVIUM_ERRATUM_30115
495 bool "Cavium erratum 30115: Guest may disable interrupts in host"
498 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
499 1.2, and T83 Pass 1.0, KVM guest execution may disable
500 interrupts in host. Trapping both GICv3 group-0 and group-1
501 accesses sidesteps the issue.
505 config QCOM_FALKOR_ERRATUM_1003
506 bool "Falkor E1003: Incorrect translation due to ASID change"
508 select ARM64_PAN if ARM64_SW_TTBR0_PAN
510 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
511 and BADDR are changed together in TTBRx_EL1. The workaround for this
512 issue is to use a reserved ASID in cpu_do_switch_mm() before
513 switching to the new ASID. Saying Y here selects ARM64_PAN if
514 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
515 maintaining the E1003 workaround in the software PAN emulation code
516 would be an unnecessary complication. The affected Falkor v1 CPU
517 implements ARMv8.1 hardware PAN support and using hardware PAN
518 support versus software PAN emulation is mutually exclusive at
523 config QCOM_FALKOR_ERRATUM_1009
524 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
527 On Falkor v1, the CPU may prematurely complete a DSB following a
528 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
529 one more time to fix the issue.
533 config QCOM_QDF2400_ERRATUM_0065
534 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
537 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
538 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
539 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
548 default ARM64_4K_PAGES
550 Page size (translation granule) configuration.
552 config ARM64_4K_PAGES
555 This feature enables 4KB pages support.
557 config ARM64_16K_PAGES
560 The system will use 16KB pages support. AArch32 emulation
561 requires applications compiled with 16K (or a multiple of 16K)
564 config ARM64_64K_PAGES
567 This feature enables 64KB pages support (4KB by default)
568 allowing only two levels of page tables and faster TLB
569 look-up. AArch32 emulation requires applications compiled
570 with 64K aligned segments.
575 prompt "Virtual address space size"
576 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
577 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
578 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
580 Allows choosing one of multiple possible virtual address
581 space sizes. The level of translation table is determined by
582 a combination of page size and virtual address space size.
584 config ARM64_VA_BITS_36
585 bool "36-bit" if EXPERT
586 depends on ARM64_16K_PAGES
588 config ARM64_VA_BITS_39
590 depends on ARM64_4K_PAGES
592 config ARM64_VA_BITS_42
594 depends on ARM64_64K_PAGES
596 config ARM64_VA_BITS_47
598 depends on ARM64_16K_PAGES
600 config ARM64_VA_BITS_48
607 default 36 if ARM64_VA_BITS_36
608 default 39 if ARM64_VA_BITS_39
609 default 42 if ARM64_VA_BITS_42
610 default 47 if ARM64_VA_BITS_47
611 default 48 if ARM64_VA_BITS_48
613 config CPU_BIG_ENDIAN
614 bool "Build big-endian kernel"
616 Say Y if you plan on running a kernel in big-endian mode.
619 bool "Multi-core scheduler support"
621 Multi-core scheduler support improves the CPU scheduler's decision
622 making when dealing with multi-core CPU chips at a cost of slightly
623 increased overhead in some places. If unsure say N here.
626 bool "SMT scheduler support"
628 Improves the CPU scheduler's decision making when dealing with
629 MultiThreading at a cost of slightly increased overhead in some
630 places. If unsure say N here.
633 int "Maximum number of CPUs (2-4096)"
635 # These have to remain sorted largest to smallest
639 bool "Support for hot-pluggable CPUs"
640 select GENERIC_IRQ_MIGRATION
642 Say Y here to experiment with turning CPUs off and on. CPUs
643 can be controlled through /sys/devices/system/cpu.
645 # Common NUMA Features
647 bool "Numa Memory Allocation and Scheduler Support"
648 select ACPI_NUMA if ACPI
651 Enable NUMA (Non Uniform Memory Access) support.
653 The kernel will try to allocate memory used by a CPU on the
654 local memory of the CPU and add some more
655 NUMA awareness to the kernel.
658 int "Maximum NUMA Nodes (as a power of 2)"
661 depends on NEED_MULTIPLE_NODES
663 Specify the maximum number of NUMA Nodes available on the target
664 system. Increases memory reserved to accommodate various tables.
666 config USE_PERCPU_NUMA_NODE_ID
670 config HAVE_SETUP_PER_CPU_AREA
674 config NEED_PER_CPU_EMBED_FIRST_CHUNK
682 source kernel/Kconfig.preempt
683 source kernel/Kconfig.hz
685 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
688 config ARCH_HAS_HOLES_MEMORYMODEL
689 def_bool y if SPARSEMEM
691 config ARCH_SPARSEMEM_ENABLE
693 select SPARSEMEM_VMEMMAP_ENABLE
695 config ARCH_SPARSEMEM_DEFAULT
696 def_bool ARCH_SPARSEMEM_ENABLE
698 config ARCH_SELECT_MEMORY_MODEL
699 def_bool ARCH_SPARSEMEM_ENABLE
701 config HAVE_ARCH_PFN_VALID
702 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
704 config HW_PERF_EVENTS
708 config SYS_SUPPORTS_HUGETLBFS
711 config ARCH_WANT_HUGE_PMD_SHARE
712 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
714 config ARCH_HAS_CACHE_LINE_SIZE
720 bool "Enable seccomp to safely compute untrusted bytecode"
722 This kernel feature is useful for number crunching applications
723 that may need to compute untrusted bytecode during their
724 execution. By using pipes or other transports made available to
725 the process as file descriptors supporting the read/write
726 syscalls, it's possible to isolate those applications in
727 their own address space using seccomp. Once seccomp is
728 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
729 and the task is only allowed to execute a few safe syscalls
730 defined by each seccomp mode.
733 bool "Enable paravirtualization code"
735 This changes the kernel so it can modify itself when it is run
736 under a hypervisor, potentially improving performance significantly
737 over full virtualization.
739 config PARAVIRT_TIME_ACCOUNTING
740 bool "Paravirtual steal time accounting"
744 Select this option to enable fine granularity task steal time
745 accounting. Time spent executing other tasks in parallel with
746 the current vCPU is discounted from the vCPU power. To account for
747 that, there can be a small performance impact.
749 If in doubt, say N here.
752 depends on PM_SLEEP_SMP
754 bool "kexec system call"
756 kexec is a system call that implements the ability to shutdown your
757 current kernel, and to start another kernel. It is like a reboot
758 but it is independent of the system firmware. And like a reboot
759 you can start any kernel with it, not just Linux.
762 bool "Build kdump crash kernel"
764 Generate crash dump after being started by kexec. This should
765 be normally only set in special crash dump kernels which are
766 loaded in the main kernel with kexec-tools into a specially
767 reserved region and then later executed after a crash by
770 For more details see Documentation/kdump/kdump.txt
777 bool "Xen guest support on ARM64"
778 depends on ARM64 && OF
782 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
784 config FORCE_MAX_ZONEORDER
786 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
787 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
790 The kernel memory allocator divides physically contiguous memory
791 blocks into "zones", where each zone is a power of two number of
792 pages. This option selects the largest power of two that the kernel
793 keeps in the memory allocator. If you need to allocate very large
794 blocks of physically contiguous memory, then you may need to
797 This config option is actually maximum order plus one. For example,
798 a value of 11 means that the largest free memory block is 2^10 pages.
800 We make sure that we can allocate upto a HugePage size for each configuration.
802 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
804 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
805 4M allocations matching the default size used by generic code.
807 menuconfig ARMV8_DEPRECATED
808 bool "Emulate deprecated/obsolete ARMv8 instructions"
811 Legacy software support may require certain instructions
812 that have been deprecated or obsoleted in the architecture.
814 Enable this config to enable selective emulation of these
822 bool "Emulate SWP/SWPB instructions"
824 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
825 they are always undefined. Say Y here to enable software
826 emulation of these instructions for userspace using LDXR/STXR.
828 In some older versions of glibc [<=2.8] SWP is used during futex
829 trylock() operations with the assumption that the code will not
830 be preempted. This invalid assumption may be more likely to fail
831 with SWP emulation enabled, leading to deadlock of the user
834 NOTE: when accessing uncached shared regions, LDXR/STXR rely
835 on an external transaction monitoring block called a global
836 monitor to maintain update atomicity. If your system does not
837 implement a global monitor, this option can cause programs that
838 perform SWP operations to uncached memory to deadlock.
842 config CP15_BARRIER_EMULATION
843 bool "Emulate CP15 Barrier instructions"
845 The CP15 barrier instructions - CP15ISB, CP15DSB, and
846 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
847 strongly recommended to use the ISB, DSB, and DMB
848 instructions instead.
850 Say Y here to enable software emulation of these
851 instructions for AArch32 userspace code. When this option is
852 enabled, CP15 barrier usage is traced which can help
853 identify software that needs updating.
857 config SETEND_EMULATION
858 bool "Emulate SETEND instruction"
860 The SETEND instruction alters the data-endianness of the
861 AArch32 EL0, and is deprecated in ARMv8.
863 Say Y here to enable software emulation of the instruction
864 for AArch32 userspace code.
866 Note: All the cpus on the system must have mixed endian support at EL0
867 for this feature to be enabled. If a new CPU - which doesn't support mixed
868 endian - is hotplugged in after this feature has been enabled, there could
869 be unexpected results in the applications.
874 config ARM64_SW_TTBR0_PAN
875 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
877 Enabling this option prevents the kernel from accessing
878 user-space memory directly by pointing TTBR0_EL1 to a reserved
879 zeroed area and reserved ASID. The user access routines
880 restore the valid TTBR0_EL1 temporarily.
882 menu "ARMv8.1 architectural features"
884 config ARM64_HW_AFDBM
885 bool "Support for hardware updates of the Access and Dirty page flags"
888 The ARMv8.1 architecture extensions introduce support for
889 hardware updates of the access and dirty information in page
890 table entries. When enabled in TCR_EL1 (HA and HD bits) on
891 capable processors, accesses to pages with PTE_AF cleared will
892 set this bit instead of raising an access flag fault.
893 Similarly, writes to read-only pages with the DBM bit set will
894 clear the read-only bit (AP[2]) instead of raising a
897 Kernels built with this configuration option enabled continue
898 to work on pre-ARMv8.1 hardware and the performance impact is
899 minimal. If unsure, say Y.
902 bool "Enable support for Privileged Access Never (PAN)"
905 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
906 prevents the kernel or hypervisor from accessing user-space (EL0)
909 Choosing this option will cause any unprotected (not using
910 copy_to_user et al) memory access to fail with a permission fault.
912 The feature is detected at runtime, and will remain as a 'nop'
913 instruction if the cpu does not implement the feature.
915 config ARM64_LSE_ATOMICS
916 bool "Atomic instructions"
918 As part of the Large System Extensions, ARMv8.1 introduces new
919 atomic instructions that are designed specifically to scale in
922 Say Y here to make use of these instructions for the in-kernel
923 atomic routines. This incurs a small overhead on CPUs that do
924 not support these instructions and requires the kernel to be
925 built with binutils >= 2.25.
928 bool "Enable support for Virtualization Host Extensions (VHE)"
931 Virtualization Host Extensions (VHE) allow the kernel to run
932 directly at EL2 (instead of EL1) on processors that support
933 it. This leads to better performance for KVM, as they reduce
934 the cost of the world switch.
936 Selecting this option allows the VHE feature to be detected
937 at runtime, and does not affect processors that do not
938 implement this feature.
942 menu "ARMv8.2 architectural features"
945 bool "Enable support for User Access Override (UAO)"
948 User Access Override (UAO; part of the ARMv8.2 Extensions)
949 causes the 'unprivileged' variant of the load/store instructions to
950 be overriden to be privileged.
952 This option changes get_user() and friends to use the 'unprivileged'
953 variant of the load/store instructions. This ensures that user-space
954 really did have access to the supplied memory. When addr_limit is
955 set to kernel memory the UAO bit will be set, allowing privileged
956 access to kernel memory.
958 Choosing this option will cause copy_to_user() et al to use user-space
961 The feature is detected at runtime, the kernel will use the
962 regular load/store instructions if the cpu does not implement the
966 bool "Enable support for persistent memory"
967 select ARCH_HAS_PMEM_API
968 select ARCH_HAS_UACCESS_FLUSHCACHE
970 Say Y to enable support for the persistent memory API based on the
971 ARMv8.2 DCPoP feature.
973 The feature is detected at runtime, and the kernel will use DC CVAC
974 operations if DC CVAP is not supported (following the behaviour of
975 DC CVAP itself if the system does not define a point of persistence).
979 config ARM64_MODULE_CMODEL_LARGE
982 config ARM64_MODULE_PLTS
984 select ARM64_MODULE_CMODEL_LARGE
985 select HAVE_MOD_ARCH_SPECIFIC
990 This builds the kernel as a Position Independent Executable (PIE),
991 which retains all relocation metadata required to relocate the
992 kernel binary at runtime to a different virtual address than the
993 address it was linked at.
994 Since AArch64 uses the RELA relocation format, this requires a
995 relocation pass at runtime even if the kernel is loaded at the
996 same address it was linked at.
998 config RANDOMIZE_BASE
999 bool "Randomize the address of the kernel image"
1000 select ARM64_MODULE_PLTS if MODULES
1003 Randomizes the virtual address at which the kernel image is
1004 loaded, as a security feature that deters exploit attempts
1005 relying on knowledge of the location of kernel internals.
1007 It is the bootloader's job to provide entropy, by passing a
1008 random u64 value in /chosen/kaslr-seed at kernel entry.
1010 When booting via the UEFI stub, it will invoke the firmware's
1011 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1012 to the kernel proper. In addition, it will randomise the physical
1013 location of the kernel Image as well.
1017 config RANDOMIZE_MODULE_REGION_FULL
1018 bool "Randomize the module region independently from the core kernel"
1019 depends on RANDOMIZE_BASE
1022 Randomizes the location of the module region without considering the
1023 location of the core kernel. This way, it is impossible for modules
1024 to leak information about the location of core kernel data structures
1025 but it does imply that function calls between modules and the core
1026 kernel will need to be resolved via veneers in the module PLT.
1028 When this option is not set, the module region will be randomized over
1029 a limited range that contains the [_stext, _etext] interval of the
1030 core kernel, so branch relocations are always in range.
1036 config ARM64_ACPI_PARKING_PROTOCOL
1037 bool "Enable support for the ARM64 ACPI parking protocol"
1040 Enable support for the ARM64 ACPI parking protocol. If disabled
1041 the kernel will not allow booting through the ARM64 ACPI parking
1042 protocol even if the corresponding data is present in the ACPI
1046 string "Default kernel command string"
1049 Provide a set of default command-line options at build time by
1050 entering them here. As a minimum, you should specify the the
1051 root device (e.g. root=/dev/nfs).
1053 config CMDLINE_FORCE
1054 bool "Always use the default kernel command string"
1056 Always use the default kernel command string, even if the boot
1057 loader passes other arguments to the kernel.
1058 This is useful if you cannot or don't want to change the
1059 command-line options your boot loader passes to the kernel.
1065 bool "UEFI runtime support"
1066 depends on OF && !CPU_BIG_ENDIAN
1069 select EFI_PARAMS_FROM_FDT
1070 select EFI_RUNTIME_WRAPPERS
1075 This option provides support for runtime services provided
1076 by UEFI firmware (such as non-volatile variables, realtime
1077 clock, and platform reset). A UEFI stub is also provided to
1078 allow the kernel to be booted as an EFI application. This
1079 is only useful on systems that have UEFI firmware.
1082 bool "Enable support for SMBIOS (DMI) tables"
1086 This enables SMBIOS/DMI feature for systems.
1088 This option is only useful on systems that have UEFI firmware.
1089 However, even with this option, the resultant kernel should
1090 continue to boot on existing non-UEFI platforms.
1094 menu "Userspace binary formats"
1096 source "fs/Kconfig.binfmt"
1099 bool "Kernel support for 32-bit EL0"
1100 depends on ARM64_4K_PAGES || EXPERT
1101 select COMPAT_BINFMT_ELF if BINFMT_ELF
1103 select OLD_SIGSUSPEND3
1104 select COMPAT_OLD_SIGACTION
1106 This option enables support for a 32-bit EL0 running under a 64-bit
1107 kernel at EL1. AArch32-specific components such as system calls,
1108 the user helper functions, VFP support and the ptrace interface are
1109 handled appropriately by the kernel.
1111 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1112 that you will only be able to execute AArch32 binaries that were compiled
1113 with page size aligned segments.
1115 If you want to execute 32-bit userspace applications, say Y.
1117 config SYSVIPC_COMPAT
1119 depends on COMPAT && SYSVIPC
1123 menu "Power management options"
1125 source "kernel/power/Kconfig"
1127 config ARCH_HIBERNATION_POSSIBLE
1131 config ARCH_HIBERNATION_HEADER
1133 depends on HIBERNATION
1135 config ARCH_SUSPEND_POSSIBLE
1140 menu "CPU Power Management"
1142 source "drivers/cpuidle/Kconfig"
1144 source "drivers/cpufreq/Kconfig"
1148 source "net/Kconfig"
1150 source "drivers/Kconfig"
1152 source "drivers/firmware/Kconfig"
1154 source "drivers/acpi/Kconfig"
1158 source "arch/arm64/kvm/Kconfig"
1160 source "arch/arm64/Kconfig.debug"
1162 source "security/Kconfig"
1164 source "crypto/Kconfig"
1166 source "arch/arm64/crypto/Kconfig"
1169 source "lib/Kconfig"