3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if (ACPI && PCI)
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_MEMORY
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
34 select ARCH_HAVE_NMI_SAFE_CMPXCHG
35 select ARCH_INLINE_READ_LOCK if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
38 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
46 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
50 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
52 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
56 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
60 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
61 select ARCH_USE_CMPXCHG_LOCKREF
62 select ARCH_USE_QUEUED_RWLOCKS
63 select ARCH_USE_QUEUED_SPINLOCKS
64 select ARCH_SUPPORTS_MEMORY_FAILURE
65 select ARCH_SUPPORTS_ATOMIC_RMW
66 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
67 select ARCH_SUPPORTS_NUMA_BALANCING
68 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
69 select ARCH_WANT_FRAME_POINTERS
70 select ARCH_HAS_UBSAN_SANITIZE_ALL
74 select AUDIT_ARCH_COMPAT_GENERIC
75 select ARM_GIC_V2M if PCI
77 select ARM_GIC_V3_ITS if PCI
79 select BUILDTIME_EXTABLE_SORT
80 select CLONE_BACKWARDS
82 select CPU_PM if (SUSPEND || CPU_IDLE)
84 select DCACHE_WORD_ACCESS
85 select DMA_DIRECT_REMAP
88 select GENERIC_ALLOCATOR
89 select GENERIC_ARCH_TOPOLOGY
90 select GENERIC_CLOCKEVENTS
91 select GENERIC_CLOCKEVENTS_BROADCAST
92 select GENERIC_CPU_AUTOPROBE
93 select GENERIC_CPU_VULNERABILITIES
94 select GENERIC_EARLY_IOREMAP
95 select GENERIC_IDLE_POLL_SETUP
96 select GENERIC_IRQ_MULTI_HANDLER
97 select GENERIC_IRQ_PROBE
98 select GENERIC_IRQ_SHOW
99 select GENERIC_IRQ_SHOW_LEVEL
100 select GENERIC_PCI_IOMAP
101 select GENERIC_SCHED_CLOCK
102 select GENERIC_SMP_IDLE_THREAD
103 select GENERIC_STRNCPY_FROM_USER
104 select GENERIC_STRNLEN_USER
105 select GENERIC_TIME_VSYSCALL
106 select HANDLE_DOMAIN_IRQ
107 select HARDIRQS_SW_RESEND
109 select HAVE_ACPI_APEI if (ACPI && EFI)
110 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
111 select HAVE_ARCH_AUDITSYSCALL
112 select HAVE_ARCH_BITREVERSE
113 select HAVE_ARCH_HUGE_VMAP
114 select HAVE_ARCH_JUMP_LABEL
115 select HAVE_ARCH_JUMP_LABEL_RELATIVE
116 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
117 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
118 select HAVE_ARCH_KGDB
119 select HAVE_ARCH_MMAP_RND_BITS
120 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
121 select HAVE_ARCH_PREL32_RELOCATIONS
122 select HAVE_ARCH_SECCOMP_FILTER
123 select HAVE_ARCH_STACKLEAK
124 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
125 select HAVE_ARCH_TRACEHOOK
126 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
127 select HAVE_ARCH_VMAP_STACK
128 select HAVE_ARM_SMCCC
130 select HAVE_C_RECORDMCOUNT
131 select HAVE_CMPXCHG_DOUBLE
132 select HAVE_CMPXCHG_LOCAL
133 select HAVE_CONTEXT_TRACKING
134 select HAVE_DEBUG_BUGVERBOSE
135 select HAVE_DEBUG_KMEMLEAK
136 select HAVE_DMA_CONTIGUOUS
137 select HAVE_DYNAMIC_FTRACE
138 select HAVE_EFFICIENT_UNALIGNED_ACCESS
139 select HAVE_FTRACE_MCOUNT_RECORD
140 select HAVE_FUNCTION_TRACER
141 select HAVE_FUNCTION_GRAPH_TRACER
142 select HAVE_GCC_PLUGINS
143 select HAVE_HW_BREAKPOINT if PERF_EVENTS
144 select HAVE_IRQ_TIME_ACCOUNTING
145 select HAVE_MEMBLOCK_NODE_MAP if NUMA
147 select HAVE_PATA_PLATFORM
148 select HAVE_PERF_EVENTS
149 select HAVE_PERF_REGS
150 select HAVE_PERF_USER_STACK_DUMP
151 select HAVE_REGS_AND_STACK_ACCESS_API
152 select HAVE_FUNCTION_ARG_ACCESS_API
153 select HAVE_RCU_TABLE_FREE
155 select HAVE_STACKPROTECTOR
156 select HAVE_SYSCALL_TRACEPOINTS
158 select HAVE_KRETPROBES
159 select IOMMU_DMA if IOMMU_SUPPORT
161 select IRQ_FORCED_THREADING
162 select MODULES_USE_ELF_RELA
163 select NEED_DMA_MAP_STATE
164 select NEED_SG_DMA_LENGTH
166 select OF_EARLY_FLATTREE
167 select PCI_DOMAINS_GENERIC if PCI
168 select PCI_ECAM if (ACPI && PCI)
169 select PCI_SYSCALL if PCI
175 select SYSCTL_EXCEPTION_TRACE
176 select THREAD_INFO_IN_TASK
178 ARM 64-bit (AArch64) Linux support.
186 config ARM64_PAGE_SHIFT
188 default 16 if ARM64_64K_PAGES
189 default 14 if ARM64_16K_PAGES
192 config ARM64_CONT_SHIFT
194 default 5 if ARM64_64K_PAGES
195 default 7 if ARM64_16K_PAGES
198 config ARCH_MMAP_RND_BITS_MIN
199 default 14 if ARM64_64K_PAGES
200 default 16 if ARM64_16K_PAGES
203 # max bits determined by the following formula:
204 # VA_BITS - PAGE_SHIFT - 3
205 config ARCH_MMAP_RND_BITS_MAX
206 default 19 if ARM64_VA_BITS=36
207 default 24 if ARM64_VA_BITS=39
208 default 27 if ARM64_VA_BITS=42
209 default 30 if ARM64_VA_BITS=47
210 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
211 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
212 default 33 if ARM64_VA_BITS=48
213 default 14 if ARM64_64K_PAGES
214 default 16 if ARM64_16K_PAGES
217 config ARCH_MMAP_RND_COMPAT_BITS_MIN
218 default 7 if ARM64_64K_PAGES
219 default 9 if ARM64_16K_PAGES
222 config ARCH_MMAP_RND_COMPAT_BITS_MAX
228 config STACKTRACE_SUPPORT
231 config ILLEGAL_POINTER_VALUE
233 default 0xdead000000000000
235 config LOCKDEP_SUPPORT
238 config TRACE_IRQFLAGS_SUPPORT
245 config GENERIC_BUG_RELATIVE_POINTERS
247 depends on GENERIC_BUG
249 config GENERIC_HWEIGHT
255 config GENERIC_CALIBRATE_DELAY
261 config HAVE_GENERIC_GUP
264 config ARCH_ENABLE_MEMORY_HOTPLUG
270 config KERNEL_MODE_NEON
273 config FIX_EARLYCON_MEM
276 config PGTABLE_LEVELS
278 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
279 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
280 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52)
281 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
282 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
283 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
285 config ARCH_SUPPORTS_UPROBES
288 config ARCH_PROC_KCORE_TEXT
291 source "arch/arm64/Kconfig.platforms"
293 menu "Kernel Features"
295 menu "ARM errata workarounds via the alternatives framework"
297 config ARM64_WORKAROUND_CLEAN_CACHE
300 config ARM64_ERRATUM_826319
301 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
303 select ARM64_WORKAROUND_CLEAN_CACHE
305 This option adds an alternative code sequence to work around ARM
306 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
307 AXI master interface and an L2 cache.
309 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
310 and is unable to accept a certain write via this interface, it will
311 not progress on read data presented on the read data channel and the
314 The workaround promotes data cache clean instructions to
315 data cache clean-and-invalidate.
316 Please note that this does not necessarily enable the workaround,
317 as it depends on the alternative framework, which will only patch
318 the kernel if an affected CPU is detected.
322 config ARM64_ERRATUM_827319
323 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
325 select ARM64_WORKAROUND_CLEAN_CACHE
327 This option adds an alternative code sequence to work around ARM
328 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
329 master interface and an L2 cache.
331 Under certain conditions this erratum can cause a clean line eviction
332 to occur at the same time as another transaction to the same address
333 on the AMBA 5 CHI interface, which can cause data corruption if the
334 interconnect reorders the two transactions.
336 The workaround promotes data cache clean instructions to
337 data cache clean-and-invalidate.
338 Please note that this does not necessarily enable the workaround,
339 as it depends on the alternative framework, which will only patch
340 the kernel if an affected CPU is detected.
344 config ARM64_ERRATUM_824069
345 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
347 select ARM64_WORKAROUND_CLEAN_CACHE
349 This option adds an alternative code sequence to work around ARM
350 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
351 to a coherent interconnect.
353 If a Cortex-A53 processor is executing a store or prefetch for
354 write instruction at the same time as a processor in another
355 cluster is executing a cache maintenance operation to the same
356 address, then this erratum might cause a clean cache line to be
357 incorrectly marked as dirty.
359 The workaround promotes data cache clean instructions to
360 data cache clean-and-invalidate.
361 Please note that this option does not necessarily enable the
362 workaround, as it depends on the alternative framework, which will
363 only patch the kernel if an affected CPU is detected.
367 config ARM64_ERRATUM_819472
368 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
370 select ARM64_WORKAROUND_CLEAN_CACHE
372 This option adds an alternative code sequence to work around ARM
373 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
374 present when it is connected to a coherent interconnect.
376 If the processor is executing a load and store exclusive sequence at
377 the same time as a processor in another cluster is executing a cache
378 maintenance operation to the same address, then this erratum might
379 cause data corruption.
381 The workaround promotes data cache clean instructions to
382 data cache clean-and-invalidate.
383 Please note that this does not necessarily enable the workaround,
384 as it depends on the alternative framework, which will only patch
385 the kernel if an affected CPU is detected.
389 config ARM64_ERRATUM_832075
390 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
393 This option adds an alternative code sequence to work around ARM
394 erratum 832075 on Cortex-A57 parts up to r1p2.
396 Affected Cortex-A57 parts might deadlock when exclusive load/store
397 instructions to Write-Back memory are mixed with Device loads.
399 The workaround is to promote device loads to use Load-Acquire
401 Please note that this does not necessarily enable the workaround,
402 as it depends on the alternative framework, which will only patch
403 the kernel if an affected CPU is detected.
407 config ARM64_ERRATUM_834220
408 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
412 This option adds an alternative code sequence to work around ARM
413 erratum 834220 on Cortex-A57 parts up to r1p2.
415 Affected Cortex-A57 parts might report a Stage 2 translation
416 fault as the result of a Stage 1 fault for load crossing a
417 page boundary when there is a permission or device memory
418 alignment fault at Stage 1 and a translation fault at Stage 2.
420 The workaround is to verify that the Stage 1 translation
421 doesn't generate a fault before handling the Stage 2 fault.
422 Please note that this does not necessarily enable the workaround,
423 as it depends on the alternative framework, which will only patch
424 the kernel if an affected CPU is detected.
428 config ARM64_ERRATUM_845719
429 bool "Cortex-A53: 845719: a load might read incorrect data"
433 This option adds an alternative code sequence to work around ARM
434 erratum 845719 on Cortex-A53 parts up to r0p4.
436 When running a compat (AArch32) userspace on an affected Cortex-A53
437 part, a load at EL0 from a virtual address that matches the bottom 32
438 bits of the virtual address used by a recent load at (AArch64) EL1
439 might return incorrect data.
441 The workaround is to write the contextidr_el1 register on exception
442 return to a 32-bit task.
443 Please note that this does not necessarily enable the workaround,
444 as it depends on the alternative framework, which will only patch
445 the kernel if an affected CPU is detected.
449 config ARM64_ERRATUM_843419
450 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
452 select ARM64_MODULE_PLTS if MODULES
454 This option links the kernel with '--fix-cortex-a53-843419' and
455 enables PLT support to replace certain ADRP instructions, which can
456 cause subsequent memory accesses to use an incorrect address on
457 Cortex-A53 parts up to r0p4.
461 config ARM64_ERRATUM_1024718
462 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
465 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
467 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
468 update of the hardware dirty bit when the DBM/AP bits are updated
469 without a break-before-make. The workaround is to disable the usage
470 of hardware DBM locally on the affected cores. CPUs not affected by
471 this erratum will continue to use the feature.
475 config ARM64_ERRATUM_1188873
476 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
479 select ARM_ARCH_TIMER_OOL_WORKAROUND
481 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
484 Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
485 cause register corruption when accessing the timer registers
486 from AArch32 userspace.
490 config ARM64_ERRATUM_1165522
491 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
494 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
496 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
497 corrupted TLBs by speculating an AT instruction during a guest
502 config ARM64_ERRATUM_1286807
503 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
505 select ARM64_WORKAROUND_REPEAT_TLBI
507 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
509 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
510 address for a cacheable mapping of a location is being
511 accessed by a core while another core is remapping the virtual
512 address to a new physical page using the recommended
513 break-before-make sequence, then under very rare circumstances
514 TLBI+DSB completes before a read using the translation being
515 invalidated has been observed by other observers. The
516 workaround repeats the TLBI+DSB operation.
520 config CAVIUM_ERRATUM_22375
521 bool "Cavium erratum 22375, 24313"
524 Enable workaround for errata 22375 and 24313.
526 This implements two gicv3-its errata workarounds for ThunderX. Both
527 with a small impact affecting only ITS table allocation.
529 erratum 22375: only alloc 8MB table size
530 erratum 24313: ignore memory access type
532 The fixes are in ITS initialization and basically ignore memory access
533 type and table size provided by the TYPER and BASER registers.
537 config CAVIUM_ERRATUM_23144
538 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
542 ITS SYNC command hang for cross node io and collections/cpu mapping.
546 config CAVIUM_ERRATUM_23154
547 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
550 The gicv3 of ThunderX requires a modified version for
551 reading the IAR status to ensure data synchronization
552 (access to icc_iar1_el1 is not sync'ed before and after).
556 config CAVIUM_ERRATUM_27456
557 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
560 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
561 instructions may cause the icache to become corrupted if it
562 contains data for a non-current ASID. The fix is to
563 invalidate the icache when changing the mm context.
567 config CAVIUM_ERRATUM_30115
568 bool "Cavium erratum 30115: Guest may disable interrupts in host"
571 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
572 1.2, and T83 Pass 1.0, KVM guest execution may disable
573 interrupts in host. Trapping both GICv3 group-0 and group-1
574 accesses sidesteps the issue.
578 config QCOM_FALKOR_ERRATUM_1003
579 bool "Falkor E1003: Incorrect translation due to ASID change"
582 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
583 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
584 in TTBR1_EL1, this situation only occurs in the entry trampoline and
585 then only for entries in the walk cache, since the leaf translation
586 is unchanged. Work around the erratum by invalidating the walk cache
587 entries for the trampoline before entering the kernel proper.
589 config ARM64_WORKAROUND_REPEAT_TLBI
592 config QCOM_FALKOR_ERRATUM_1009
593 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
595 select ARM64_WORKAROUND_REPEAT_TLBI
597 On Falkor v1, the CPU may prematurely complete a DSB following a
598 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
599 one more time to fix the issue.
603 config QCOM_QDF2400_ERRATUM_0065
604 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
607 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
608 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
609 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
613 config SOCIONEXT_SYNQUACER_PREITS
614 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
617 Socionext Synquacer SoCs implement a separate h/w block to generate
618 MSI doorbell writes with non-zero values for the device ID.
622 config HISILICON_ERRATUM_161600802
623 bool "Hip07 161600802: Erroneous redistributor VLPI base"
626 The HiSilicon Hip07 SoC uses the wrong redistributor base
627 when issued ITS commands such as VMOVP and VMAPP, and requires
628 a 128kB offset to be applied to the target address in this commands.
632 config QCOM_FALKOR_ERRATUM_E1041
633 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
636 Falkor CPU may speculatively fetch instructions from an improper
637 memory location when MMU translation is changed from SCTLR_ELn[M]=1
638 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
642 config FUJITSU_ERRATUM_010001
643 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
646 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
647 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
648 accesses may cause undefined fault (Data abort, DFSC=0b111111).
649 This fault occurs under a specific hardware condition when a
650 load/store instruction performs an address translation using:
651 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
652 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
653 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
654 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
656 The workaround is to ensure these bits are clear in TCR_ELx.
657 The workaround only affects the Fujitsu-A64FX.
666 default ARM64_4K_PAGES
668 Page size (translation granule) configuration.
670 config ARM64_4K_PAGES
673 This feature enables 4KB pages support.
675 config ARM64_16K_PAGES
678 The system will use 16KB pages support. AArch32 emulation
679 requires applications compiled with 16K (or a multiple of 16K)
682 config ARM64_64K_PAGES
685 This feature enables 64KB pages support (4KB by default)
686 allowing only two levels of page tables and faster TLB
687 look-up. AArch32 emulation requires applications compiled
688 with 64K aligned segments.
693 prompt "Virtual address space size"
694 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
695 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
696 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
698 Allows choosing one of multiple possible virtual address
699 space sizes. The level of translation table is determined by
700 a combination of page size and virtual address space size.
702 config ARM64_VA_BITS_36
703 bool "36-bit" if EXPERT
704 depends on ARM64_16K_PAGES
706 config ARM64_VA_BITS_39
708 depends on ARM64_4K_PAGES
710 config ARM64_VA_BITS_42
712 depends on ARM64_64K_PAGES
714 config ARM64_VA_BITS_47
716 depends on ARM64_16K_PAGES
718 config ARM64_VA_BITS_48
721 config ARM64_USER_VA_BITS_52
723 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
725 Enable 52-bit virtual addressing for userspace when explicitly
726 requested via a hint to mmap(). The kernel will continue to
727 use 48-bit virtual addresses for its own mappings.
729 NOTE: Enabling 52-bit virtual addressing in conjunction with
730 ARMv8.3 Pointer Authentication will result in the PAC being
731 reduced from 7 bits to 3 bits, which may have a significant
732 impact on its susceptibility to brute-force attacks.
734 If unsure, select 48-bit virtual addressing instead.
738 config ARM64_FORCE_52BIT
739 bool "Force 52-bit virtual addresses for userspace"
740 depends on ARM64_USER_VA_BITS_52 && EXPERT
742 For systems with 52-bit userspace VAs enabled, the kernel will attempt
743 to maintain compatibility with older software by providing 48-bit VAs
744 unless a hint is supplied to mmap.
746 This configuration option disables the 48-bit compatibility logic, and
747 forces all userspace addresses to be 52-bit on HW that supports it. One
748 should only enable this configuration option for stress testing userspace
749 memory management code. If unsure say N here.
753 default 36 if ARM64_VA_BITS_36
754 default 39 if ARM64_VA_BITS_39
755 default 42 if ARM64_VA_BITS_42
756 default 47 if ARM64_VA_BITS_47
757 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52
760 prompt "Physical address space size"
761 default ARM64_PA_BITS_48
763 Choose the maximum physical address range that the kernel will
766 config ARM64_PA_BITS_48
769 config ARM64_PA_BITS_52
770 bool "52-bit (ARMv8.2)"
771 depends on ARM64_64K_PAGES
772 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
774 Enable support for a 52-bit physical address space, introduced as
775 part of the ARMv8.2-LPA extension.
777 With this enabled, the kernel will also continue to work on CPUs that
778 do not support ARMv8.2-LPA, but with some added memory overhead (and
779 minor performance overhead).
785 default 48 if ARM64_PA_BITS_48
786 default 52 if ARM64_PA_BITS_52
788 config CPU_BIG_ENDIAN
789 bool "Build big-endian kernel"
791 Say Y if you plan on running a kernel in big-endian mode.
794 bool "Multi-core scheduler support"
796 Multi-core scheduler support improves the CPU scheduler's decision
797 making when dealing with multi-core CPU chips at a cost of slightly
798 increased overhead in some places. If unsure say N here.
801 bool "SMT scheduler support"
803 Improves the CPU scheduler's decision making when dealing with
804 MultiThreading at a cost of slightly increased overhead in some
805 places. If unsure say N here.
808 int "Maximum number of CPUs (2-4096)"
813 bool "Support for hot-pluggable CPUs"
814 select GENERIC_IRQ_MIGRATION
816 Say Y here to experiment with turning CPUs off and on. CPUs
817 can be controlled through /sys/devices/system/cpu.
819 # Common NUMA Features
821 bool "Numa Memory Allocation and Scheduler Support"
822 select ACPI_NUMA if ACPI
825 Enable NUMA (Non Uniform Memory Access) support.
827 The kernel will try to allocate memory used by a CPU on the
828 local memory of the CPU and add some more
829 NUMA awareness to the kernel.
832 int "Maximum NUMA Nodes (as a power of 2)"
835 depends on NEED_MULTIPLE_NODES
837 Specify the maximum number of NUMA Nodes available on the target
838 system. Increases memory reserved to accommodate various tables.
840 config USE_PERCPU_NUMA_NODE_ID
844 config HAVE_SETUP_PER_CPU_AREA
848 config NEED_PER_CPU_EMBED_FIRST_CHUNK
855 source "kernel/Kconfig.hz"
857 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
860 config ARCH_SPARSEMEM_ENABLE
862 select SPARSEMEM_VMEMMAP_ENABLE
864 config ARCH_SPARSEMEM_DEFAULT
865 def_bool ARCH_SPARSEMEM_ENABLE
867 config ARCH_SELECT_MEMORY_MODEL
868 def_bool ARCH_SPARSEMEM_ENABLE
870 config ARCH_FLATMEM_ENABLE
873 config HAVE_ARCH_PFN_VALID
876 config HW_PERF_EVENTS
880 config SYS_SUPPORTS_HUGETLBFS
883 config ARCH_WANT_HUGE_PMD_SHARE
884 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
886 config ARCH_HAS_CACHE_LINE_SIZE
889 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
890 def_bool y if PGTABLE_LEVELS > 2
893 bool "Enable seccomp to safely compute untrusted bytecode"
895 This kernel feature is useful for number crunching applications
896 that may need to compute untrusted bytecode during their
897 execution. By using pipes or other transports made available to
898 the process as file descriptors supporting the read/write
899 syscalls, it's possible to isolate those applications in
900 their own address space using seccomp. Once seccomp is
901 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
902 and the task is only allowed to execute a few safe syscalls
903 defined by each seccomp mode.
906 bool "Enable paravirtualization code"
908 This changes the kernel so it can modify itself when it is run
909 under a hypervisor, potentially improving performance significantly
910 over full virtualization.
912 config PARAVIRT_TIME_ACCOUNTING
913 bool "Paravirtual steal time accounting"
917 Select this option to enable fine granularity task steal time
918 accounting. Time spent executing other tasks in parallel with
919 the current vCPU is discounted from the vCPU power. To account for
920 that, there can be a small performance impact.
922 If in doubt, say N here.
925 depends on PM_SLEEP_SMP
927 bool "kexec system call"
929 kexec is a system call that implements the ability to shutdown your
930 current kernel, and to start another kernel. It is like a reboot
931 but it is independent of the system firmware. And like a reboot
932 you can start any kernel with it, not just Linux.
935 bool "kexec file based system call"
938 This is new version of kexec system call. This system call is
939 file based and takes file descriptors as system call argument
940 for kernel and initramfs as opposed to list of segments as
941 accepted by previous system call.
943 config KEXEC_VERIFY_SIG
944 bool "Verify kernel signature during kexec_file_load() syscall"
945 depends on KEXEC_FILE
947 Select this option to verify a signature with loaded kernel
948 image. If configured, any attempt of loading a image without
949 valid signature will fail.
951 In addition to that option, you need to enable signature
952 verification for the corresponding kernel image type being
953 loaded in order for this to work.
955 config KEXEC_IMAGE_VERIFY_SIG
956 bool "Enable Image signature verification support"
958 depends on KEXEC_VERIFY_SIG
959 depends on EFI && SIGNED_PE_FILE_VERIFICATION
961 Enable Image signature verification support.
963 comment "Support for PE file signature verification disabled"
964 depends on KEXEC_VERIFY_SIG
965 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
968 bool "Build kdump crash kernel"
970 Generate crash dump after being started by kexec. This should
971 be normally only set in special crash dump kernels which are
972 loaded in the main kernel with kexec-tools into a specially
973 reserved region and then later executed after a crash by
976 For more details see Documentation/kdump/kdump.txt
983 bool "Xen guest support on ARM64"
984 depends on ARM64 && OF
988 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
990 config FORCE_MAX_ZONEORDER
992 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
993 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
996 The kernel memory allocator divides physically contiguous memory
997 blocks into "zones", where each zone is a power of two number of
998 pages. This option selects the largest power of two that the kernel
999 keeps in the memory allocator. If you need to allocate very large
1000 blocks of physically contiguous memory, then you may need to
1001 increase this value.
1003 This config option is actually maximum order plus one. For example,
1004 a value of 11 means that the largest free memory block is 2^10 pages.
1006 We make sure that we can allocate upto a HugePage size for each configuration.
1008 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1010 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1011 4M allocations matching the default size used by generic code.
1013 config UNMAP_KERNEL_AT_EL0
1014 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1017 Speculation attacks against some high-performance processors can
1018 be used to bypass MMU permission checks and leak kernel data to
1019 userspace. This can be defended against by unmapping the kernel
1020 when running in userspace, mapping it back in on exception entry
1021 via a trampoline page in the vector table.
1025 config HARDEN_BRANCH_PREDICTOR
1026 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1029 Speculation attacks against some high-performance processors rely on
1030 being able to manipulate the branch predictor for a victim context by
1031 executing aliasing branches in the attacker context. Such attacks
1032 can be partially mitigated against by clearing internal branch
1033 predictor state and limiting the prediction logic in some situations.
1035 This config option will take CPU-specific actions to harden the
1036 branch predictor against aliasing attacks and may rely on specific
1037 instruction sequences or control bits being set by the system
1042 config HARDEN_EL2_VECTORS
1043 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1046 Speculation attacks against some high-performance processors can
1047 be used to leak privileged information such as the vector base
1048 register, resulting in a potential defeat of the EL2 layout
1051 This config option will map the vectors to a fixed location,
1052 independent of the EL2 code mapping, so that revealing VBAR_EL2
1053 to an attacker does not give away any extra information. This
1054 only gets enabled on affected CPUs.
1059 bool "Speculative Store Bypass Disable" if EXPERT
1062 This enables mitigation of the bypassing of previous stores
1063 by speculative loads.
1067 config RODATA_FULL_DEFAULT_ENABLED
1068 bool "Apply r/o permissions of VM areas also to their linear aliases"
1071 Apply read-only attributes of VM areas to the linear alias of
1072 the backing pages as well. This prevents code or read-only data
1073 from being modified (inadvertently or intentionally) via another
1074 mapping of the same memory page. This additional enhancement can
1075 be turned off at runtime by passing rodata=[off|on] (and turned on
1076 with rodata=full if this option is set to 'n')
1078 This requires the linear region to be mapped down to pages,
1079 which may adversely affect performance in some cases.
1081 config ARM64_SW_TTBR0_PAN
1082 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1084 Enabling this option prevents the kernel from accessing
1085 user-space memory directly by pointing TTBR0_EL1 to a reserved
1086 zeroed area and reserved ASID. The user access routines
1087 restore the valid TTBR0_EL1 temporarily.
1090 bool "Kernel support for 32-bit EL0"
1091 depends on ARM64_4K_PAGES || EXPERT
1092 select COMPAT_BINFMT_ELF if BINFMT_ELF
1094 select OLD_SIGSUSPEND3
1095 select COMPAT_OLD_SIGACTION
1097 This option enables support for a 32-bit EL0 running under a 64-bit
1098 kernel at EL1. AArch32-specific components such as system calls,
1099 the user helper functions, VFP support and the ptrace interface are
1100 handled appropriately by the kernel.
1102 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1103 that you will only be able to execute AArch32 binaries that were compiled
1104 with page size aligned segments.
1106 If you want to execute 32-bit userspace applications, say Y.
1110 config KUSER_HELPERS
1111 bool "Enable kuser helpers page for 32 bit applications"
1114 Warning: disabling this option may break 32-bit user programs.
1116 Provide kuser helpers to compat tasks. The kernel provides
1117 helper code to userspace in read only form at a fixed location
1118 to allow userspace to be independent of the CPU type fitted to
1119 the system. This permits binaries to be run on ARMv4 through
1120 to ARMv8 without modification.
1122 See Documentation/arm/kernel_user_helpers.txt for details.
1124 However, the fixed address nature of these helpers can be used
1125 by ROP (return orientated programming) authors when creating
1128 If all of the binaries and libraries which run on your platform
1129 are built specifically for your platform, and make no use of
1130 these helpers, then you can turn this option off to hinder
1131 such exploits. However, in that case, if a binary or library
1132 relying on those helpers is run, it will not function correctly.
1134 Say N here only if you are absolutely certain that you do not
1135 need these helpers; otherwise, the safe option is to say Y.
1138 menuconfig ARMV8_DEPRECATED
1139 bool "Emulate deprecated/obsolete ARMv8 instructions"
1142 Legacy software support may require certain instructions
1143 that have been deprecated or obsoleted in the architecture.
1145 Enable this config to enable selective emulation of these
1152 config SWP_EMULATION
1153 bool "Emulate SWP/SWPB instructions"
1155 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1156 they are always undefined. Say Y here to enable software
1157 emulation of these instructions for userspace using LDXR/STXR.
1159 In some older versions of glibc [<=2.8] SWP is used during futex
1160 trylock() operations with the assumption that the code will not
1161 be preempted. This invalid assumption may be more likely to fail
1162 with SWP emulation enabled, leading to deadlock of the user
1165 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1166 on an external transaction monitoring block called a global
1167 monitor to maintain update atomicity. If your system does not
1168 implement a global monitor, this option can cause programs that
1169 perform SWP operations to uncached memory to deadlock.
1173 config CP15_BARRIER_EMULATION
1174 bool "Emulate CP15 Barrier instructions"
1176 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1177 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1178 strongly recommended to use the ISB, DSB, and DMB
1179 instructions instead.
1181 Say Y here to enable software emulation of these
1182 instructions for AArch32 userspace code. When this option is
1183 enabled, CP15 barrier usage is traced which can help
1184 identify software that needs updating.
1188 config SETEND_EMULATION
1189 bool "Emulate SETEND instruction"
1191 The SETEND instruction alters the data-endianness of the
1192 AArch32 EL0, and is deprecated in ARMv8.
1194 Say Y here to enable software emulation of the instruction
1195 for AArch32 userspace code.
1197 Note: All the cpus on the system must have mixed endian support at EL0
1198 for this feature to be enabled. If a new CPU - which doesn't support mixed
1199 endian - is hotplugged in after this feature has been enabled, there could
1200 be unexpected results in the applications.
1207 menu "ARMv8.1 architectural features"
1209 config ARM64_HW_AFDBM
1210 bool "Support for hardware updates of the Access and Dirty page flags"
1213 The ARMv8.1 architecture extensions introduce support for
1214 hardware updates of the access and dirty information in page
1215 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1216 capable processors, accesses to pages with PTE_AF cleared will
1217 set this bit instead of raising an access flag fault.
1218 Similarly, writes to read-only pages with the DBM bit set will
1219 clear the read-only bit (AP[2]) instead of raising a
1222 Kernels built with this configuration option enabled continue
1223 to work on pre-ARMv8.1 hardware and the performance impact is
1224 minimal. If unsure, say Y.
1227 bool "Enable support for Privileged Access Never (PAN)"
1230 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1231 prevents the kernel or hypervisor from accessing user-space (EL0)
1234 Choosing this option will cause any unprotected (not using
1235 copy_to_user et al) memory access to fail with a permission fault.
1237 The feature is detected at runtime, and will remain as a 'nop'
1238 instruction if the cpu does not implement the feature.
1240 config ARM64_LSE_ATOMICS
1241 bool "Atomic instructions"
1244 As part of the Large System Extensions, ARMv8.1 introduces new
1245 atomic instructions that are designed specifically to scale in
1248 Say Y here to make use of these instructions for the in-kernel
1249 atomic routines. This incurs a small overhead on CPUs that do
1250 not support these instructions and requires the kernel to be
1251 built with binutils >= 2.25 in order for the new instructions
1255 bool "Enable support for Virtualization Host Extensions (VHE)"
1258 Virtualization Host Extensions (VHE) allow the kernel to run
1259 directly at EL2 (instead of EL1) on processors that support
1260 it. This leads to better performance for KVM, as they reduce
1261 the cost of the world switch.
1263 Selecting this option allows the VHE feature to be detected
1264 at runtime, and does not affect processors that do not
1265 implement this feature.
1269 menu "ARMv8.2 architectural features"
1272 bool "Enable support for User Access Override (UAO)"
1275 User Access Override (UAO; part of the ARMv8.2 Extensions)
1276 causes the 'unprivileged' variant of the load/store instructions to
1277 be overridden to be privileged.
1279 This option changes get_user() and friends to use the 'unprivileged'
1280 variant of the load/store instructions. This ensures that user-space
1281 really did have access to the supplied memory. When addr_limit is
1282 set to kernel memory the UAO bit will be set, allowing privileged
1283 access to kernel memory.
1285 Choosing this option will cause copy_to_user() et al to use user-space
1288 The feature is detected at runtime, the kernel will use the
1289 regular load/store instructions if the cpu does not implement the
1293 bool "Enable support for persistent memory"
1294 select ARCH_HAS_PMEM_API
1295 select ARCH_HAS_UACCESS_FLUSHCACHE
1297 Say Y to enable support for the persistent memory API based on the
1298 ARMv8.2 DCPoP feature.
1300 The feature is detected at runtime, and the kernel will use DC CVAC
1301 operations if DC CVAP is not supported (following the behaviour of
1302 DC CVAP itself if the system does not define a point of persistence).
1304 config ARM64_RAS_EXTN
1305 bool "Enable support for RAS CPU Extensions"
1308 CPUs that support the Reliability, Availability and Serviceability
1309 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1310 errors, classify them and report them to software.
1312 On CPUs with these extensions system software can use additional
1313 barriers to determine if faults are pending and read the
1314 classification from a new set of registers.
1316 Selecting this feature will allow the kernel to use these barriers
1317 and access the new registers if the system supports the extension.
1318 Platform RAS features may additionally depend on firmware support.
1321 bool "Enable support for Common Not Private (CNP) translations"
1323 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1325 Common Not Private (CNP) allows translation table entries to
1326 be shared between different PEs in the same inner shareable
1327 domain, so the hardware can use this fact to optimise the
1328 caching of such entries in the TLB.
1330 Selecting this option allows the CNP feature to be detected
1331 at runtime, and does not affect PEs that do not implement
1336 menu "ARMv8.3 architectural features"
1338 config ARM64_PTR_AUTH
1339 bool "Enable support for pointer authentication"
1342 Pointer authentication (part of the ARMv8.3 Extensions) provides
1343 instructions for signing and authenticating pointers against secret
1344 keys, which can be used to mitigate Return Oriented Programming (ROP)
1347 This option enables these instructions at EL0 (i.e. for userspace).
1349 Choosing this option will cause the kernel to initialise secret keys
1350 for each process at exec() time, with these keys being
1351 context-switched along with the process.
1353 The feature is detected at runtime. If the feature is not present in
1354 hardware it will not be advertised to userspace nor will it be
1360 bool "ARM Scalable Vector Extension support"
1362 depends on !KVM || ARM64_VHE
1364 The Scalable Vector Extension (SVE) is an extension to the AArch64
1365 execution state which complements and extends the SIMD functionality
1366 of the base architecture to support much larger vectors and to enable
1367 additional vectorisation opportunities.
1369 To enable use of this extension on CPUs that implement it, say Y.
1371 On CPUs that support the SVE2 extensions, this option will enable
1374 Note that for architectural reasons, firmware _must_ implement SVE
1375 support when running on SVE capable hardware. The required support
1378 * version 1.5 and later of the ARM Trusted Firmware
1379 * the AArch64 boot wrapper since commit 5e1261e08abf
1380 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1382 For other firmware implementations, consult the firmware documentation
1385 If you need the kernel to boot on SVE-capable hardware with broken
1386 firmware, you may need to say N here until you get your firmware
1387 fixed. Otherwise, you may experience firmware panics or lockups when
1388 booting the kernel. If unsure and you are not observing these
1389 symptoms, you should assume that it is safe to say Y.
1391 CPUs that support SVE are architecturally required to support the
1392 Virtualization Host Extensions (VHE), so the kernel makes no
1393 provision for supporting SVE alongside KVM without VHE enabled.
1394 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1395 KVM in the same kernel image.
1397 config ARM64_MODULE_PLTS
1399 select HAVE_MOD_ARCH_SPECIFIC
1401 config ARM64_PSEUDO_NMI
1402 bool "Support for NMI-like interrupts"
1403 select CONFIG_ARM_GIC_V3
1405 Adds support for mimicking Non-Maskable Interrupts through the use of
1406 GIC interrupt priority. This support requires version 3 or later of
1409 This high priority configuration for interrupts needs to be
1410 explicitly enabled by setting the kernel parameter
1411 "irqchip.gicv3_pseudo_nmi" to 1.
1418 This builds the kernel as a Position Independent Executable (PIE),
1419 which retains all relocation metadata required to relocate the
1420 kernel binary at runtime to a different virtual address than the
1421 address it was linked at.
1422 Since AArch64 uses the RELA relocation format, this requires a
1423 relocation pass at runtime even if the kernel is loaded at the
1424 same address it was linked at.
1426 config RANDOMIZE_BASE
1427 bool "Randomize the address of the kernel image"
1428 select ARM64_MODULE_PLTS if MODULES
1431 Randomizes the virtual address at which the kernel image is
1432 loaded, as a security feature that deters exploit attempts
1433 relying on knowledge of the location of kernel internals.
1435 It is the bootloader's job to provide entropy, by passing a
1436 random u64 value in /chosen/kaslr-seed at kernel entry.
1438 When booting via the UEFI stub, it will invoke the firmware's
1439 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1440 to the kernel proper. In addition, it will randomise the physical
1441 location of the kernel Image as well.
1445 config RANDOMIZE_MODULE_REGION_FULL
1446 bool "Randomize the module region over a 4 GB range"
1447 depends on RANDOMIZE_BASE
1450 Randomizes the location of the module region inside a 4 GB window
1451 covering the core kernel. This way, it is less likely for modules
1452 to leak information about the location of core kernel data structures
1453 but it does imply that function calls between modules and the core
1454 kernel will need to be resolved via veneers in the module PLT.
1456 When this option is not set, the module region will be randomized over
1457 a limited range that contains the [_stext, _etext] interval of the
1458 core kernel, so branch relocations are always in range.
1460 config CC_HAVE_STACKPROTECTOR_SYSREG
1461 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1463 config STACKPROTECTOR_PER_TASK
1465 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1471 config ARM64_ACPI_PARKING_PROTOCOL
1472 bool "Enable support for the ARM64 ACPI parking protocol"
1475 Enable support for the ARM64 ACPI parking protocol. If disabled
1476 the kernel will not allow booting through the ARM64 ACPI parking
1477 protocol even if the corresponding data is present in the ACPI
1481 string "Default kernel command string"
1484 Provide a set of default command-line options at build time by
1485 entering them here. As a minimum, you should specify the the
1486 root device (e.g. root=/dev/nfs).
1488 config CMDLINE_FORCE
1489 bool "Always use the default kernel command string"
1491 Always use the default kernel command string, even if the boot
1492 loader passes other arguments to the kernel.
1493 This is useful if you cannot or don't want to change the
1494 command-line options your boot loader passes to the kernel.
1500 bool "UEFI runtime support"
1501 depends on OF && !CPU_BIG_ENDIAN
1502 depends on KERNEL_MODE_NEON
1503 select ARCH_SUPPORTS_ACPI
1506 select EFI_PARAMS_FROM_FDT
1507 select EFI_RUNTIME_WRAPPERS
1512 This option provides support for runtime services provided
1513 by UEFI firmware (such as non-volatile variables, realtime
1514 clock, and platform reset). A UEFI stub is also provided to
1515 allow the kernel to be booted as an EFI application. This
1516 is only useful on systems that have UEFI firmware.
1519 bool "Enable support for SMBIOS (DMI) tables"
1523 This enables SMBIOS/DMI feature for systems.
1525 This option is only useful on systems that have UEFI firmware.
1526 However, even with this option, the resultant kernel should
1527 continue to boot on existing non-UEFI platforms.
1531 config SYSVIPC_COMPAT
1533 depends on COMPAT && SYSVIPC
1535 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1537 depends on HUGETLB_PAGE && MIGRATION
1539 menu "Power management options"
1541 source "kernel/power/Kconfig"
1543 config ARCH_HIBERNATION_POSSIBLE
1547 config ARCH_HIBERNATION_HEADER
1549 depends on HIBERNATION
1551 config ARCH_SUSPEND_POSSIBLE
1556 menu "CPU Power Management"
1558 source "drivers/cpuidle/Kconfig"
1560 source "drivers/cpufreq/Kconfig"
1564 source "drivers/firmware/Kconfig"
1566 source "drivers/acpi/Kconfig"
1568 source "arch/arm64/kvm/Kconfig"
1571 source "arch/arm64/crypto/Kconfig"