3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ARCH_CLOCKSOURCE_DATA
11 select ARCH_HAS_DEBUG_VIRTUAL
12 select ARCH_HAS_DEVMEM_IS_ALLOWED
13 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
14 select ARCH_HAS_ELF_RANDOMIZE
15 select ARCH_HAS_FORTIFY_SOURCE
16 select ARCH_HAS_GCOV_PROFILE_ALL
17 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_SG_CHAIN
21 select ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_HAS_STRICT_MODULE_RWX
23 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
24 select ARCH_HAVE_NMI_SAFE_CMPXCHG
25 select ARCH_INLINE_READ_LOCK if !PREEMPT
26 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
27 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
28 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
29 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
30 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
31 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
32 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
33 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
34 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
35 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
36 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
37 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
38 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
39 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
40 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
41 select ARCH_USE_CMPXCHG_LOCKREF
42 select ARCH_USE_QUEUED_RWLOCKS
43 select ARCH_SUPPORTS_MEMORY_FAILURE
44 select ARCH_SUPPORTS_ATOMIC_RMW
45 select ARCH_SUPPORTS_NUMA_BALANCING
46 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
47 select ARCH_WANT_FRAME_POINTERS
48 select ARCH_HAS_UBSAN_SANITIZE_ALL
52 select AUDIT_ARCH_COMPAT_GENERIC
53 select ARM_GIC_V2M if PCI
55 select ARM_GIC_V3_ITS if PCI
57 select BUILDTIME_EXTABLE_SORT
58 select CLONE_BACKWARDS
60 select CPU_PM if (SUSPEND || CPU_IDLE)
61 select DCACHE_WORD_ACCESS
64 select GENERIC_ALLOCATOR
65 select GENERIC_ARCH_TOPOLOGY
66 select GENERIC_CLOCKEVENTS
67 select GENERIC_CLOCKEVENTS_BROADCAST
68 select GENERIC_CPU_AUTOPROBE
69 select GENERIC_EARLY_IOREMAP
70 select GENERIC_IDLE_POLL_SETUP
71 select GENERIC_IRQ_PROBE
72 select GENERIC_IRQ_SHOW
73 select GENERIC_IRQ_SHOW_LEVEL
74 select GENERIC_PCI_IOMAP
75 select GENERIC_SCHED_CLOCK
76 select GENERIC_SMP_IDLE_THREAD
77 select GENERIC_STRNCPY_FROM_USER
78 select GENERIC_STRNLEN_USER
79 select GENERIC_TIME_VSYSCALL
80 select HANDLE_DOMAIN_IRQ
81 select HARDIRQS_SW_RESEND
82 select HAVE_ACPI_APEI if (ACPI && EFI)
83 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
84 select HAVE_ARCH_AUDITSYSCALL
85 select HAVE_ARCH_BITREVERSE
86 select HAVE_ARCH_HUGE_VMAP
87 select HAVE_ARCH_JUMP_LABEL
88 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
90 select HAVE_ARCH_MMAP_RND_BITS
91 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
92 select HAVE_ARCH_SECCOMP_FILTER
93 select HAVE_ARCH_TRACEHOOK
94 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
95 select HAVE_ARCH_VMAP_STACK
98 select HAVE_C_RECORDMCOUNT
99 select HAVE_CC_STACKPROTECTOR
100 select HAVE_CMPXCHG_DOUBLE
101 select HAVE_CMPXCHG_LOCAL
102 select HAVE_CONTEXT_TRACKING
103 select HAVE_DEBUG_BUGVERBOSE
104 select HAVE_DEBUG_KMEMLEAK
105 select HAVE_DMA_API_DEBUG
106 select HAVE_DMA_CONTIGUOUS
107 select HAVE_DYNAMIC_FTRACE
108 select HAVE_EFFICIENT_UNALIGNED_ACCESS
109 select HAVE_FTRACE_MCOUNT_RECORD
110 select HAVE_FUNCTION_TRACER
111 select HAVE_FUNCTION_GRAPH_TRACER
112 select HAVE_GCC_PLUGINS
113 select HAVE_GENERIC_DMA_COHERENT
114 select HAVE_HW_BREAKPOINT if PERF_EVENTS
115 select HAVE_IRQ_TIME_ACCOUNTING
117 select HAVE_MEMBLOCK_NODE_MAP if NUMA
119 select HAVE_PATA_PLATFORM
120 select HAVE_PERF_EVENTS
121 select HAVE_PERF_REGS
122 select HAVE_PERF_USER_STACK_DUMP
123 select HAVE_REGS_AND_STACK_ACCESS_API
124 select HAVE_RCU_TABLE_FREE
125 select HAVE_SYSCALL_TRACEPOINTS
127 select HAVE_KRETPROBES
128 select IOMMU_DMA if IOMMU_SUPPORT
130 select IRQ_FORCED_THREADING
131 select MODULES_USE_ELF_RELA
134 select OF_EARLY_FLATTREE
135 select OF_RESERVED_MEM
136 select PCI_ECAM if ACPI
141 select SYSCTL_EXCEPTION_TRACE
142 select THREAD_INFO_IN_TASK
144 ARM 64-bit (AArch64) Linux support.
149 config ARCH_PHYS_ADDR_T_64BIT
155 config ARM64_PAGE_SHIFT
157 default 16 if ARM64_64K_PAGES
158 default 14 if ARM64_16K_PAGES
161 config ARM64_CONT_SHIFT
163 default 5 if ARM64_64K_PAGES
164 default 7 if ARM64_16K_PAGES
167 config ARCH_MMAP_RND_BITS_MIN
168 default 14 if ARM64_64K_PAGES
169 default 16 if ARM64_16K_PAGES
172 # max bits determined by the following formula:
173 # VA_BITS - PAGE_SHIFT - 3
174 config ARCH_MMAP_RND_BITS_MAX
175 default 19 if ARM64_VA_BITS=36
176 default 24 if ARM64_VA_BITS=39
177 default 27 if ARM64_VA_BITS=42
178 default 30 if ARM64_VA_BITS=47
179 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
180 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
181 default 33 if ARM64_VA_BITS=48
182 default 14 if ARM64_64K_PAGES
183 default 16 if ARM64_16K_PAGES
186 config ARCH_MMAP_RND_COMPAT_BITS_MIN
187 default 7 if ARM64_64K_PAGES
188 default 9 if ARM64_16K_PAGES
191 config ARCH_MMAP_RND_COMPAT_BITS_MAX
197 config STACKTRACE_SUPPORT
200 config ILLEGAL_POINTER_VALUE
202 default 0xdead000000000000
204 config LOCKDEP_SUPPORT
207 config TRACE_IRQFLAGS_SUPPORT
210 config RWSEM_XCHGADD_ALGORITHM
217 config GENERIC_BUG_RELATIVE_POINTERS
219 depends on GENERIC_BUG
221 config GENERIC_HWEIGHT
227 config GENERIC_CALIBRATE_DELAY
233 config HAVE_GENERIC_GUP
236 config ARCH_DMA_ADDR_T_64BIT
239 config NEED_DMA_MAP_STATE
242 config NEED_SG_DMA_LENGTH
254 config KERNEL_MODE_NEON
257 config FIX_EARLYCON_MEM
260 config PGTABLE_LEVELS
262 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
263 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
264 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
265 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
266 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
267 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
269 config ARCH_SUPPORTS_UPROBES
272 config ARCH_PROC_KCORE_TEXT
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
279 source "arch/arm64/Kconfig.platforms"
286 This feature enables support for PCI bus system. If you say Y
287 here, the kernel will include drivers and infrastructure code
288 to support PCI bus devices.
293 config PCI_DOMAINS_GENERIC
299 source "drivers/pci/Kconfig"
303 menu "Kernel Features"
305 menu "ARM errata workarounds via the alternatives framework"
307 config ARM64_ERRATUM_826319
308 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
311 This option adds an alternative code sequence to work around ARM
312 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
313 AXI master interface and an L2 cache.
315 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
316 and is unable to accept a certain write via this interface, it will
317 not progress on read data presented on the read data channel and the
320 The workaround promotes data cache clean instructions to
321 data cache clean-and-invalidate.
322 Please note that this does not necessarily enable the workaround,
323 as it depends on the alternative framework, which will only patch
324 the kernel if an affected CPU is detected.
328 config ARM64_ERRATUM_827319
329 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
332 This option adds an alternative code sequence to work around ARM
333 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
334 master interface and an L2 cache.
336 Under certain conditions this erratum can cause a clean line eviction
337 to occur at the same time as another transaction to the same address
338 on the AMBA 5 CHI interface, which can cause data corruption if the
339 interconnect reorders the two transactions.
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this does not necessarily enable the workaround,
344 as it depends on the alternative framework, which will only patch
345 the kernel if an affected CPU is detected.
349 config ARM64_ERRATUM_824069
350 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
353 This option adds an alternative code sequence to work around ARM
354 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
355 to a coherent interconnect.
357 If a Cortex-A53 processor is executing a store or prefetch for
358 write instruction at the same time as a processor in another
359 cluster is executing a cache maintenance operation to the same
360 address, then this erratum might cause a clean cache line to be
361 incorrectly marked as dirty.
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this option does not necessarily enable the
366 workaround, as it depends on the alternative framework, which will
367 only patch the kernel if an affected CPU is detected.
371 config ARM64_ERRATUM_819472
372 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
392 config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
402 The workaround is to promote device loads to use Load-Acquire
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
410 config ARM64_ERRATUM_834220
411 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
415 This option adds an alternative code sequence to work around ARM
416 erratum 834220 on Cortex-A57 parts up to r1p2.
418 Affected Cortex-A57 parts might report a Stage 2 translation
419 fault as the result of a Stage 1 fault for load crossing a
420 page boundary when there is a permission or device memory
421 alignment fault at Stage 1 and a translation fault at Stage 2.
423 The workaround is to verify that the Stage 1 translation
424 doesn't generate a fault before handling the Stage 2 fault.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
431 config ARM64_ERRATUM_845719
432 bool "Cortex-A53: 845719: a load might read incorrect data"
436 This option adds an alternative code sequence to work around ARM
437 erratum 845719 on Cortex-A53 parts up to r0p4.
439 When running a compat (AArch32) userspace on an affected Cortex-A53
440 part, a load at EL0 from a virtual address that matches the bottom 32
441 bits of the virtual address used by a recent load at (AArch64) EL1
442 might return incorrect data.
444 The workaround is to write the contextidr_el1 register on exception
445 return to a 32-bit task.
446 Please note that this does not necessarily enable the workaround,
447 as it depends on the alternative framework, which will only patch
448 the kernel if an affected CPU is detected.
452 config ARM64_ERRATUM_843419
453 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
455 select ARM64_MODULE_CMODEL_LARGE if MODULES
457 This option links the kernel with '--fix-cortex-a53-843419' and
458 builds modules using the large memory model in order to avoid the use
459 of the ADRP instruction, which can cause a subsequent memory access
460 to use an incorrect address on Cortex-A53 parts up to r0p4.
464 config CAVIUM_ERRATUM_22375
465 bool "Cavium erratum 22375, 24313"
468 Enable workaround for erratum 22375, 24313.
470 This implements two gicv3-its errata workarounds for ThunderX. Both
471 with small impact affecting only ITS table allocation.
473 erratum 22375: only alloc 8MB table size
474 erratum 24313: ignore memory access type
476 The fixes are in ITS initialization and basically ignore memory access
477 type and table size provided by the TYPER and BASER registers.
481 config CAVIUM_ERRATUM_23144
482 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
486 ITS SYNC command hang for cross node io and collections/cpu mapping.
490 config CAVIUM_ERRATUM_23154
491 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
494 The gicv3 of ThunderX requires a modified version for
495 reading the IAR status to ensure data synchronization
496 (access to icc_iar1_el1 is not sync'ed before and after).
500 config CAVIUM_ERRATUM_27456
501 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
504 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
505 instructions may cause the icache to become corrupted if it
506 contains data for a non-current ASID. The fix is to
507 invalidate the icache when changing the mm context.
511 config CAVIUM_ERRATUM_30115
512 bool "Cavium erratum 30115: Guest may disable interrupts in host"
515 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
516 1.2, and T83 Pass 1.0, KVM guest execution may disable
517 interrupts in host. Trapping both GICv3 group-0 and group-1
518 accesses sidesteps the issue.
522 config QCOM_FALKOR_ERRATUM_1003
523 bool "Falkor E1003: Incorrect translation due to ASID change"
525 select ARM64_PAN if ARM64_SW_TTBR0_PAN
527 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
528 and BADDR are changed together in TTBRx_EL1. The workaround for this
529 issue is to use a reserved ASID in cpu_do_switch_mm() before
530 switching to the new ASID. Saying Y here selects ARM64_PAN if
531 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and
532 maintaining the E1003 workaround in the software PAN emulation code
533 would be an unnecessary complication. The affected Falkor v1 CPU
534 implements ARMv8.1 hardware PAN support and using hardware PAN
535 support versus software PAN emulation is mutually exclusive at
540 config QCOM_FALKOR_ERRATUM_1009
541 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
544 On Falkor v1, the CPU may prematurely complete a DSB following a
545 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
546 one more time to fix the issue.
550 config QCOM_QDF2400_ERRATUM_0065
551 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
554 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
555 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
556 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
561 config SOCIONEXT_SYNQUACER_PREITS
562 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
565 Socionext Synquacer SoCs implement a separate h/w block to generate
566 MSI doorbell writes with non-zero values for the device ID.
570 config HISILICON_ERRATUM_161600802
571 bool "Hip07 161600802: Erroneous redistributor VLPI base"
574 The HiSilicon Hip07 SoC usees the wrong redistributor base
575 when issued ITS commands such as VMOVP and VMAPP, and requires
576 a 128kB offset to be applied to the target address in this commands.
584 default ARM64_4K_PAGES
586 Page size (translation granule) configuration.
588 config ARM64_4K_PAGES
591 This feature enables 4KB pages support.
593 config ARM64_16K_PAGES
596 The system will use 16KB pages support. AArch32 emulation
597 requires applications compiled with 16K (or a multiple of 16K)
600 config ARM64_64K_PAGES
603 This feature enables 64KB pages support (4KB by default)
604 allowing only two levels of page tables and faster TLB
605 look-up. AArch32 emulation requires applications compiled
606 with 64K aligned segments.
611 prompt "Virtual address space size"
612 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
613 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
614 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
616 Allows choosing one of multiple possible virtual address
617 space sizes. The level of translation table is determined by
618 a combination of page size and virtual address space size.
620 config ARM64_VA_BITS_36
621 bool "36-bit" if EXPERT
622 depends on ARM64_16K_PAGES
624 config ARM64_VA_BITS_39
626 depends on ARM64_4K_PAGES
628 config ARM64_VA_BITS_42
630 depends on ARM64_64K_PAGES
632 config ARM64_VA_BITS_47
634 depends on ARM64_16K_PAGES
636 config ARM64_VA_BITS_48
643 default 36 if ARM64_VA_BITS_36
644 default 39 if ARM64_VA_BITS_39
645 default 42 if ARM64_VA_BITS_42
646 default 47 if ARM64_VA_BITS_47
647 default 48 if ARM64_VA_BITS_48
649 config CPU_BIG_ENDIAN
650 bool "Build big-endian kernel"
652 Say Y if you plan on running a kernel in big-endian mode.
655 bool "Multi-core scheduler support"
657 Multi-core scheduler support improves the CPU scheduler's decision
658 making when dealing with multi-core CPU chips at a cost of slightly
659 increased overhead in some places. If unsure say N here.
662 bool "SMT scheduler support"
664 Improves the CPU scheduler's decision making when dealing with
665 MultiThreading at a cost of slightly increased overhead in some
666 places. If unsure say N here.
669 int "Maximum number of CPUs (2-4096)"
671 # These have to remain sorted largest to smallest
675 bool "Support for hot-pluggable CPUs"
676 select GENERIC_IRQ_MIGRATION
678 Say Y here to experiment with turning CPUs off and on. CPUs
679 can be controlled through /sys/devices/system/cpu.
681 # Common NUMA Features
683 bool "Numa Memory Allocation and Scheduler Support"
684 select ACPI_NUMA if ACPI
687 Enable NUMA (Non Uniform Memory Access) support.
689 The kernel will try to allocate memory used by a CPU on the
690 local memory of the CPU and add some more
691 NUMA awareness to the kernel.
694 int "Maximum NUMA Nodes (as a power of 2)"
697 depends on NEED_MULTIPLE_NODES
699 Specify the maximum number of NUMA Nodes available on the target
700 system. Increases memory reserved to accommodate various tables.
702 config USE_PERCPU_NUMA_NODE_ID
706 config HAVE_SETUP_PER_CPU_AREA
710 config NEED_PER_CPU_EMBED_FIRST_CHUNK
718 source kernel/Kconfig.preempt
719 source kernel/Kconfig.hz
721 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
724 config ARCH_HAS_HOLES_MEMORYMODEL
725 def_bool y if SPARSEMEM
727 config ARCH_SPARSEMEM_ENABLE
729 select SPARSEMEM_VMEMMAP_ENABLE
731 config ARCH_SPARSEMEM_DEFAULT
732 def_bool ARCH_SPARSEMEM_ENABLE
734 config ARCH_SELECT_MEMORY_MODEL
735 def_bool ARCH_SPARSEMEM_ENABLE
737 config HAVE_ARCH_PFN_VALID
738 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
740 config HW_PERF_EVENTS
744 config SYS_SUPPORTS_HUGETLBFS
747 config ARCH_WANT_HUGE_PMD_SHARE
748 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
750 config ARCH_HAS_CACHE_LINE_SIZE
756 bool "Enable seccomp to safely compute untrusted bytecode"
758 This kernel feature is useful for number crunching applications
759 that may need to compute untrusted bytecode during their
760 execution. By using pipes or other transports made available to
761 the process as file descriptors supporting the read/write
762 syscalls, it's possible to isolate those applications in
763 their own address space using seccomp. Once seccomp is
764 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
765 and the task is only allowed to execute a few safe syscalls
766 defined by each seccomp mode.
769 bool "Enable paravirtualization code"
771 This changes the kernel so it can modify itself when it is run
772 under a hypervisor, potentially improving performance significantly
773 over full virtualization.
775 config PARAVIRT_TIME_ACCOUNTING
776 bool "Paravirtual steal time accounting"
780 Select this option to enable fine granularity task steal time
781 accounting. Time spent executing other tasks in parallel with
782 the current vCPU is discounted from the vCPU power. To account for
783 that, there can be a small performance impact.
785 If in doubt, say N here.
788 depends on PM_SLEEP_SMP
790 bool "kexec system call"
792 kexec is a system call that implements the ability to shutdown your
793 current kernel, and to start another kernel. It is like a reboot
794 but it is independent of the system firmware. And like a reboot
795 you can start any kernel with it, not just Linux.
798 bool "Build kdump crash kernel"
800 Generate crash dump after being started by kexec. This should
801 be normally only set in special crash dump kernels which are
802 loaded in the main kernel with kexec-tools into a specially
803 reserved region and then later executed after a crash by
806 For more details see Documentation/kdump/kdump.txt
813 bool "Xen guest support on ARM64"
814 depends on ARM64 && OF
818 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
820 config FORCE_MAX_ZONEORDER
822 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
823 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
826 The kernel memory allocator divides physically contiguous memory
827 blocks into "zones", where each zone is a power of two number of
828 pages. This option selects the largest power of two that the kernel
829 keeps in the memory allocator. If you need to allocate very large
830 blocks of physically contiguous memory, then you may need to
833 This config option is actually maximum order plus one. For example,
834 a value of 11 means that the largest free memory block is 2^10 pages.
836 We make sure that we can allocate upto a HugePage size for each configuration.
838 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
840 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
841 4M allocations matching the default size used by generic code.
843 menuconfig ARMV8_DEPRECATED
844 bool "Emulate deprecated/obsolete ARMv8 instructions"
848 Legacy software support may require certain instructions
849 that have been deprecated or obsoleted in the architecture.
851 Enable this config to enable selective emulation of these
859 bool "Emulate SWP/SWPB instructions"
861 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
862 they are always undefined. Say Y here to enable software
863 emulation of these instructions for userspace using LDXR/STXR.
865 In some older versions of glibc [<=2.8] SWP is used during futex
866 trylock() operations with the assumption that the code will not
867 be preempted. This invalid assumption may be more likely to fail
868 with SWP emulation enabled, leading to deadlock of the user
871 NOTE: when accessing uncached shared regions, LDXR/STXR rely
872 on an external transaction monitoring block called a global
873 monitor to maintain update atomicity. If your system does not
874 implement a global monitor, this option can cause programs that
875 perform SWP operations to uncached memory to deadlock.
879 config CP15_BARRIER_EMULATION
880 bool "Emulate CP15 Barrier instructions"
882 The CP15 barrier instructions - CP15ISB, CP15DSB, and
883 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
884 strongly recommended to use the ISB, DSB, and DMB
885 instructions instead.
887 Say Y here to enable software emulation of these
888 instructions for AArch32 userspace code. When this option is
889 enabled, CP15 barrier usage is traced which can help
890 identify software that needs updating.
894 config SETEND_EMULATION
895 bool "Emulate SETEND instruction"
897 The SETEND instruction alters the data-endianness of the
898 AArch32 EL0, and is deprecated in ARMv8.
900 Say Y here to enable software emulation of the instruction
901 for AArch32 userspace code.
903 Note: All the cpus on the system must have mixed endian support at EL0
904 for this feature to be enabled. If a new CPU - which doesn't support mixed
905 endian - is hotplugged in after this feature has been enabled, there could
906 be unexpected results in the applications.
911 config ARM64_SW_TTBR0_PAN
912 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
914 Enabling this option prevents the kernel from accessing
915 user-space memory directly by pointing TTBR0_EL1 to a reserved
916 zeroed area and reserved ASID. The user access routines
917 restore the valid TTBR0_EL1 temporarily.
919 menu "ARMv8.1 architectural features"
921 config ARM64_HW_AFDBM
922 bool "Support for hardware updates of the Access and Dirty page flags"
925 The ARMv8.1 architecture extensions introduce support for
926 hardware updates of the access and dirty information in page
927 table entries. When enabled in TCR_EL1 (HA and HD bits) on
928 capable processors, accesses to pages with PTE_AF cleared will
929 set this bit instead of raising an access flag fault.
930 Similarly, writes to read-only pages with the DBM bit set will
931 clear the read-only bit (AP[2]) instead of raising a
934 Kernels built with this configuration option enabled continue
935 to work on pre-ARMv8.1 hardware and the performance impact is
936 minimal. If unsure, say Y.
939 bool "Enable support for Privileged Access Never (PAN)"
942 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
943 prevents the kernel or hypervisor from accessing user-space (EL0)
946 Choosing this option will cause any unprotected (not using
947 copy_to_user et al) memory access to fail with a permission fault.
949 The feature is detected at runtime, and will remain as a 'nop'
950 instruction if the cpu does not implement the feature.
952 config ARM64_LSE_ATOMICS
953 bool "Atomic instructions"
955 As part of the Large System Extensions, ARMv8.1 introduces new
956 atomic instructions that are designed specifically to scale in
959 Say Y here to make use of these instructions for the in-kernel
960 atomic routines. This incurs a small overhead on CPUs that do
961 not support these instructions and requires the kernel to be
962 built with binutils >= 2.25.
965 bool "Enable support for Virtualization Host Extensions (VHE)"
968 Virtualization Host Extensions (VHE) allow the kernel to run
969 directly at EL2 (instead of EL1) on processors that support
970 it. This leads to better performance for KVM, as they reduce
971 the cost of the world switch.
973 Selecting this option allows the VHE feature to be detected
974 at runtime, and does not affect processors that do not
975 implement this feature.
979 menu "ARMv8.2 architectural features"
982 bool "Enable support for User Access Override (UAO)"
985 User Access Override (UAO; part of the ARMv8.2 Extensions)
986 causes the 'unprivileged' variant of the load/store instructions to
987 be overridden to be privileged.
989 This option changes get_user() and friends to use the 'unprivileged'
990 variant of the load/store instructions. This ensures that user-space
991 really did have access to the supplied memory. When addr_limit is
992 set to kernel memory the UAO bit will be set, allowing privileged
993 access to kernel memory.
995 Choosing this option will cause copy_to_user() et al to use user-space
998 The feature is detected at runtime, the kernel will use the
999 regular load/store instructions if the cpu does not implement the
1003 bool "Enable support for persistent memory"
1004 select ARCH_HAS_PMEM_API
1005 select ARCH_HAS_UACCESS_FLUSHCACHE
1007 Say Y to enable support for the persistent memory API based on the
1008 ARMv8.2 DCPoP feature.
1010 The feature is detected at runtime, and the kernel will use DC CVAC
1011 operations if DC CVAP is not supported (following the behaviour of
1012 DC CVAP itself if the system does not define a point of persistence).
1017 bool "ARM Scalable Vector Extension support"
1020 The Scalable Vector Extension (SVE) is an extension to the AArch64
1021 execution state which complements and extends the SIMD functionality
1022 of the base architecture to support much larger vectors and to enable
1023 additional vectorisation opportunities.
1025 To enable use of this extension on CPUs that implement it, say Y.
1027 config ARM64_MODULE_CMODEL_LARGE
1030 config ARM64_MODULE_PLTS
1032 select ARM64_MODULE_CMODEL_LARGE
1033 select HAVE_MOD_ARCH_SPECIFIC
1038 This builds the kernel as a Position Independent Executable (PIE),
1039 which retains all relocation metadata required to relocate the
1040 kernel binary at runtime to a different virtual address than the
1041 address it was linked at.
1042 Since AArch64 uses the RELA relocation format, this requires a
1043 relocation pass at runtime even if the kernel is loaded at the
1044 same address it was linked at.
1046 config RANDOMIZE_BASE
1047 bool "Randomize the address of the kernel image"
1048 select ARM64_MODULE_PLTS if MODULES
1051 Randomizes the virtual address at which the kernel image is
1052 loaded, as a security feature that deters exploit attempts
1053 relying on knowledge of the location of kernel internals.
1055 It is the bootloader's job to provide entropy, by passing a
1056 random u64 value in /chosen/kaslr-seed at kernel entry.
1058 When booting via the UEFI stub, it will invoke the firmware's
1059 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1060 to the kernel proper. In addition, it will randomise the physical
1061 location of the kernel Image as well.
1065 config RANDOMIZE_MODULE_REGION_FULL
1066 bool "Randomize the module region independently from the core kernel"
1067 depends on RANDOMIZE_BASE
1070 Randomizes the location of the module region without considering the
1071 location of the core kernel. This way, it is impossible for modules
1072 to leak information about the location of core kernel data structures
1073 but it does imply that function calls between modules and the core
1074 kernel will need to be resolved via veneers in the module PLT.
1076 When this option is not set, the module region will be randomized over
1077 a limited range that contains the [_stext, _etext] interval of the
1078 core kernel, so branch relocations are always in range.
1084 config ARM64_ACPI_PARKING_PROTOCOL
1085 bool "Enable support for the ARM64 ACPI parking protocol"
1088 Enable support for the ARM64 ACPI parking protocol. If disabled
1089 the kernel will not allow booting through the ARM64 ACPI parking
1090 protocol even if the corresponding data is present in the ACPI
1094 string "Default kernel command string"
1097 Provide a set of default command-line options at build time by
1098 entering them here. As a minimum, you should specify the the
1099 root device (e.g. root=/dev/nfs).
1101 config CMDLINE_FORCE
1102 bool "Always use the default kernel command string"
1104 Always use the default kernel command string, even if the boot
1105 loader passes other arguments to the kernel.
1106 This is useful if you cannot or don't want to change the
1107 command-line options your boot loader passes to the kernel.
1113 bool "UEFI runtime support"
1114 depends on OF && !CPU_BIG_ENDIAN
1115 depends on KERNEL_MODE_NEON
1118 select EFI_PARAMS_FROM_FDT
1119 select EFI_RUNTIME_WRAPPERS
1124 This option provides support for runtime services provided
1125 by UEFI firmware (such as non-volatile variables, realtime
1126 clock, and platform reset). A UEFI stub is also provided to
1127 allow the kernel to be booted as an EFI application. This
1128 is only useful on systems that have UEFI firmware.
1131 bool "Enable support for SMBIOS (DMI) tables"
1135 This enables SMBIOS/DMI feature for systems.
1137 This option is only useful on systems that have UEFI firmware.
1138 However, even with this option, the resultant kernel should
1139 continue to boot on existing non-UEFI platforms.
1143 menu "Userspace binary formats"
1145 source "fs/Kconfig.binfmt"
1148 bool "Kernel support for 32-bit EL0"
1149 depends on ARM64_4K_PAGES || EXPERT
1150 select COMPAT_BINFMT_ELF if BINFMT_ELF
1152 select OLD_SIGSUSPEND3
1153 select COMPAT_OLD_SIGACTION
1155 This option enables support for a 32-bit EL0 running under a 64-bit
1156 kernel at EL1. AArch32-specific components such as system calls,
1157 the user helper functions, VFP support and the ptrace interface are
1158 handled appropriately by the kernel.
1160 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1161 that you will only be able to execute AArch32 binaries that were compiled
1162 with page size aligned segments.
1164 If you want to execute 32-bit userspace applications, say Y.
1166 config SYSVIPC_COMPAT
1168 depends on COMPAT && SYSVIPC
1172 menu "Power management options"
1174 source "kernel/power/Kconfig"
1176 config ARCH_HIBERNATION_POSSIBLE
1180 config ARCH_HIBERNATION_HEADER
1182 depends on HIBERNATION
1184 config ARCH_SUSPEND_POSSIBLE
1189 menu "CPU Power Management"
1191 source "drivers/cpuidle/Kconfig"
1193 source "drivers/cpufreq/Kconfig"
1197 source "net/Kconfig"
1199 source "drivers/Kconfig"
1201 source "drivers/firmware/Kconfig"
1203 source "drivers/acpi/Kconfig"
1207 source "arch/arm64/kvm/Kconfig"
1209 source "arch/arm64/Kconfig.debug"
1211 source "security/Kconfig"
1213 source "crypto/Kconfig"
1215 source "arch/arm64/crypto/Kconfig"
1218 source "lib/Kconfig"