1 /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
6 * S5PC1XX clock register definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __PLAT_REGS_CLOCK_H
14 #define __PLAT_REGS_CLOCK_H __FILE__
16 #define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
17 #define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
19 /* s5pc100 register for clock */
20 #define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
21 #define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
22 #define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
23 #define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
25 #define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
26 #define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
27 #define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
28 #define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
30 #define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
31 #define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
32 #define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
33 #define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
35 #define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
36 #define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
37 #define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
38 #define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
39 #define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
41 #define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
43 #define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
44 #define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
45 #define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
47 #define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
48 #define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
49 #define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
50 #define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
51 #define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
52 #define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
54 #define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
56 #define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
57 #define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
60 #define S5PC100_EPLL_EN (1<<31)
61 #define S5PC100_EPLL_MASK 0xffffffff
62 #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
65 #define S5PC100_CLKSRC0_APLL_MASK (0x1<<0)
66 #define S5PC100_CLKSRC0_APLL_SHIFT (0)
67 #define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
68 #define S5PC100_CLKSRC0_MPLL_SHIFT (4)
69 #define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
70 #define S5PC100_CLKSRC0_EPLL_SHIFT (8)
71 #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
72 #define S5PC100_CLKSRC0_HPLL_SHIFT (12)
73 #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
74 #define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
75 #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
76 #define S5PC100_CLKSRC0_HREF_SHIFT (20)
77 #define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
78 #define S5PC100_CLKSRC0_ONENAND_SHIFT (24)
82 #define S5PC100_CLKSRC1_UART_MASK (0x1<<0)
83 #define S5PC100_CLKSRC1_UART_SHIFT (0)
84 #define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4)
85 #define S5PC100_CLKSRC1_SPI0_SHIFT (4)
86 #define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8)
87 #define S5PC100_CLKSRC1_SPI1_SHIFT (8)
88 #define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12)
89 #define S5PC100_CLKSRC1_SPI2_SHIFT (12)
90 #define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16)
91 #define S5PC100_CLKSRC1_IRDA_SHIFT (16)
92 #define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20)
93 #define S5PC100_CLKSRC1_UHOST_SHIFT (20)
94 #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
95 #define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
98 #define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0)
99 #define S5PC100_CLKSRC2_MMC0_SHIFT (0)
100 #define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4)
101 #define S5PC100_CLKSRC2_MMC1_SHIFT (4)
102 #define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8)
103 #define S5PC100_CLKSRC2_MMC2_SHIFT (8)
104 #define S5PC100_CLKSRC2_LCD_MASK (0x3<<12)
105 #define S5PC100_CLKSRC2_LCD_SHIFT (12)
106 #define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16)
107 #define S5PC100_CLKSRC2_FIMC0_SHIFT (16)
108 #define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20)
109 #define S5PC100_CLKSRC2_FIMC1_SHIFT (20)
110 #define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24)
111 #define S5PC100_CLKSRC2_FIMC2_SHIFT (24)
112 #define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28)
113 #define S5PC100_CLKSRC2_MIXER_SHIFT (28)
116 #define S5PC100_CLKSRC3_PWI_MASK (0x3<<0)
117 #define S5PC100_CLKSRC3_PWI_SHIFT (0)
118 #define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4)
119 #define S5PC100_CLKSRC3_HCLKD2_SHIFT (4)
120 #define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8)
121 #define S5PC100_CLKSRC3_I2SD2_SHIFT (8)
122 #define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12)
123 #define S5PC100_CLKSRC3_AUDIO0_SHIFT (12)
124 #define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16)
125 #define S5PC100_CLKSRC3_AUDIO1_SHIFT (16)
126 #define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20)
127 #define S5PC100_CLKSRC3_AUDIO2_SHIFT (20)
128 #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
129 #define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
132 #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
133 #define S5PC100_CLKDIV0_APLL_SHIFT (0)
134 #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
135 #define S5PC100_CLKDIV0_ARM_SHIFT (4)
136 #define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
137 #define S5PC100_CLKDIV0_D0_SHIFT (8)
138 #define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
139 #define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
140 #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
141 #define S5PC100_CLKDIV0_SECSS_SHIFT (16)
144 #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
145 #define S5PC100_CLKDIV1_APLL2_SHIFT (0)
146 #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
147 #define S5PC100_CLKDIV1_MPLL_SHIFT (4)
148 #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
149 #define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
150 #define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
151 #define S5PC100_CLKDIV1_D1_SHIFT (12)
152 #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
153 #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
154 #define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20)
155 #define S5PC100_CLKDIV1_ONENAND_SHIFT (20)
156 #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
157 #define S5PC100_CLKDIV1_CAM_SHIFT (24)
160 #define S5PC100_CLKDIV2_UART_MASK (0x7<<0)
161 #define S5PC100_CLKDIV2_UART_SHIFT (0)
162 #define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4)
163 #define S5PC100_CLKDIV2_SPI0_SHIFT (4)
164 #define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8)
165 #define S5PC100_CLKDIV2_SPI1_SHIFT (8)
166 #define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12)
167 #define S5PC100_CLKDIV2_SPI2_SHIFT (12)
168 #define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16)
169 #define S5PC100_CLKDIV2_IRDA_SHIFT (16)
170 #define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20)
171 #define S5PC100_CLKDIV2_UHOST_SHIFT (20)
174 #define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0)
175 #define S5PC100_CLKDIV3_MMC0_SHIFT (0)
176 #define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4)
177 #define S5PC100_CLKDIV3_MMC1_SHIFT (4)
178 #define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8)
179 #define S5PC100_CLKDIV3_MMC2_SHIFT (8)
180 #define S5PC100_CLKDIV3_LCD_MASK (0xf<<12)
181 #define S5PC100_CLKDIV3_LCD_SHIFT (12)
182 #define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16)
183 #define S5PC100_CLKDIV3_FIMC0_SHIFT (16)
184 #define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20)
185 #define S5PC100_CLKDIV3_FIMC1_SHIFT (20)
186 #define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24)
187 #define S5PC100_CLKDIV3_FIMC2_SHIFT (24)
188 #define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28)
189 #define S5PC100_CLKDIV3_HDMI_SHIFT (28)
192 #define S5PC100_CLKDIV4_PWI_MASK (0x7<<0)
193 #define S5PC100_CLKDIV4_PWI_SHIFT (0)
194 #define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4)
195 #define S5PC100_CLKDIV4_HCLKD2_SHIFT (4)
196 #define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8)
197 #define S5PC100_CLKDIV4_I2SD2_SHIFT (8)
198 #define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12)
199 #define S5PC100_CLKDIV4_AUDIO0_SHIFT (12)
200 #define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16)
201 #define S5PC100_CLKDIV4_AUDIO1_SHIFT (16)
202 #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
203 #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
205 /* HCLKD0/PCLKD0 Clock Gate 0 Registers */
206 #define S5PC100_CLKGATE_D00_INTC (1<<0)
207 #define S5PC100_CLKGATE_D00_TZIC (1<<1)
208 #define S5PC100_CLKGATE_D00_CFCON (1<<2)
209 #define S5PC100_CLKGATE_D00_MDMA (1<<3)
210 #define S5PC100_CLKGATE_D00_G2D (1<<4)
211 #define S5PC100_CLKGATE_D00_SECSS (1<<5)
212 #define S5PC100_CLKGATE_D00_CSSYS (1<<6)
214 /* HCLKD0/PCLKD0 Clock Gate 1 Registers */
215 #define S5PC100_CLKGATE_D01_DMC (1<<0)
216 #define S5PC100_CLKGATE_D01_SROMC (1<<1)
217 #define S5PC100_CLKGATE_D01_ONENAND (1<<2)
218 #define S5PC100_CLKGATE_D01_NFCON (1<<3)
219 #define S5PC100_CLKGATE_D01_INTMEM (1<<4)
220 #define S5PC100_CLKGATE_D01_EBI (1<<5)
222 /* PCLKD0 Clock Gate 2 Registers */
223 #define S5PC100_CLKGATE_D02_SECKEY (1<<1)
224 #define S5PC100_CLKGATE_D02_SDM (1<<2)
226 /* HCLKD1/PCLKD1 Clock Gate 0 Registers */
227 #define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
228 #define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
229 #define S5PC100_CLKGATE_D10_USBHOST (1<<2)
230 #define S5PC100_CLKGATE_D10_USBOTG (1<<3)
231 #define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
232 #define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
233 #define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
234 #define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
236 /* HCLKD1/PCLKD1 Clock Gate 1 Registers */
237 #define S5PC100_CLKGATE_D11_LCD (1<<0)
238 #define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
239 #define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
240 #define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
241 #define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
242 #define S5PC100_CLKGATE_D11_JPEG (1<<5)
243 #define S5PC100_CLKGATE_D11_DSI (1<<6)
244 #define S5PC100_CLKGATE_D11_CSI (1<<7)
245 #define S5PC100_CLKGATE_D11_G3D (1<<8)
247 /* HCLKD1/PCLKD1 Clock Gate 2 Registers */
248 #define S5PC100_CLKGATE_D12_TV (1<<0)
249 #define S5PC100_CLKGATE_D12_VP (1<<1)
250 #define S5PC100_CLKGATE_D12_MIXER (1<<2)
251 #define S5PC100_CLKGATE_D12_HDMI (1<<3)
252 #define S5PC100_CLKGATE_D12_MFC (1<<4)
254 /* HCLKD1/PCLKD1 Clock Gate 3 Registers */
255 #define S5PC100_CLKGATE_D13_CHIPID (1<<0)
256 #define S5PC100_CLKGATE_D13_GPIO (1<<1)
257 #define S5PC100_CLKGATE_D13_APC (1<<2)
258 #define S5PC100_CLKGATE_D13_IEC (1<<3)
259 #define S5PC100_CLKGATE_D13_PWM (1<<6)
260 #define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
261 #define S5PC100_CLKGATE_D13_WDT (1<<8)
262 #define S5PC100_CLKGATE_D13_RTC (1<<9)
264 /* HCLKD1/PCLKD1 Clock Gate 4 Registers */
265 #define S5PC100_CLKGATE_D14_UART0 (1<<0)
266 #define S5PC100_CLKGATE_D14_UART1 (1<<1)
267 #define S5PC100_CLKGATE_D14_UART2 (1<<2)
268 #define S5PC100_CLKGATE_D14_UART3 (1<<3)
269 #define S5PC100_CLKGATE_D14_IIC (1<<4)
270 #define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
271 #define S5PC100_CLKGATE_D14_SPI0 (1<<6)
272 #define S5PC100_CLKGATE_D14_SPI1 (1<<7)
273 #define S5PC100_CLKGATE_D14_SPI2 (1<<8)
274 #define S5PC100_CLKGATE_D14_IRDA (1<<9)
275 #define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
276 #define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
277 #define S5PC100_CLKGATE_D14_HSITX (1<<12)
278 #define S5PC100_CLKGATE_D14_HSIRX (1<<13)
280 /* HCLKD1/PCLKD1 Clock Gate 5 Registers */
281 #define S5PC100_CLKGATE_D15_IIS0 (1<<0)
282 #define S5PC100_CLKGATE_D15_IIS1 (1<<1)
283 #define S5PC100_CLKGATE_D15_IIS2 (1<<2)
284 #define S5PC100_CLKGATE_D15_AC97 (1<<3)
285 #define S5PC100_CLKGATE_D15_PCM0 (1<<4)
286 #define S5PC100_CLKGATE_D15_PCM1 (1<<5)
287 #define S5PC100_CLKGATE_D15_SPDIF (1<<6)
288 #define S5PC100_CLKGATE_D15_TSADC (1<<7)
289 #define S5PC100_CLKGATE_D15_KEYIF (1<<8)
290 #define S5PC100_CLKGATE_D15_CG (1<<9)
292 /* HCLKD2 Clock Gate 0 Registers */
293 #define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
294 #define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
296 /* Special Clock Gate 0 Registers */
297 #define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
298 #define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
299 #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
300 #define S5PC100_CLKGATE_SCLK0_UART (1<<3)
301 #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
302 #define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
303 #define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
304 #define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
305 #define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
306 #define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
307 #define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
308 #define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
309 #define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
310 #define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
311 #define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
312 #define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
313 #define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
314 #define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
316 /* Special Clock Gate 1 Registers */
317 #define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
318 #define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
319 #define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
320 #define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
321 #define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
322 #define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
323 #define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
324 #define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
325 #define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
326 #define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
327 #define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
328 #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
329 #define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
331 #define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
332 #define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
333 #define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
334 #define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
335 #define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
336 #define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
337 #define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
338 #define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
339 #define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
340 #define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
341 #define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
343 #define S5PC100_SWRESET_RESETVAL 0xc100
344 #define S5PC100_OTHER_SYS_INT 24
345 #define S5PC100_OTHER_STA_TYPE 23
346 #define STA_TYPE_EXPON 0
347 #define STA_TYPE_SFR 1
349 #define S5PC100_SLEEP_CFG_OSC_EN 0
351 /* OTHERS Resgister */
352 #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
353 #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
355 /* MIPI D-PHY Control Register 0 */
356 #define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
357 #define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
359 #endif /* _PLAT_REGS_CLOCK_H */