arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/dma.h>
  28 #include <plat/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285
 286 /*
 287  * omap_mcbsp_get_dma_op_mode just return the current configured
 288  * operating mode for the mcbsp channel
 289  */
 290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 291 {
 292         struct omap_mcbsp *mcbsp;
 293         int dma_op_mode;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         dma_op_mode = mcbsp->dma_op_mode;
 302
 303         return dma_op_mode;
 304 }
 305 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 306
 307 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 308 {
 309         /*
 310          * Enable wakup behavior, smart idle and all wakeups
 311          * REVISIT: some wakeups may be unnecessary
 312          */
 313         if (cpu_is_omap34xx()) {
 314                 u16 syscon;
 315
 316                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 317                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 318
 319                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 320                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 321                                         CLOCKACTIVITY(0x02));
 322                         OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
 323                                         XRDYEN | RRDYEN);
 324                 } else {
 325                         syscon |= SIDLEMODE(0x01);
 326                 }
 327
 328                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 329         }
 330 }
 331
 332 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 333 {
 334         /*
 335          * Disable wakup behavior, smart idle and all wakeups
 336          */
 337         if (cpu_is_omap34xx()) {
 338                 u16 syscon;
 339
 340                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 341                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 342                 /*
 343                  * HW bug workaround - If no_idle mode is taken, we need to
 344                  * go to smart_idle before going to always_idle, or the
 345                  * device will not hit retention anymore.
 346                  */
 347                 syscon |= SIDLEMODE(0x02);
 348                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 349
 350                 syscon &= ~(SIDLEMODE(0x03));
 351                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 352
 353                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
 354         }
 355 }
 356 #else
 357 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 358 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 359 #endif
 360
 361 /*
 362  * We can choose between IRQ based or polled IO.
 363  * This needs to be called before omap_mcbsp_request().
 364  */
 365 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 366 {
 367         struct omap_mcbsp *mcbsp;
 368
 369         if (!omap_mcbsp_check_valid_id(id)) {
 370                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 371                 return -ENODEV;
 372         }
 373         mcbsp = id_to_mcbsp_ptr(id);
 374
 375         spin_lock(&mcbsp->lock);
 376
 377         if (!mcbsp->free) {
 378                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 379                         mcbsp->id);
 380                 spin_unlock(&mcbsp->lock);
 381                 return -EINVAL;
 382         }
 383
 384         mcbsp->io_type = io_type;
 385
 386         spin_unlock(&mcbsp->lock);
 387
 388         return 0;
 389 }
 390 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 391
 392 int omap_mcbsp_request(unsigned int id)
 393 {
 394         struct omap_mcbsp *mcbsp;
 395         int err;
 396
 397         if (!omap_mcbsp_check_valid_id(id)) {
 398                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 399                 return -ENODEV;
 400         }
 401         mcbsp = id_to_mcbsp_ptr(id);
 402
 403         spin_lock(&mcbsp->lock);
 404         if (!mcbsp->free) {
 405                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 406                         mcbsp->id);
 407                 spin_unlock(&mcbsp->lock);
 408                 return -EBUSY;
 409         }
 410
 411         mcbsp->free = 0;
 412         spin_unlock(&mcbsp->lock);
 413
 414         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 415                 mcbsp->pdata->ops->request(id);
 416
 417         clk_enable(mcbsp->iclk);
 418         clk_enable(mcbsp->fclk);
 419
 420         /* Do procedure specific to omap34xx arch, if applicable */
 421         omap34xx_mcbsp_request(mcbsp);
 422
 423         /*
 424          * Make sure that transmitter, receiver and sample-rate generator are
 425          * not running before activating IRQs.
 426          */
 427         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 428         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 429
 430         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 431                 /* We need to get IRQs here */
 432                 init_completion(&mcbsp->tx_irq_completion);
 433                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 434                                         0, "McBSP", (void *)mcbsp);
 435                 if (err != 0) {
 436                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 437                                         "for McBSP%d\n", mcbsp->tx_irq,
 438                                         mcbsp->id);
 439                         return err;
 440                 }
 441
 442                 init_completion(&mcbsp->rx_irq_completion);
 443                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 444                                         0, "McBSP", (void *)mcbsp);
 445                 if (err != 0) {
 446                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 447                                         "for McBSP%d\n", mcbsp->rx_irq,
 448                                         mcbsp->id);
 449                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 450                         return err;
 451                 }
 452         }
 453
 454         return 0;
 455 }
 456 EXPORT_SYMBOL(omap_mcbsp_request);
 457
 458 void omap_mcbsp_free(unsigned int id)
 459 {
 460         struct omap_mcbsp *mcbsp;
 461
 462         if (!omap_mcbsp_check_valid_id(id)) {
 463                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 464                 return;
 465         }
 466         mcbsp = id_to_mcbsp_ptr(id);
 467
 468         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 469                 mcbsp->pdata->ops->free(id);
 470
 471         /* Do procedure specific to omap34xx arch, if applicable */
 472         omap34xx_mcbsp_free(mcbsp);
 473
 474         clk_disable(mcbsp->fclk);
 475         clk_disable(mcbsp->iclk);
 476
 477         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 478                 /* Free IRQs */
 479                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 480                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 481         }
 482
 483         spin_lock(&mcbsp->lock);
 484         if (mcbsp->free) {
 485                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 486                         mcbsp->id);
 487                 spin_unlock(&mcbsp->lock);
 488                 return;
 489         }
 490
 491         mcbsp->free = 1;
 492         spin_unlock(&mcbsp->lock);
 493 }
 494 EXPORT_SYMBOL(omap_mcbsp_free);
 495
 496 /*
 497  * Here we start the McBSP, by enabling transmitter, receiver or both.
 498  * If no transmitter or receiver is active prior calling, then sample-rate
 499  * generator and frame sync are started.
 500  */
 501 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 502 {
 503         struct omap_mcbsp *mcbsp;
 504         void __iomem *io_base;
 505         int idle;
 506         u16 w;
 507
 508         if (!omap_mcbsp_check_valid_id(id)) {
 509                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 510                 return;
 511         }
 512         mcbsp = id_to_mcbsp_ptr(id);
 513         io_base = mcbsp->io_base;
 514
 515         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 516         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 517
 518         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 519                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 520
 521         if (idle) {
 522                 /* Start the sample generator */
 523                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 524                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 525         }
 526
 527         /* Enable transmitter and receiver */
 528         tx &= 1;
 529         w = OMAP_MCBSP_READ(io_base, SPCR2);
 530         OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
 531
 532         rx &= 1;
 533         w = OMAP_MCBSP_READ(io_base, SPCR1);
 534         OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
 535
 536         /*
 537          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 538          * REVISIT: 100us may give enough time for two CLKSRG, however
 539          * due to some unknown PM related, clock gating etc. reason it
 540          * is now at 500us.
 541          */
 542         udelay(500);
 543
 544         if (idle) {
 545                 /* Start frame sync */
 546                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 547                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 548         }
 549
 550         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 551                 /* Release the transmitter and receiver */
 552                 w = OMAP_MCBSP_READ(io_base, XCCR);
 553                 w &= ~(tx ? XDISABLE : 0);
 554                 OMAP_MCBSP_WRITE(io_base, XCCR, w);
 555                 w = OMAP_MCBSP_READ(io_base, RCCR);
 556                 w &= ~(rx ? RDISABLE : 0);
 557                 OMAP_MCBSP_WRITE(io_base, RCCR, w);
 558         }
 559
 560         /* Dump McBSP Regs */
 561         omap_mcbsp_dump_reg(id);
 562 }
 563 EXPORT_SYMBOL(omap_mcbsp_start);
 564
 565 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 566 {
 567         struct omap_mcbsp *mcbsp;
 568         void __iomem *io_base;
 569         int idle;
 570         u16 w;
 571
 572         if (!omap_mcbsp_check_valid_id(id)) {
 573                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 574                 return;
 575         }
 576
 577         mcbsp = id_to_mcbsp_ptr(id);
 578         io_base = mcbsp->io_base;
 579
 580         /* Reset transmitter */
 581         tx &= 1;
 582         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 583                 w = OMAP_MCBSP_READ(io_base, XCCR);
 584                 w |= (tx ? XDISABLE : 0);
 585                 OMAP_MCBSP_WRITE(io_base, XCCR, w);
 586         }
 587         w = OMAP_MCBSP_READ(io_base, SPCR2);
 588         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
 589
 590         /* Reset receiver */
 591         rx &= 1;
 592         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 593                 w = OMAP_MCBSP_READ(io_base, RCCR);
 594                 w |= (rx ? RDISABLE : 0);
 595                 OMAP_MCBSP_WRITE(io_base, RCCR, w);
 596         }
 597         w = OMAP_MCBSP_READ(io_base, SPCR1);
 598         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
 599
 600         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 601                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 602
 603         if (idle) {
 604                 /* Reset the sample rate generator */
 605                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 606                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 607         }
 608 }
 609 EXPORT_SYMBOL(omap_mcbsp_stop);
 610
 611 /* polled mcbsp i/o operations */
 612 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 613 {
 614         struct omap_mcbsp *mcbsp;
 615         void __iomem *base;
 616
 617         if (!omap_mcbsp_check_valid_id(id)) {
 618                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 619                 return -ENODEV;
 620         }
 621
 622         mcbsp = id_to_mcbsp_ptr(id);
 623         base = mcbsp->io_base;
 624
 625         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 626         /* if frame sync error - clear the error */
 627         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 628                 /* clear error */
 629                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 630                        base + OMAP_MCBSP_REG_SPCR2);
 631                 /* resend */
 632                 return -1;
 633         } else {
 634                 /* wait for transmit confirmation */
 635                 int attemps = 0;
 636                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 637                         if (attemps++ > 1000) {
 638                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 639                                        (~XRST),
 640                                        base + OMAP_MCBSP_REG_SPCR2);
 641                                 udelay(10);
 642                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 643                                        (XRST),
 644                                        base + OMAP_MCBSP_REG_SPCR2);
 645                                 udelay(10);
 646                                 dev_err(mcbsp->dev, "Could not write to"
 647                                         " McBSP%d Register\n", mcbsp->id);
 648                                 return -2;
 649                         }
 650                 }
 651         }
 652
 653         return 0;
 654 }
 655 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 656
 657 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 658 {
 659         struct omap_mcbsp *mcbsp;
 660         void __iomem *base;
 661
 662         if (!omap_mcbsp_check_valid_id(id)) {
 663                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 664                 return -ENODEV;
 665         }
 666         mcbsp = id_to_mcbsp_ptr(id);
 667
 668         base = mcbsp->io_base;
 669         /* if frame sync error - clear the error */
 670         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 671                 /* clear error */
 672                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 673                        base + OMAP_MCBSP_REG_SPCR1);
 674                 /* resend */
 675                 return -1;
 676         } else {
 677                 /* wait for recieve confirmation */
 678                 int attemps = 0;
 679                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 680                         if (attemps++ > 1000) {
 681                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 682                                        (~RRST),
 683                                        base + OMAP_MCBSP_REG_SPCR1);
 684                                 udelay(10);
 685                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 686                                        (RRST),
 687                                        base + OMAP_MCBSP_REG_SPCR1);
 688                                 udelay(10);
 689                                 dev_err(mcbsp->dev, "Could not read from"
 690                                         " McBSP%d Register\n", mcbsp->id);
 691                                 return -2;
 692                         }
 693                 }
 694         }
 695         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 696
 697         return 0;
 698 }
 699 EXPORT_SYMBOL(omap_mcbsp_pollread);
 700
 701 /*
 702  * IRQ based word transmission.
 703  */
 704 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 705 {
 706         struct omap_mcbsp *mcbsp;
 707         void __iomem *io_base;
 708         omap_mcbsp_word_length word_length;
 709
 710         if (!omap_mcbsp_check_valid_id(id)) {
 711                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 712                 return;
 713         }
 714
 715         mcbsp = id_to_mcbsp_ptr(id);
 716         io_base = mcbsp->io_base;
 717         word_length = mcbsp->tx_word_length;
 718
 719         wait_for_completion(&mcbsp->tx_irq_completion);
 720
 721         if (word_length > OMAP_MCBSP_WORD_16)
 722                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 723         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 724 }
 725 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 726
 727 u32 omap_mcbsp_recv_word(unsigned int id)
 728 {
 729         struct omap_mcbsp *mcbsp;
 730         void __iomem *io_base;
 731         u16 word_lsb, word_msb = 0;
 732         omap_mcbsp_word_length word_length;
 733
 734         if (!omap_mcbsp_check_valid_id(id)) {
 735                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 736                 return -ENODEV;
 737         }
 738         mcbsp = id_to_mcbsp_ptr(id);
 739
 740         word_length = mcbsp->rx_word_length;
 741         io_base = mcbsp->io_base;
 742
 743         wait_for_completion(&mcbsp->rx_irq_completion);
 744
 745         if (word_length > OMAP_MCBSP_WORD_16)
 746                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 747         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 748
 749         return (word_lsb | (word_msb << 16));
 750 }
 751 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 752
 753 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 754 {
 755         struct omap_mcbsp *mcbsp;
 756         void __iomem *io_base;
 757         omap_mcbsp_word_length tx_word_length;
 758         omap_mcbsp_word_length rx_word_length;
 759         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 760
 761         if (!omap_mcbsp_check_valid_id(id)) {
 762                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 763                 return -ENODEV;
 764         }
 765         mcbsp = id_to_mcbsp_ptr(id);
 766         io_base = mcbsp->io_base;
 767         tx_word_length = mcbsp->tx_word_length;
 768         rx_word_length = mcbsp->rx_word_length;
 769
 770         if (tx_word_length != rx_word_length)
 771                 return -EINVAL;
 772
 773         /* First we wait for the transmitter to be ready */
 774         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 775         while (!(spcr2 & XRDY)) {
 776                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 777                 if (attempts++ > 1000) {
 778                         /* We must reset the transmitter */
 779                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 780                         udelay(10);
 781                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 782                         udelay(10);
 783                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 784                                 "ready\n", mcbsp->id);
 785                         return -EAGAIN;
 786                 }
 787         }
 788
 789         /* Now we can push the data */
 790         if (tx_word_length > OMAP_MCBSP_WORD_16)
 791                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 792         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 793
 794         /* We wait for the receiver to be ready */
 795         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 796         while (!(spcr1 & RRDY)) {
 797                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 798                 if (attempts++ > 1000) {
 799                         /* We must reset the receiver */
 800                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 801                         udelay(10);
 802                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 803                         udelay(10);
 804                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 805                                 "ready\n", mcbsp->id);
 806                         return -EAGAIN;
 807                 }
 808         }
 809
 810         /* Receiver is ready, let's read the dummy data */
 811         if (rx_word_length > OMAP_MCBSP_WORD_16)
 812                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 813         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 814
 815         return 0;
 816 }
 817 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 818
 819 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 820 {
 821         struct omap_mcbsp *mcbsp;
 822         u32 clock_word = 0;
 823         void __iomem *io_base;
 824         omap_mcbsp_word_length tx_word_length;
 825         omap_mcbsp_word_length rx_word_length;
 826         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 827
 828         if (!omap_mcbsp_check_valid_id(id)) {
 829                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 830                 return -ENODEV;
 831         }
 832
 833         mcbsp = id_to_mcbsp_ptr(id);
 834         io_base = mcbsp->io_base;
 835
 836         tx_word_length = mcbsp->tx_word_length;
 837         rx_word_length = mcbsp->rx_word_length;
 838
 839         if (tx_word_length != rx_word_length)
 840                 return -EINVAL;
 841
 842         /* First we wait for the transmitter to be ready */
 843         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 844         while (!(spcr2 & XRDY)) {
 845                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 846                 if (attempts++ > 1000) {
 847                         /* We must reset the transmitter */
 848                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 849                         udelay(10);
 850                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 851                         udelay(10);
 852                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 853                                 "ready\n", mcbsp->id);
 854                         return -EAGAIN;
 855                 }
 856         }
 857
 858         /* We first need to enable the bus clock */
 859         if (tx_word_length > OMAP_MCBSP_WORD_16)
 860                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 861         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 862
 863         /* We wait for the receiver to be ready */
 864         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 865         while (!(spcr1 & RRDY)) {
 866                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 867                 if (attempts++ > 1000) {
 868                         /* We must reset the receiver */
 869                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 870                         udelay(10);
 871                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 872                         udelay(10);
 873                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 874                                 "ready\n", mcbsp->id);
 875                         return -EAGAIN;
 876                 }
 877         }
 878
 879         /* Receiver is ready, there is something for us */
 880         if (rx_word_length > OMAP_MCBSP_WORD_16)
 881                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 882         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 883
 884         word[0] = (word_lsb | (word_msb << 16));
 885
 886         return 0;
 887 }
 888 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 889
 890 /*
 891  * Simple DMA based buffer rx/tx routines.
 892  * Nothing fancy, just a single buffer tx/rx through DMA.
 893  * The DMA resources are released once the transfer is done.
 894  * For anything fancier, you should use your own customized DMA
 895  * routines and callbacks.
 896  */
 897 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 898                                 unsigned int length)
 899 {
 900         struct omap_mcbsp *mcbsp;
 901         int dma_tx_ch;
 902         int src_port = 0;
 903         int dest_port = 0;
 904         int sync_dev = 0;
 905
 906         if (!omap_mcbsp_check_valid_id(id)) {
 907                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 908                 return -ENODEV;
 909         }
 910         mcbsp = id_to_mcbsp_ptr(id);
 911
 912         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 913                                 omap_mcbsp_tx_dma_callback,
 914                                 mcbsp,
 915                                 &dma_tx_ch)) {
 916                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 917                                 "McBSP%d TX. Trying IRQ based TX\n",
 918                                 mcbsp->id);
 919                 return -EAGAIN;
 920         }
 921         mcbsp->dma_tx_lch = dma_tx_ch;
 922
 923         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 924                 dma_tx_ch);
 925
 926         init_completion(&mcbsp->tx_dma_completion);
 927
 928         if (cpu_class_is_omap1()) {
 929                 src_port = OMAP_DMA_PORT_TIPB;
 930                 dest_port = OMAP_DMA_PORT_EMIFF;
 931         }
 932         if (cpu_class_is_omap2())
 933                 sync_dev = mcbsp->dma_tx_sync;
 934
 935         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 936                                      OMAP_DMA_DATA_TYPE_S16,
 937                                      length >> 1, 1,
 938                                      OMAP_DMA_SYNC_ELEMENT,
 939          sync_dev, 0);
 940
 941         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 942                                  src_port,
 943                                  OMAP_DMA_AMODE_CONSTANT,
 944                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 945                                  0, 0);
 946
 947         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 948                                 dest_port,
 949                                 OMAP_DMA_AMODE_POST_INC,
 950                                 buffer,
 951                                 0, 0);
 952
 953         omap_start_dma(mcbsp->dma_tx_lch);
 954         wait_for_completion(&mcbsp->tx_dma_completion);
 955
 956         return 0;
 957 }
 958 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 959
 960 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 961                                 unsigned int length)
 962 {
 963         struct omap_mcbsp *mcbsp;
 964         int dma_rx_ch;
 965         int src_port = 0;
 966         int dest_port = 0;
 967         int sync_dev = 0;
 968
 969         if (!omap_mcbsp_check_valid_id(id)) {
 970                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 971                 return -ENODEV;
 972         }
 973         mcbsp = id_to_mcbsp_ptr(id);
 974
 975         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 976                                 omap_mcbsp_rx_dma_callback,
 977                                 mcbsp,
 978                                 &dma_rx_ch)) {
 979                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
 980                                 "McBSP%d RX. Trying IRQ based RX\n",
 981                                 mcbsp->id);
 982                 return -EAGAIN;
 983         }
 984         mcbsp->dma_rx_lch = dma_rx_ch;
 985
 986         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
 987                 dma_rx_ch);
 988
 989         init_completion(&mcbsp->rx_dma_completion);
 990
 991         if (cpu_class_is_omap1()) {
 992                 src_port = OMAP_DMA_PORT_TIPB;
 993                 dest_port = OMAP_DMA_PORT_EMIFF;
 994         }
 995         if (cpu_class_is_omap2())
 996                 sync_dev = mcbsp->dma_rx_sync;
 997
 998         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
 999                                         OMAP_DMA_DATA_TYPE_S16,
1000                                         length >> 1, 1,
1001                                         OMAP_DMA_SYNC_ELEMENT,
1002                                         sync_dev, 0);
1003
1004         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1005                                 src_port,
1006                                 OMAP_DMA_AMODE_CONSTANT,
1007                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1008                                 0, 0);
1009
1010         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1011                                         dest_port,
1012                                         OMAP_DMA_AMODE_POST_INC,
1013                                         buffer,
1014                                         0, 0);
1015
1016         omap_start_dma(mcbsp->dma_rx_lch);
1017         wait_for_completion(&mcbsp->rx_dma_completion);
1018
1019         return 0;
1020 }
1021 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1022
1023 /*
1024  * SPI wrapper.
1025  * Since SPI setup is much simpler than the generic McBSP one,
1026  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1027  * Once this is done, you can call omap_mcbsp_start().
1028  */
1029 void omap_mcbsp_set_spi_mode(unsigned int id,
1030                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1031 {
1032         struct omap_mcbsp *mcbsp;
1033         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1034
1035         if (!omap_mcbsp_check_valid_id(id)) {
1036                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1037                 return;
1038         }
1039         mcbsp = id_to_mcbsp_ptr(id);
1040
1041         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1042
1043         /* SPI has only one frame */
1044         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1045         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1046
1047         /* Clock stop mode */
1048         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1049                 mcbsp_cfg.spcr1 |= (1 << 12);
1050         else
1051                 mcbsp_cfg.spcr1 |= (3 << 11);
1052
1053         /* Set clock parities */
1054         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1055                 mcbsp_cfg.pcr0 |= CLKRP;
1056         else
1057                 mcbsp_cfg.pcr0 &= ~CLKRP;
1058
1059         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1060                 mcbsp_cfg.pcr0 &= ~CLKXP;
1061         else
1062                 mcbsp_cfg.pcr0 |= CLKXP;
1063
1064         /* Set SCLKME to 0 and CLKSM to 1 */
1065         mcbsp_cfg.pcr0 &= ~SCLKME;
1066         mcbsp_cfg.srgr2 |= CLKSM;
1067
1068         /* Set FSXP */
1069         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1070                 mcbsp_cfg.pcr0 &= ~FSXP;
1071         else
1072                 mcbsp_cfg.pcr0 |= FSXP;
1073
1074         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1075                 mcbsp_cfg.pcr0 |= CLKXM;
1076                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1077                 mcbsp_cfg.pcr0 |= FSXM;
1078                 mcbsp_cfg.srgr2 &= ~FSGM;
1079                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1080                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1081         } else {
1082                 mcbsp_cfg.pcr0 &= ~CLKXM;
1083                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1084                 mcbsp_cfg.pcr0 &= ~FSXM;
1085                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1086                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1087         }
1088
1089         mcbsp_cfg.xcr2 &= ~XPHASE;
1090         mcbsp_cfg.rcr2 &= ~RPHASE;
1091
1092         omap_mcbsp_config(id, &mcbsp_cfg);
1093 }
1094 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1095
1096 #ifdef CONFIG_ARCH_OMAP34XX
1097 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1098 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1099 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1100 static ssize_t prop##_show(struct device *dev,                          \
1101                         struct device_attribute *attr, char *buf)       \
1102 {                                                                       \
1103         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1104                                                                         \
1105         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1106 }                                                                       \
1107                                                                         \
1108 static ssize_t prop##_store(struct device *dev,                         \
1109                                 struct device_attribute *attr,          \
1110                                 const char *buf, size_t size)           \
1111 {                                                                       \
1112         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1113         unsigned long val;                                              \
1114         int status;                                                     \
1115                                                                         \
1116         status = strict_strtoul(buf, 0, &val);                          \
1117         if (status)                                                     \
1118                 return status;                                          \
1119                                                                         \
1120         if (!valid_threshold(mcbsp, val))                               \
1121                 return -EDOM;                                           \
1122                                                                         \
1123         mcbsp->prop = val;                                              \
1124         return size;                                                    \
1125 }                                                                       \
1126                                                                         \
1127 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1128
1129 THRESHOLD_PROP_BUILDER(max_tx_thres);
1130 THRESHOLD_PROP_BUILDER(max_rx_thres);
1131
1132 static const char *dma_op_modes[] = {
1133         "element", "threshold", "frame",
1134 };
1135
1136 static ssize_t dma_op_mode_show(struct device *dev,
1137                         struct device_attribute *attr, char *buf)
1138 {
1139         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1140         int dma_op_mode, i = 0;
1141         ssize_t len = 0;
1142         const char * const *s;
1143
1144         dma_op_mode = mcbsp->dma_op_mode;
1145
1146         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1147                 if (dma_op_mode == i)
1148                         len += sprintf(buf + len, "[%s] ", *s);
1149                 else
1150                         len += sprintf(buf + len, "%s ", *s);
1151         }
1152         len += sprintf(buf + len, "\n");
1153
1154         return len;
1155 }
1156
1157 static ssize_t dma_op_mode_store(struct device *dev,
1158                                 struct device_attribute *attr,
1159                                 const char *buf, size_t size)
1160 {
1161         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1162         const char * const *s;
1163         int i = 0;
1164
1165         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1166                 if (sysfs_streq(buf, *s))
1167                         break;
1168
1169         if (i == ARRAY_SIZE(dma_op_modes))
1170                 return -EINVAL;
1171
1172         spin_lock_irq(&mcbsp->lock);
1173         if (!mcbsp->free) {
1174                 size = -EBUSY;
1175                 goto unlock;
1176         }
1177         mcbsp->dma_op_mode = i;
1178
1179 unlock:
1180         spin_unlock_irq(&mcbsp->lock);
1181
1182         return size;
1183 }
1184
1185 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1186
1187 static const struct attribute *additional_attrs[] = {
1188         &dev_attr_max_tx_thres.attr,
1189         &dev_attr_max_rx_thres.attr,
1190         &dev_attr_dma_op_mode.attr,
1191         NULL,
1192 };
1193
1194 static const struct attribute_group additional_attr_group = {
1195         .attrs = (struct attribute **)additional_attrs,
1196 };
1197
1198 static inline int __devinit omap_additional_add(struct device *dev)
1199 {
1200         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1201 }
1202
1203 static inline void __devexit omap_additional_remove(struct device *dev)
1204 {
1205         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1206 }
1207
1208 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1209 {
1210         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1211         if (cpu_is_omap34xx()) {
1212                 mcbsp->max_tx_thres = max_thres(mcbsp);
1213                 mcbsp->max_rx_thres = max_thres(mcbsp);
1214                 /*
1215                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1216                  * for mcbsp2 instances.
1217                  */
1218                 if (omap_additional_add(mcbsp->dev))
1219                         dev_warn(mcbsp->dev,
1220                                 "Unable to create additional controls\n");
1221         } else {
1222                 mcbsp->max_tx_thres = -EINVAL;
1223                 mcbsp->max_rx_thres = -EINVAL;
1224         }
1225 }
1226
1227 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1228 {
1229         if (cpu_is_omap34xx())
1230                 omap_additional_remove(mcbsp->dev);
1231 }
1232 #else
1233 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1234 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1235 #endif /* CONFIG_ARCH_OMAP34XX */
1236
1237 /*
1238  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1239  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1240  */
1241 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1242 {
1243         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1244         struct omap_mcbsp *mcbsp;
1245         int id = pdev->id - 1;
1246         int ret = 0;
1247
1248         if (!pdata) {
1249                 dev_err(&pdev->dev, "McBSP device initialized without"
1250                                 "platform data\n");
1251                 ret = -EINVAL;
1252                 goto exit;
1253         }
1254
1255         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1256
1257         if (id >= omap_mcbsp_count) {
1258                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1259                 ret = -EINVAL;
1260                 goto exit;
1261         }
1262
1263         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1264         if (!mcbsp) {
1265                 ret = -ENOMEM;
1266                 goto exit;
1267         }
1268
1269         spin_lock_init(&mcbsp->lock);
1270         mcbsp->id = id + 1;
1271         mcbsp->free = 1;
1272         mcbsp->dma_tx_lch = -1;
1273         mcbsp->dma_rx_lch = -1;
1274
1275         mcbsp->phys_base = pdata->phys_base;
1276         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1277         if (!mcbsp->io_base) {
1278                 ret = -ENOMEM;
1279                 goto err_ioremap;
1280         }
1281
1282         /* Default I/O is IRQ based */
1283         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1284         mcbsp->tx_irq = pdata->tx_irq;
1285         mcbsp->rx_irq = pdata->rx_irq;
1286         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1287         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1288
1289         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1290         if (IS_ERR(mcbsp->iclk)) {
1291                 ret = PTR_ERR(mcbsp->iclk);
1292                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1293                 goto err_iclk;
1294         }
1295
1296         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1297         if (IS_ERR(mcbsp->fclk)) {
1298                 ret = PTR_ERR(mcbsp->fclk);
1299                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1300                 goto err_fclk;
1301         }
1302
1303         mcbsp->pdata = pdata;
1304         mcbsp->dev = &pdev->dev;
1305         mcbsp_ptr[id] = mcbsp;
1306         platform_set_drvdata(pdev, mcbsp);
1307
1308         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1309         omap34xx_device_init(mcbsp);
1310
1311         return 0;
1312
1313 err_fclk:
1314         clk_put(mcbsp->iclk);
1315 err_iclk:
1316         iounmap(mcbsp->io_base);
1317 err_ioremap:
1318         kfree(mcbsp);
1319 exit:
1320         return ret;
1321 }
1322
1323 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1324 {
1325         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1326
1327         platform_set_drvdata(pdev, NULL);
1328         if (mcbsp) {
1329
1330                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1331                                 mcbsp->pdata->ops->free)
1332                         mcbsp->pdata->ops->free(mcbsp->id);
1333
1334                 omap34xx_device_exit(mcbsp);
1335
1336                 clk_disable(mcbsp->fclk);
1337                 clk_disable(mcbsp->iclk);
1338                 clk_put(mcbsp->fclk);
1339                 clk_put(mcbsp->iclk);
1340
1341                 iounmap(mcbsp->io_base);
1342
1343                 mcbsp->fclk = NULL;
1344                 mcbsp->iclk = NULL;
1345                 mcbsp->free = 0;
1346                 mcbsp->dev = NULL;
1347         }
1348
1349         return 0;
1350 }
1351
1352 static struct platform_driver omap_mcbsp_driver = {
1353         .probe          = omap_mcbsp_probe,
1354         .remove         = __devexit_p(omap_mcbsp_remove),
1355         .driver         = {
1356                 .name   = "omap-mcbsp",
1357         },
1358 };
1359
1360 int __init omap_mcbsp_init(void)
1361 {
1362         /* Register the McBSP driver */
1363         return platform_driver_register(&omap_mcbsp_driver);
1364 }