arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/hardware.h>
  31 #include <asm/dma.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #define DEBUG_PRINTS
  37 #undef DEBUG_PRINTS
  38 #ifdef DEBUG_PRINTS
  39 #define debug_printk(x) printk x
  40 #else
  41 #define debug_printk(x)
  42 #endif
  43
  44 #define OMAP_DMA_ACTIVE         0x01
  45 #define OMAP_DMA_CCR_EN         (1 << 7)
  46 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  47
  48 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  49
  50 static int enable_1510_mode = 0;
  51
  52 struct omap_dma_lch {
  53         int next_lch;
  54         int dev_id;
  55         u16 saved_csr;
  56         u16 enabled_irqs;
  57         const char *dev_name;
  58         void (* callback)(int lch, u16 ch_status, void *data);
  59         void *data;
  60         long flags;
  61 };
  62
  63 static int dma_chan_count;
  64
  65 static spinlock_t dma_chan_lock;
  66 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  67
  68 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  69         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  70         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  71         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  72         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  73         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  74 };
  75
  76 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
  77                                                 __FUNCTION__);
  78
  79 #ifdef CONFIG_ARCH_OMAP15XX
  80 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
  81 int omap_dma_in_1510_mode(void)
  82 {
  83         return enable_1510_mode;
  84 }
  85 #else
  86 #define omap_dma_in_1510_mode()         0
  87 #endif
  88
  89 #ifdef CONFIG_ARCH_OMAP1
  90 static inline int get_gdma_dev(int req)
  91 {
  92         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  93         int shift = ((req - 1) % 5) * 6;
  94
  95         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  96 }
  97
  98 static inline void set_gdma_dev(int req, int dev)
  99 {
 100         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 101         int shift = ((req - 1) % 5) * 6;
 102         u32 l;
 103
 104         l = omap_readl(reg);
 105         l &= ~(0x3f << shift);
 106         l |= (dev - 1) << shift;
 107         omap_writel(l, reg);
 108 }
 109 #else
 110 #define set_gdma_dev(req, dev)  do {} while (0)
 111 #endif
 112
 113 static void clear_lch_regs(int lch)
 114 {
 115         int i;
 116         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
 117
 118         for (i = 0; i < 0x2c; i += 2)
 119                 omap_writew(0, lch_base + i);
 120 }
 121
 122 void omap_set_dma_priority(int dst_port, int priority)
 123 {
 124         unsigned long reg;
 125         u32 l;
 126
 127         switch (dst_port) {
 128         case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 129                 reg = OMAP_TC_OCPT1_PRIOR;
 130                 break;
 131         case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 132                 reg = OMAP_TC_OCPT2_PRIOR;
 133                 break;
 134         case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 135                 reg = OMAP_TC_EMIFF_PRIOR;
 136                 break;
 137         case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 138                 reg = OMAP_TC_EMIFS_PRIOR;
 139                 break;
 140         default:
 141                 BUG();
 142                 return;
 143         }
 144         l = omap_readl(reg);
 145         l &= ~(0xf << 8);
 146         l |= (priority & 0xf) << 8;
 147         omap_writel(l, reg);
 148 }
 149
 150 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 151                                   int frame_count, int sync_mode,
 152                                   int dma_trigger, int src_or_dst_synch)
 153 {
 154         OMAP_DMA_CSDP_REG(lch) &= ~0x03;
 155         OMAP_DMA_CSDP_REG(lch) |= data_type;
 156
 157         if (cpu_class_is_omap1()) {
 158                 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
 159                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 160                         OMAP_DMA_CCR_REG(lch) |= 1 << 5;
 161
 162                 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
 163                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 164                         OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
 165         }
 166
 167         if (cpu_is_omap24xx() && dma_trigger) {
 168                 u32 val = OMAP_DMA_CCR_REG(lch);
 169
 170                 val &= ~(3 << 19);
 171                 if (dma_trigger > 63)
 172                         val |= 1 << 20;
 173                 if (dma_trigger > 31)
 174                         val |= 1 << 19;
 175
 176                 val &= ~(0x1f);
 177                 val |= (dma_trigger & 0x1f);
 178
 179                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 180                         val |= 1 << 5;
 181                 else
 182                         val &= ~(1 << 5);
 183
 184                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 185                         val |= 1 << 18;
 186                 else
 187                         val &= ~(1 << 18);
 188
 189                 if (src_or_dst_synch)
 190                         val |= 1 << 24;         /* source synch */
 191                 else
 192                         val &= ~(1 << 24);      /* dest synch */
 193
 194                 OMAP_DMA_CCR_REG(lch) = val;
 195         }
 196
 197         OMAP_DMA_CEN_REG(lch) = elem_count;
 198         OMAP_DMA_CFN_REG(lch) = frame_count;
 199 }
 200
 201 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 202 {
 203         u16 w;
 204
 205         BUG_ON(omap_dma_in_1510_mode());
 206
 207         if (cpu_is_omap24xx()) {
 208                 REVISIT_24XX();
 209                 return;
 210         }
 211
 212         w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
 213         switch (mode) {
 214         case OMAP_DMA_CONSTANT_FILL:
 215                 w |= 0x01;
 216                 break;
 217         case OMAP_DMA_TRANSPARENT_COPY:
 218                 w |= 0x02;
 219                 break;
 220         case OMAP_DMA_COLOR_DIS:
 221                 break;
 222         default:
 223                 BUG();
 224         }
 225         OMAP1_DMA_CCR2_REG(lch) = w;
 226
 227         w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
 228         /* Default is channel type 2D */
 229         if (mode) {
 230                 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
 231                 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
 232                 w |= 1;         /* Channel type G */
 233         }
 234         OMAP1_DMA_LCH_CTRL_REG(lch) = w;
 235 }
 236
 237 /* Note that src_port is only for omap1 */
 238 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 239                              unsigned long src_start,
 240                              int src_ei, int src_fi)
 241 {
 242         if (cpu_class_is_omap1()) {
 243                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
 244                 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
 245         }
 246
 247         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
 248         OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
 249
 250         if (cpu_class_is_omap1()) {
 251                 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
 252                 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
 253         }
 254
 255         if (cpu_is_omap24xx())
 256                 OMAP2_DMA_CSSA_REG(lch) = src_start;
 257
 258         OMAP_DMA_CSEI_REG(lch) = src_ei;
 259         OMAP_DMA_CSFI_REG(lch) = src_fi;
 260 }
 261
 262 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
 263 {
 264         omap_set_dma_transfer_params(lch, params->data_type,
 265                                      params->elem_count, params->frame_count,
 266                                      params->sync_mode, params->trigger,
 267                                      params->src_or_dst_synch);
 268         omap_set_dma_src_params(lch, params->src_port,
 269                                 params->src_amode, params->src_start,
 270                                 params->src_ei, params->src_fi);
 271
 272         omap_set_dma_dest_params(lch, params->dst_port,
 273                                  params->dst_amode, params->dst_start,
 274                                  params->dst_ei, params->dst_fi);
 275 }
 276
 277 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 278 {
 279         if (cpu_is_omap24xx()) {
 280                 REVISIT_24XX();
 281                 return;
 282         }
 283         OMAP_DMA_CSEI_REG(lch) = eidx;
 284         OMAP_DMA_CSFI_REG(lch) = fidx;
 285 }
 286
 287 void omap_set_dma_src_data_pack(int lch, int enable)
 288 {
 289         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
 290         if (enable)
 291                 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
 292 }
 293
 294 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 295 {
 296         unsigned int burst = 0;
 297         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
 298
 299         switch (burst_mode) {
 300         case OMAP_DMA_DATA_BURST_DIS:
 301                 break;
 302         case OMAP_DMA_DATA_BURST_4:
 303                 if (cpu_is_omap24xx())
 304                         burst = 0x1;
 305                 else
 306                         burst = 0x2;
 307                 break;
 308         case OMAP_DMA_DATA_BURST_8:
 309                 if (cpu_is_omap24xx()) {
 310                         burst = 0x2;
 311                         break;
 312                 }
 313                 /* not supported by current hardware on OMAP1
 314                  * w |= (0x03 << 7);
 315                  * fall through
 316                  */
 317         case OMAP_DMA_DATA_BURST_16:
 318                 if (cpu_is_omap24xx()) {
 319                         burst = 0x3;
 320                         break;
 321                 }
 322                 /* OMAP1 don't support burst 16
 323                  * fall through
 324                  */
 325         default:
 326                 BUG();
 327         }
 328         OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
 329 }
 330
 331 /* Note that dest_port is only for OMAP1 */
 332 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 333                               unsigned long dest_start,
 334                               int dst_ei, int dst_fi)
 335 {
 336         if (cpu_class_is_omap1()) {
 337                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
 338                 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
 339         }
 340
 341         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
 342         OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
 343
 344         if (cpu_class_is_omap1()) {
 345                 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
 346                 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
 347         }
 348
 349         if (cpu_is_omap24xx())
 350                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
 351
 352         OMAP_DMA_CDEI_REG(lch) = dst_ei;
 353         OMAP_DMA_CDFI_REG(lch) = dst_fi;
 354 }
 355
 356 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 357 {
 358         if (cpu_is_omap24xx()) {
 359                 REVISIT_24XX();
 360                 return;
 361         }
 362         OMAP_DMA_CDEI_REG(lch) = eidx;
 363         OMAP_DMA_CDFI_REG(lch) = fidx;
 364 }
 365
 366 void omap_set_dma_dest_data_pack(int lch, int enable)
 367 {
 368         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
 369         if (enable)
 370                 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
 371 }
 372
 373 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 374 {
 375         unsigned int burst = 0;
 376         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
 377
 378         switch (burst_mode) {
 379         case OMAP_DMA_DATA_BURST_DIS:
 380                 break;
 381         case OMAP_DMA_DATA_BURST_4:
 382                 if (cpu_is_omap24xx())
 383                         burst = 0x1;
 384                 else
 385                         burst = 0x2;
 386                 break;
 387         case OMAP_DMA_DATA_BURST_8:
 388                 if (cpu_is_omap24xx())
 389                         burst = 0x2;
 390                 else
 391                         burst = 0x3;
 392                 break;
 393         case OMAP_DMA_DATA_BURST_16:
 394                 if (cpu_is_omap24xx()) {
 395                         burst = 0x3;
 396                         break;
 397                 }
 398                 /* OMAP1 don't support burst 16
 399                  * fall through
 400                  */
 401         default:
 402                 printk(KERN_ERR "Invalid DMA burst mode\n");
 403                 BUG();
 404                 return;
 405         }
 406         OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
 407 }
 408
 409 static inline void omap_enable_channel_irq(int lch)
 410 {
 411         u32 status;
 412
 413         /* Clear CSR */
 414         if (cpu_class_is_omap1())
 415                 status = OMAP_DMA_CSR_REG(lch);
 416         else if (cpu_is_omap24xx())
 417                 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 418
 419         /* Enable some nice interrupts. */
 420         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
 421
 422         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 423 }
 424
 425 static void omap_disable_channel_irq(int lch)
 426 {
 427         if (cpu_is_omap24xx())
 428                 OMAP_DMA_CICR_REG(lch) = 0;
 429 }
 430
 431 void omap_enable_dma_irq(int lch, u16 bits)
 432 {
 433         dma_chan[lch].enabled_irqs |= bits;
 434 }
 435
 436 void omap_disable_dma_irq(int lch, u16 bits)
 437 {
 438         dma_chan[lch].enabled_irqs &= ~bits;
 439 }
 440
 441 static inline void enable_lnk(int lch)
 442 {
 443         if (cpu_class_is_omap1())
 444                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
 445
 446         /* Set the ENABLE_LNK bits */
 447         if (dma_chan[lch].next_lch != -1)
 448                 OMAP_DMA_CLNK_CTRL_REG(lch) =
 449                         dma_chan[lch].next_lch | (1 << 15);
 450 }
 451
 452 static inline void disable_lnk(int lch)
 453 {
 454         /* Disable interrupts */
 455         if (cpu_class_is_omap1()) {
 456                 OMAP_DMA_CICR_REG(lch) = 0;
 457                 /* Set the STOP_LNK bit */
 458                 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
 459         }
 460
 461         if (cpu_is_omap24xx()) {
 462                 omap_disable_channel_irq(lch);
 463                 /* Clear the ENABLE_LNK bit */
 464                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
 465         }
 466
 467         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 468 }
 469
 470 static inline void omap2_enable_irq_lch(int lch)
 471 {
 472         u32 val;
 473
 474         if (!cpu_is_omap24xx())
 475                 return;
 476
 477         val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 478         val |= 1 << lch;
 479         omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 480 }
 481
 482 int omap_request_dma(int dev_id, const char *dev_name,
 483                      void (* callback)(int lch, u16 ch_status, void *data),
 484                      void *data, int *dma_ch_out)
 485 {
 486         int ch, free_ch = -1;
 487         unsigned long flags;
 488         struct omap_dma_lch *chan;
 489
 490         spin_lock_irqsave(&dma_chan_lock, flags);
 491         for (ch = 0; ch < dma_chan_count; ch++) {
 492                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 493                         free_ch = ch;
 494                         if (dev_id == 0)
 495                                 break;
 496                 }
 497         }
 498         if (free_ch == -1) {
 499                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 500                 return -EBUSY;
 501         }
 502         chan = dma_chan + free_ch;
 503         chan->dev_id = dev_id;
 504
 505         if (cpu_class_is_omap1())
 506                 clear_lch_regs(free_ch);
 507
 508         if (cpu_is_omap24xx())
 509                 omap_clear_dma(free_ch);
 510
 511         spin_unlock_irqrestore(&dma_chan_lock, flags);
 512
 513         chan->dev_name = dev_name;
 514         chan->callback = callback;
 515         chan->data = data;
 516         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 517
 518         if (cpu_class_is_omap1())
 519                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 520         else if (cpu_is_omap24xx())
 521                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 522                         OMAP2_DMA_TRANS_ERR_IRQ;
 523
 524         if (cpu_is_omap16xx()) {
 525                 /* If the sync device is set, configure it dynamically. */
 526                 if (dev_id != 0) {
 527                         set_gdma_dev(free_ch + 1, dev_id);
 528                         dev_id = free_ch + 1;
 529                 }
 530                 /* Disable the 1510 compatibility mode and set the sync device
 531                  * id. */
 532                 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
 533         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 534                 OMAP_DMA_CCR_REG(free_ch) = dev_id;
 535         }
 536
 537         if (cpu_is_omap24xx()) {
 538                 omap2_enable_irq_lch(free_ch);
 539
 540                 omap_enable_channel_irq(free_ch);
 541                 /* Clear the CSR register and IRQ status register */
 542                 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
 543                 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
 544         }
 545
 546         *dma_ch_out = free_ch;
 547
 548         return 0;
 549 }
 550
 551 void omap_free_dma(int lch)
 552 {
 553         unsigned long flags;
 554
 555         spin_lock_irqsave(&dma_chan_lock, flags);
 556         if (dma_chan[lch].dev_id == -1) {
 557                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
 558                        lch);
 559                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 560                 return;
 561         }
 562         dma_chan[lch].dev_id = -1;
 563         dma_chan[lch].next_lch = -1;
 564         dma_chan[lch].callback = NULL;
 565         spin_unlock_irqrestore(&dma_chan_lock, flags);
 566
 567         if (cpu_class_is_omap1()) {
 568                 /* Disable all DMA interrupts for the channel. */
 569                 OMAP_DMA_CICR_REG(lch) = 0;
 570                 /* Make sure the DMA transfer is stopped. */
 571                 OMAP_DMA_CCR_REG(lch) = 0;
 572         }
 573
 574         if (cpu_is_omap24xx()) {
 575                 u32 val;
 576                 /* Disable interrupts */
 577                 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 578                 val &= ~(1 << lch);
 579                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 580
 581                 /* Clear the CSR register and IRQ status register */
 582                 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 583
 584                 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 585                 val |= 1 << lch;
 586                 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 587
 588                 /* Disable all DMA interrupts for the channel. */
 589                 OMAP_DMA_CICR_REG(lch) = 0;
 590
 591                 /* Make sure the DMA transfer is stopped. */
 592                 OMAP_DMA_CCR_REG(lch) = 0;
 593                 omap_clear_dma(lch);
 594         }
 595 }
 596
 597 /*
 598  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 599  * through omap_start_dma(). Any buffers in flight are discarded.
 600  */
 601 void omap_clear_dma(int lch)
 602 {
 603         unsigned long flags;
 604
 605         local_irq_save(flags);
 606
 607         if (cpu_class_is_omap1()) {
 608                 int status;
 609                 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 610
 611                 /* Clear pending interrupts */
 612                 status = OMAP_DMA_CSR_REG(lch);
 613         }
 614
 615         if (cpu_is_omap24xx()) {
 616                 int i;
 617                 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
 618                 for (i = 0; i < 0x44; i += 4)
 619                         omap_writel(0, lch_base + i);
 620         }
 621
 622         local_irq_restore(flags);
 623 }
 624
 625 void omap_start_dma(int lch)
 626 {
 627         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 628                 int next_lch, cur_lch;
 629                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 630
 631                 dma_chan_link_map[lch] = 1;
 632                 /* Set the link register of the first channel */
 633                 enable_lnk(lch);
 634
 635                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 636                 cur_lch = dma_chan[lch].next_lch;
 637                 do {
 638                         next_lch = dma_chan[cur_lch].next_lch;
 639
 640                         /* The loop case: we've been here already */
 641                         if (dma_chan_link_map[cur_lch])
 642                                 break;
 643                         /* Mark the current channel */
 644                         dma_chan_link_map[cur_lch] = 1;
 645
 646                         enable_lnk(cur_lch);
 647                         omap_enable_channel_irq(cur_lch);
 648
 649                         cur_lch = next_lch;
 650                 } while (next_lch != -1);
 651         } else if (cpu_is_omap24xx()) {
 652                 /* Errata: Need to write lch even if not using chaining */
 653                 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
 654         }
 655
 656         omap_enable_channel_irq(lch);
 657
 658         /* Errata: On ES2.0 BUFFERING disable must be set.
 659          * This will always fail on ES1.0 */
 660         if (cpu_is_omap24xx()) {
 661                 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 662         }
 663
 664         OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 665
 666         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 667 }
 668
 669 void omap_stop_dma(int lch)
 670 {
 671         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 672                 int next_lch, cur_lch = lch;
 673                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 674
 675                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 676                 do {
 677                         /* The loop case: we've been here already */
 678                         if (dma_chan_link_map[cur_lch])
 679                                 break;
 680                         /* Mark the current channel */
 681                         dma_chan_link_map[cur_lch] = 1;
 682
 683                         disable_lnk(cur_lch);
 684
 685                         next_lch = dma_chan[cur_lch].next_lch;
 686                         cur_lch = next_lch;
 687                 } while (next_lch != -1);
 688
 689                 return;
 690         }
 691
 692         /* Disable all interrupts on the channel */
 693         if (cpu_class_is_omap1())
 694                 OMAP_DMA_CICR_REG(lch) = 0;
 695
 696         OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 697         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 698 }
 699
 700 /*
 701  * Returns current physical source address for the given DMA channel.
 702  * If the channel is running the caller must disable interrupts prior calling
 703  * this function and process the returned value before re-enabling interrupt to
 704  * prevent races with the interrupt handler. Note that in continuous mode there
 705  * is a chance for CSSA_L register overflow inbetween the two reads resulting
 706  * in incorrect return value.
 707  */
 708 dma_addr_t omap_get_dma_src_pos(int lch)
 709 {
 710         dma_addr_t offset;
 711
 712         if (cpu_class_is_omap1())
 713                 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
 714                                        (OMAP1_DMA_CSSA_U_REG(lch) << 16));
 715
 716         if (cpu_is_omap24xx())
 717                 offset = OMAP_DMA_CSAC_REG(lch);
 718
 719         return offset;
 720 }
 721
 722 /*
 723  * Returns current physical destination address for the given DMA channel.
 724  * If the channel is running the caller must disable interrupts prior calling
 725  * this function and process the returned value before re-enabling interrupt to
 726  * prevent races with the interrupt handler. Note that in continuous mode there
 727  * is a chance for CDSA_L register overflow inbetween the two reads resulting
 728  * in incorrect return value.
 729  */
 730 dma_addr_t omap_get_dma_dst_pos(int lch)
 731 {
 732         dma_addr_t offset;
 733
 734         if (cpu_class_is_omap1())
 735                 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
 736                                        (OMAP1_DMA_CDSA_U_REG(lch) << 16));
 737
 738         if (cpu_is_omap24xx())
 739                 offset = OMAP2_DMA_CDSA_REG(lch);
 740
 741         return offset;
 742 }
 743
 744 /*
 745  * Returns current source transfer counting for the given DMA channel.
 746  * Can be used to monitor the progress of a transfer inside a block.
 747  * It must be called with disabled interrupts.
 748  */
 749 int omap_get_dma_src_addr_counter(int lch)
 750 {
 751         return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
 752 }
 753
 754 int omap_dma_running(void)
 755 {
 756         int lch;
 757
 758         /* Check if LCD DMA is running */
 759         if (cpu_is_omap16xx())
 760                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
 761                         return 1;
 762
 763         for (lch = 0; lch < dma_chan_count; lch++)
 764                 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
 765                         return 1;
 766
 767         return 0;
 768 }
 769
 770 /*
 771  * lch_queue DMA will start right after lch_head one is finished.
 772  * For this DMA link to start, you still need to start (see omap_start_dma)
 773  * the first one. That will fire up the entire queue.
 774  */
 775 void omap_dma_link_lch (int lch_head, int lch_queue)
 776 {
 777         if (omap_dma_in_1510_mode()) {
 778                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 779                 BUG();
 780                 return;
 781         }
 782
 783         if ((dma_chan[lch_head].dev_id == -1) ||
 784             (dma_chan[lch_queue].dev_id == -1)) {
 785                 printk(KERN_ERR "omap_dma: trying to link "
 786                        "non requested channels\n");
 787                 dump_stack();
 788         }
 789
 790         dma_chan[lch_head].next_lch = lch_queue;
 791 }
 792
 793 /*
 794  * Once the DMA queue is stopped, we can destroy it.
 795  */
 796 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 797 {
 798         if (omap_dma_in_1510_mode()) {
 799                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 800                 BUG();
 801                 return;
 802         }
 803
 804         if (dma_chan[lch_head].next_lch != lch_queue ||
 805             dma_chan[lch_head].next_lch == -1) {
 806                 printk(KERN_ERR "omap_dma: trying to unlink "
 807                        "non linked channels\n");
 808                 dump_stack();
 809         }
 810
 811
 812         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 813             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 814                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
 815                        "before unlinking\n");
 816                 dump_stack();
 817         }
 818
 819         dma_chan[lch_head].next_lch = -1;
 820 }
 821
 822 /*----------------------------------------------------------------------------*/
 823
 824 #ifdef CONFIG_ARCH_OMAP1
 825
 826 static int omap1_dma_handle_ch(int ch)
 827 {
 828         u16 csr;
 829
 830         if (enable_1510_mode && ch >= 6) {
 831                 csr = dma_chan[ch].saved_csr;
 832                 dma_chan[ch].saved_csr = 0;
 833         } else
 834                 csr = OMAP_DMA_CSR_REG(ch);
 835         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 836                 dma_chan[ch + 6].saved_csr = csr >> 7;
 837                 csr &= 0x7f;
 838         }
 839         if ((csr & 0x3f) == 0)
 840                 return 0;
 841         if (unlikely(dma_chan[ch].dev_id == -1)) {
 842                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
 843                        "%d (CSR %04x)\n", ch, csr);
 844                 return 0;
 845         }
 846         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
 847                 printk(KERN_WARNING "DMA timeout with device %d\n",
 848                        dma_chan[ch].dev_id);
 849         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 850                 printk(KERN_WARNING "DMA synchronization event drop occurred "
 851                        "with device %d\n", dma_chan[ch].dev_id);
 852         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 853                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 854         if (likely(dma_chan[ch].callback != NULL))
 855                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 856         return 1;
 857 }
 858
 859 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
 860                                          struct pt_regs *regs)
 861 {
 862         int ch = ((int) dev_id) - 1;
 863         int handled = 0;
 864
 865         for (;;) {
 866                 int handled_now = 0;
 867
 868                 handled_now += omap1_dma_handle_ch(ch);
 869                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 870                         handled_now += omap1_dma_handle_ch(ch + 6);
 871                 if (!handled_now)
 872                         break;
 873                 handled += handled_now;
 874         }
 875
 876         return handled ? IRQ_HANDLED : IRQ_NONE;
 877 }
 878
 879 #else
 880 #define omap1_dma_irq_handler   NULL
 881 #endif
 882
 883 #ifdef CONFIG_ARCH_OMAP2
 884
 885 static int omap2_dma_handle_ch(int ch)
 886 {
 887         u32 status = OMAP_DMA_CSR_REG(ch);
 888         u32 val;
 889
 890         if (!status)
 891                 return 0;
 892         if (unlikely(dma_chan[ch].dev_id == -1))
 893                 return 0;
 894         if (unlikely(status & OMAP_DMA_DROP_IRQ))
 895                 printk(KERN_INFO
 896                        "DMA synchronization event drop occurred with device "
 897                        "%d\n", dma_chan[ch].dev_id);
 898         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
 899                 printk(KERN_INFO "DMA transaction error with device %d\n",
 900                        dma_chan[ch].dev_id);
 901         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
 902                 printk(KERN_INFO "DMA secure error with device %d\n",
 903                        dma_chan[ch].dev_id);
 904         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
 905                 printk(KERN_INFO "DMA misaligned error with device %d\n",
 906                        dma_chan[ch].dev_id);
 907
 908         OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
 909
 910         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 911         /* ch in this function is from 0-31 while in register it is 1-32 */
 912         val = 1 << (ch);
 913         omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 914
 915         if (likely(dma_chan[ch].callback != NULL))
 916                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 917
 918         return 0;
 919 }
 920
 921 /* STATUS register count is from 1-32 while our is 0-31 */
 922 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
 923                                          struct pt_regs *regs)
 924 {
 925         u32 val;
 926         int i;
 927
 928         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 929
 930         for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
 931                 int active = val & (1 << (i - 1));
 932                 if (active)
 933                         omap2_dma_handle_ch(i - 1);
 934         }
 935
 936         return IRQ_HANDLED;
 937 }
 938
 939 static struct irqaction omap24xx_dma_irq = {
 940         .name = "DMA",
 941         .handler = omap2_dma_irq_handler,
 942         .flags = IRQF_DISABLED
 943 };
 944
 945 #else
 946 static struct irqaction omap24xx_dma_irq;
 947 #endif
 948
 949 /*----------------------------------------------------------------------------*/
 950
 951 static struct lcd_dma_info {
 952         spinlock_t lock;
 953         int reserved;
 954         void (* callback)(u16 status, void *data);
 955         void *cb_data;
 956
 957         int active;
 958         unsigned long addr, size;
 959         int rotate, data_type, xres, yres;
 960         int vxres;
 961         int mirror;
 962         int xscale, yscale;
 963         int ext_ctrl;
 964         int src_port;
 965         int single_transfer;
 966 } lcd_dma;
 967
 968 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 969                          int data_type)
 970 {
 971         lcd_dma.addr = addr;
 972         lcd_dma.data_type = data_type;
 973         lcd_dma.xres = fb_xres;
 974         lcd_dma.yres = fb_yres;
 975 }
 976
 977 void omap_set_lcd_dma_src_port(int port)
 978 {
 979         lcd_dma.src_port = port;
 980 }
 981
 982 void omap_set_lcd_dma_ext_controller(int external)
 983 {
 984         lcd_dma.ext_ctrl = external;
 985 }
 986
 987 void omap_set_lcd_dma_single_transfer(int single)
 988 {
 989         lcd_dma.single_transfer = single;
 990 }
 991
 992
 993 void omap_set_lcd_dma_b1_rotation(int rotate)
 994 {
 995         if (omap_dma_in_1510_mode()) {
 996                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 997                 BUG();
 998                 return;
 999         }
1000         lcd_dma.rotate = rotate;
1001 }
1002
1003 void omap_set_lcd_dma_b1_mirror(int mirror)
1004 {
1005         if (omap_dma_in_1510_mode()) {
1006                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1007                 BUG();
1008         }
1009         lcd_dma.mirror = mirror;
1010 }
1011
1012 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1013 {
1014         if (omap_dma_in_1510_mode()) {
1015                 printk(KERN_ERR "DMA virtual resulotion is not supported "
1016                                 "in 1510 mode\n");
1017                 BUG();
1018         }
1019         lcd_dma.vxres = vxres;
1020 }
1021
1022 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1023 {
1024         if (omap_dma_in_1510_mode()) {
1025                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1026                 BUG();
1027         }
1028         lcd_dma.xscale = xscale;
1029         lcd_dma.yscale = yscale;
1030 }
1031
1032 static void set_b1_regs(void)
1033 {
1034         unsigned long top, bottom;
1035         int es;
1036         u16 w;
1037         unsigned long en, fn;
1038         long ei, fi;
1039         unsigned long vxres;
1040         unsigned int xscale, yscale;
1041
1042         switch (lcd_dma.data_type) {
1043         case OMAP_DMA_DATA_TYPE_S8:
1044                 es = 1;
1045                 break;
1046         case OMAP_DMA_DATA_TYPE_S16:
1047                 es = 2;
1048                 break;
1049         case OMAP_DMA_DATA_TYPE_S32:
1050                 es = 4;
1051                 break;
1052         default:
1053                 BUG();
1054                 return;
1055         }
1056
1057         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1058         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1059         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1060         BUG_ON(vxres < lcd_dma.xres);
1061 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1062 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1063         switch (lcd_dma.rotate) {
1064         case 0:
1065                 if (!lcd_dma.mirror) {
1066                         top = PIXADDR(0, 0);
1067                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1068                         /* 1510 DMA requires the bottom address to be 2 more
1069                          * than the actual last memory access location. */
1070                         if (omap_dma_in_1510_mode() &&
1071                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1072                                 bottom += 2;
1073                         ei = PIXSTEP(0, 0, 1, 0);
1074                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1075                 } else {
1076                         top = PIXADDR(lcd_dma.xres - 1, 0);
1077                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1078                         ei = PIXSTEP(1, 0, 0, 0);
1079                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1080                 }
1081                 en = lcd_dma.xres;
1082                 fn = lcd_dma.yres;
1083                 break;
1084         case 90:
1085                 if (!lcd_dma.mirror) {
1086                         top = PIXADDR(0, lcd_dma.yres - 1);
1087                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1088                         ei = PIXSTEP(0, 1, 0, 0);
1089                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1090                 } else {
1091                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1092                         bottom = PIXADDR(0, 0);
1093                         ei = PIXSTEP(0, 1, 0, 0);
1094                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1095                 }
1096                 en = lcd_dma.yres;
1097                 fn = lcd_dma.xres;
1098                 break;
1099         case 180:
1100                 if (!lcd_dma.mirror) {
1101                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1102                         bottom = PIXADDR(0, 0);
1103                         ei = PIXSTEP(1, 0, 0, 0);
1104                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1105                 } else {
1106                         top = PIXADDR(0, lcd_dma.yres - 1);
1107                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1108                         ei = PIXSTEP(0, 0, 1, 0);
1109                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1110                 }
1111                 en = lcd_dma.xres;
1112                 fn = lcd_dma.yres;
1113                 break;
1114         case 270:
1115                 if (!lcd_dma.mirror) {
1116                         top = PIXADDR(lcd_dma.xres - 1, 0);
1117                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1118                         ei = PIXSTEP(0, 0, 0, 1);
1119                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1120                 } else {
1121                         top = PIXADDR(0, 0);
1122                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1123                         ei = PIXSTEP(0, 0, 0, 1);
1124                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1125                 }
1126                 en = lcd_dma.yres;
1127                 fn = lcd_dma.xres;
1128                 break;
1129         default:
1130                 BUG();
1131                 return; /* Supress warning about uninitialized vars */
1132         }
1133
1134         if (omap_dma_in_1510_mode()) {
1135                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1136                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1137                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1138                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1139
1140                 return;
1141         }
1142
1143         /* 1610 regs */
1144         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1145         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1146         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1147         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1148
1149         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1150         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1151
1152         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1153         w &= ~0x03;
1154         w |= lcd_dma.data_type;
1155         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1156
1157         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1158         /* Always set the source port as SDRAM for now*/
1159         w &= ~(0x03 << 6);
1160         if (lcd_dma.callback != NULL)
1161                 w |= 1 << 1;            /* Block interrupt enable */
1162         else
1163                 w &= ~(1 << 1);
1164         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1165
1166         if (!(lcd_dma.rotate || lcd_dma.mirror ||
1167               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1168                 return;
1169
1170         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1171         /* Set the double-indexed addressing mode */
1172         w |= (0x03 << 12);
1173         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1174
1175         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1176         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1177         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1178 }
1179
1180 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1181                                        struct pt_regs *regs)
1182 {
1183         u16 w;
1184
1185         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1186         if (unlikely(!(w & (1 << 3)))) {
1187                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1188                 return IRQ_NONE;
1189         }
1190         /* Ack the IRQ */
1191         w |= (1 << 3);
1192         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1193         lcd_dma.active = 0;
1194         if (lcd_dma.callback != NULL)
1195                 lcd_dma.callback(w, lcd_dma.cb_data);
1196
1197         return IRQ_HANDLED;
1198 }
1199
1200 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1201                          void *data)
1202 {
1203         spin_lock_irq(&lcd_dma.lock);
1204         if (lcd_dma.reserved) {
1205                 spin_unlock_irq(&lcd_dma.lock);
1206                 printk(KERN_ERR "LCD DMA channel already reserved\n");
1207                 BUG();
1208                 return -EBUSY;
1209         }
1210         lcd_dma.reserved = 1;
1211         spin_unlock_irq(&lcd_dma.lock);
1212         lcd_dma.callback = callback;
1213         lcd_dma.cb_data = data;
1214         lcd_dma.active = 0;
1215         lcd_dma.single_transfer = 0;
1216         lcd_dma.rotate = 0;
1217         lcd_dma.vxres = 0;
1218         lcd_dma.mirror = 0;
1219         lcd_dma.xscale = 0;
1220         lcd_dma.yscale = 0;
1221         lcd_dma.ext_ctrl = 0;
1222         lcd_dma.src_port = 0;
1223
1224         return 0;
1225 }
1226
1227 void omap_free_lcd_dma(void)
1228 {
1229         spin_lock(&lcd_dma.lock);
1230         if (!lcd_dma.reserved) {
1231                 spin_unlock(&lcd_dma.lock);
1232                 printk(KERN_ERR "LCD DMA is not reserved\n");
1233                 BUG();
1234                 return;
1235         }
1236         if (!enable_1510_mode)
1237                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1238                             OMAP1610_DMA_LCD_CCR);
1239         lcd_dma.reserved = 0;
1240         spin_unlock(&lcd_dma.lock);
1241 }
1242
1243 void omap_enable_lcd_dma(void)
1244 {
1245         u16 w;
1246
1247         /* Set the Enable bit only if an external controller is
1248          * connected. Otherwise the OMAP internal controller will
1249          * start the transfer when it gets enabled.
1250          */
1251         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1252                 return;
1253
1254         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1255         w |= 1 << 8;
1256         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1257
1258         lcd_dma.active = 1;
1259
1260         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1261         w |= 1 << 7;
1262         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1263 }
1264
1265 void omap_setup_lcd_dma(void)
1266 {
1267         BUG_ON(lcd_dma.active);
1268         if (!enable_1510_mode) {
1269                 /* Set some reasonable defaults */
1270                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1271                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1272                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1273         }
1274         set_b1_regs();
1275         if (!enable_1510_mode) {
1276                 u16 w;
1277
1278                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1279                 /* If DMA was already active set the end_prog bit to have
1280                  * the programmed register set loaded into the active
1281                  * register set.
1282                  */
1283                 w |= 1 << 11;           /* End_prog */
1284                 if (!lcd_dma.single_transfer)
1285                         w |= (3 << 8);  /* Auto_init, repeat */
1286                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1287         }
1288 }
1289
1290 void omap_stop_lcd_dma(void)
1291 {
1292         u16 w;
1293
1294         lcd_dma.active = 0;
1295         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1296                 return;
1297
1298         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1299         w &= ~(1 << 7);
1300         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1301
1302         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1303         w &= ~(1 << 8);
1304         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1305 }
1306
1307 int omap_lcd_dma_ext_running(void)
1308 {
1309         return lcd_dma.ext_ctrl && lcd_dma.active;
1310 }
1311
1312 /*----------------------------------------------------------------------------*/
1313
1314 static int __init omap_init_dma(void)
1315 {
1316         int ch, r;
1317
1318         if (cpu_is_omap15xx()) {
1319                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1320                 dma_chan_count = 9;
1321                 enable_1510_mode = 1;
1322         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1323                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1324                        omap_readw(OMAP_DMA_HW_ID));
1325                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1326                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1327                        omap_readw(OMAP_DMA_CAPS_0_L),
1328                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1329                        omap_readw(OMAP_DMA_CAPS_1_L),
1330                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1331                        omap_readw(OMAP_DMA_CAPS_4));
1332                 if (!enable_1510_mode) {
1333                         u16 w;
1334
1335                         /* Disable OMAP 3.0/3.1 compatibility mode. */
1336                         w = omap_readw(OMAP_DMA_GSCR);
1337                         w |= 1 << 3;
1338                         omap_writew(w, OMAP_DMA_GSCR);
1339                         dma_chan_count = 16;
1340                 } else
1341                         dma_chan_count = 9;
1342         } else if (cpu_is_omap24xx()) {
1343                 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1344                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1345                        revision >> 4, revision & 0xf);
1346                 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1347         } else {
1348                 dma_chan_count = 0;
1349                 return 0;
1350         }
1351
1352         memset(&lcd_dma, 0, sizeof(lcd_dma));
1353         spin_lock_init(&lcd_dma.lock);
1354         spin_lock_init(&dma_chan_lock);
1355         memset(&dma_chan, 0, sizeof(dma_chan));
1356
1357         for (ch = 0; ch < dma_chan_count; ch++) {
1358                 omap_clear_dma(ch);
1359                 dma_chan[ch].dev_id = -1;
1360                 dma_chan[ch].next_lch = -1;
1361
1362                 if (ch >= 6 && enable_1510_mode)
1363                         continue;
1364
1365                 if (cpu_class_is_omap1()) {
1366                         /* request_irq() doesn't like dev_id (ie. ch) being
1367                          * zero, so we have to kludge around this. */
1368                         r = request_irq(omap1_dma_irq[ch],
1369                                         omap1_dma_irq_handler, 0, "DMA",
1370                                         (void *) (ch + 1));
1371                         if (r != 0) {
1372                                 int i;
1373
1374                                 printk(KERN_ERR "unable to request IRQ %d "
1375                                        "for DMA (error %d)\n",
1376                                        omap1_dma_irq[ch], r);
1377                                 for (i = 0; i < ch; i++)
1378                                         free_irq(omap1_dma_irq[i],
1379                                                  (void *) (i + 1));
1380                                 return r;
1381                         }
1382                 }
1383         }
1384
1385         if (cpu_is_omap24xx())
1386                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1387
1388         /* FIXME: Update LCD DMA to work on 24xx */
1389         if (cpu_class_is_omap1()) {
1390                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1391                                 "LCD DMA", NULL);
1392                 if (r != 0) {
1393                         int i;
1394
1395                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
1396                                "(error %d)\n", r);
1397                         for (i = 0; i < dma_chan_count; i++)
1398                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1399                         return r;
1400                 }
1401         }
1402
1403         return 0;
1404 }
1405
1406 arch_initcall(omap_init_dma);
1407
1408 EXPORT_SYMBOL(omap_get_dma_src_pos);
1409 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1410 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1411 EXPORT_SYMBOL(omap_clear_dma);
1412 EXPORT_SYMBOL(omap_set_dma_priority);
1413 EXPORT_SYMBOL(omap_request_dma);
1414 EXPORT_SYMBOL(omap_free_dma);
1415 EXPORT_SYMBOL(omap_start_dma);
1416 EXPORT_SYMBOL(omap_stop_dma);
1417 EXPORT_SYMBOL(omap_enable_dma_irq);
1418 EXPORT_SYMBOL(omap_disable_dma_irq);
1419
1420 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1421 EXPORT_SYMBOL(omap_set_dma_color_mode);
1422
1423 EXPORT_SYMBOL(omap_set_dma_src_params);
1424 EXPORT_SYMBOL(omap_set_dma_src_index);
1425 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1426 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1427
1428 EXPORT_SYMBOL(omap_set_dma_dest_params);
1429 EXPORT_SYMBOL(omap_set_dma_dest_index);
1430 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1431 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1432
1433 EXPORT_SYMBOL(omap_set_dma_params);
1434
1435 EXPORT_SYMBOL(omap_dma_link_lch);
1436 EXPORT_SYMBOL(omap_dma_unlink_lch);
1437
1438 EXPORT_SYMBOL(omap_request_lcd_dma);
1439 EXPORT_SYMBOL(omap_free_lcd_dma);
1440 EXPORT_SYMBOL(omap_enable_lcd_dma);
1441 EXPORT_SYMBOL(omap_setup_lcd_dma);
1442 EXPORT_SYMBOL(omap_stop_lcd_dma);
1443 EXPORT_SYMBOL(omap_lcd_dma_ext_running);
1444 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1445 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1446 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1447 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1448 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1449 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1450 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1451