arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <mach/dma.h>
  36
  37 #include <mach/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP_DMA_CCR_EN                 (1 << 7)
  51 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  52
  53 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  54
  55 static int enable_1510_mode;
  56
  57 struct omap_dma_lch {
  58         int next_lch;
  59         int dev_id;
  60         u16 saved_csr;
  61         u16 enabled_irqs;
  62         const char *dev_name;
  63         void (*callback)(int lch, u16 ch_status, void *data);
  64         void *data;
  65
  66 #ifndef CONFIG_ARCH_OMAP1
  67         /* required for Dynamic chaining */
  68         int prev_linked_ch;
  69         int next_linked_ch;
  70         int state;
  71         int chain_id;
  72
  73         int status;
  74 #endif
  75         long flags;
  76 };
  77
  78 struct dma_link_info {
  79         int *linked_dmach_q;
  80         int no_of_lchs_linked;
  81
  82         int q_count;
  83         int q_tail;
  84         int q_head;
  85
  86         int chain_state;
  87         int chain_mode;
  88
  89 };
  90
  91 static struct dma_link_info *dma_linked_lch;
  92
  93 #ifndef CONFIG_ARCH_OMAP1
  94
  95 /* Chain handling macros */
  96 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  97         do {                                                            \
  98                 dma_linked_lch[chain_id].q_head =                       \
  99                 dma_linked_lch[chain_id].q_tail =                       \
 100                 dma_linked_lch[chain_id].q_count = 0;                   \
 101         } while (0)
 102 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 103                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 104                 dma_linked_lch[chain_id].q_count)
 105 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 106         do {                                                            \
 107                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 108                 dma_linked_lch[chain_id].q_count)                       \
 109         } while (0)
 110 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 111                 (0 == dma_linked_lch[chain_id].q_count)
 112 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 113         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 114 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 115         do {                                                            \
 116                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 117                 dma_linked_lch[chain_id].q_count--;                     \
 118         } while (0)
 119
 120 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 121         do {                                                            \
 122                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 123                 dma_linked_lch[chain_id].q_count++; \
 124         } while (0)
 125 #endif
 126
 127 static int dma_lch_count;
 128 static int dma_chan_count;
 129 static int omap_dma_reserve_channels;
 130
 131 static spinlock_t dma_chan_lock;
 132 static struct omap_dma_lch *dma_chan;
 133 static void __iomem *omap_dma_base;
 134
 135 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 136         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 137         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 138         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 139         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 140         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 141 };
 142
 143 static inline void disable_lnk(int lch);
 144 static void omap_disable_channel_irq(int lch);
 145 static inline void omap_enable_channel_irq(int lch);
 146
 147 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 148                                                 __func__);
 149
 150 #define dma_read(reg)                                                   \
 151 ({                                                                      \
 152         u32 __val;                                                      \
 153         if (cpu_class_is_omap1())                                       \
 154                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 155         else                                                            \
 156                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 157         __val;                                                          \
 158 })
 159
 160 #define dma_write(val, reg)                                             \
 161 ({                                                                      \
 162         if (cpu_class_is_omap1())                                       \
 163                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 164         else                                                            \
 165                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 166 })
 167
 168 #ifdef CONFIG_ARCH_OMAP15XX
 169 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 170 int omap_dma_in_1510_mode(void)
 171 {
 172         return enable_1510_mode;
 173 }
 174 #else
 175 #define omap_dma_in_1510_mode()         0
 176 #endif
 177
 178 #ifdef CONFIG_ARCH_OMAP1
 179 static inline int get_gdma_dev(int req)
 180 {
 181         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 182         int shift = ((req - 1) % 5) * 6;
 183
 184         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 185 }
 186
 187 static inline void set_gdma_dev(int req, int dev)
 188 {
 189         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 190         int shift = ((req - 1) % 5) * 6;
 191         u32 l;
 192
 193         l = omap_readl(reg);
 194         l &= ~(0x3f << shift);
 195         l |= (dev - 1) << shift;
 196         omap_writel(l, reg);
 197 }
 198 #else
 199 #define set_gdma_dev(req, dev)  do {} while (0)
 200 #endif
 201
 202 /* Omap1 only */
 203 static void clear_lch_regs(int lch)
 204 {
 205         int i;
 206         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 207
 208         for (i = 0; i < 0x2c; i += 2)
 209                 __raw_writew(0, lch_base + i);
 210 }
 211
 212 void omap_set_dma_priority(int lch, int dst_port, int priority)
 213 {
 214         unsigned long reg;
 215         u32 l;
 216
 217         if (cpu_class_is_omap1()) {
 218                 switch (dst_port) {
 219                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 220                         reg = OMAP_TC_OCPT1_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 223                         reg = OMAP_TC_OCPT2_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 226                         reg = OMAP_TC_EMIFF_PRIOR;
 227                         break;
 228                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 229                         reg = OMAP_TC_EMIFS_PRIOR;
 230                         break;
 231                 default:
 232                         BUG();
 233                         return;
 234                 }
 235                 l = omap_readl(reg);
 236                 l &= ~(0xf << 8);
 237                 l |= (priority & 0xf) << 8;
 238                 omap_writel(l, reg);
 239         }
 240
 241         if (cpu_class_is_omap2()) {
 242                 u32 ccr;
 243
 244                 ccr = dma_read(CCR(lch));
 245                 if (priority)
 246                         ccr |= (1 << 6);
 247                 else
 248                         ccr &= ~(1 << 6);
 249                 dma_write(ccr, CCR(lch));
 250         }
 251 }
 252 EXPORT_SYMBOL(omap_set_dma_priority);
 253
 254 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 255                                   int frame_count, int sync_mode,
 256                                   int dma_trigger, int src_or_dst_synch)
 257 {
 258         u32 l;
 259
 260         l = dma_read(CSDP(lch));
 261         l &= ~0x03;
 262         l |= data_type;
 263         dma_write(l, CSDP(lch));
 264
 265         if (cpu_class_is_omap1()) {
 266                 u16 ccr;
 267
 268                 ccr = dma_read(CCR(lch));
 269                 ccr &= ~(1 << 5);
 270                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 271                         ccr |= 1 << 5;
 272                 dma_write(ccr, CCR(lch));
 273
 274                 ccr = dma_read(CCR2(lch));
 275                 ccr &= ~(1 << 2);
 276                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 277                         ccr |= 1 << 2;
 278                 dma_write(ccr, CCR2(lch));
 279         }
 280
 281         if (cpu_class_is_omap2() && dma_trigger) {
 282                 u32 val;
 283
 284                 val = dma_read(CCR(lch));
 285
 286                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 287                 val &= ~((3 << 19) | 0x1f);
 288                 val |= (dma_trigger & ~0x1f) << 14;
 289                 val |= dma_trigger & 0x1f;
 290
 291                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 292                         val |= 1 << 5;
 293                 else
 294                         val &= ~(1 << 5);
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 297                         val |= 1 << 18;
 298                 else
 299                         val &= ~(1 << 18);
 300
 301                 if (src_or_dst_synch)
 302                         val |= 1 << 24;         /* source synch */
 303                 else
 304                         val &= ~(1 << 24);      /* dest synch */
 305
 306                 dma_write(val, CCR(lch));
 307         }
 308
 309         dma_write(elem_count, CEN(lch));
 310         dma_write(frame_count, CFN(lch));
 311 }
 312 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 313
 314 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 315 {
 316         BUG_ON(omap_dma_in_1510_mode());
 317
 318         if (cpu_class_is_omap1()) {
 319                 u16 w;
 320
 321                 w = dma_read(CCR2(lch));
 322                 w &= ~0x03;
 323
 324                 switch (mode) {
 325                 case OMAP_DMA_CONSTANT_FILL:
 326                         w |= 0x01;
 327                         break;
 328                 case OMAP_DMA_TRANSPARENT_COPY:
 329                         w |= 0x02;
 330                         break;
 331                 case OMAP_DMA_COLOR_DIS:
 332                         break;
 333                 default:
 334                         BUG();
 335                 }
 336                 dma_write(w, CCR2(lch));
 337
 338                 w = dma_read(LCH_CTRL(lch));
 339                 w &= ~0x0f;
 340                 /* Default is channel type 2D */
 341                 if (mode) {
 342                         dma_write((u16)color, COLOR_L(lch));
 343                         dma_write((u16)(color >> 16), COLOR_U(lch));
 344                         w |= 1;         /* Channel type G */
 345                 }
 346                 dma_write(w, LCH_CTRL(lch));
 347         }
 348
 349         if (cpu_class_is_omap2()) {
 350                 u32 val;
 351
 352                 val = dma_read(CCR(lch));
 353                 val &= ~((1 << 17) | (1 << 16));
 354
 355                 switch (mode) {
 356                 case OMAP_DMA_CONSTANT_FILL:
 357                         val |= 1 << 16;
 358                         break;
 359                 case OMAP_DMA_TRANSPARENT_COPY:
 360                         val |= 1 << 17;
 361                         break;
 362                 case OMAP_DMA_COLOR_DIS:
 363                         break;
 364                 default:
 365                         BUG();
 366                 }
 367                 dma_write(val, CCR(lch));
 368
 369                 color &= 0xffffff;
 370                 dma_write(color, COLOR(lch));
 371         }
 372 }
 373 EXPORT_SYMBOL(omap_set_dma_color_mode);
 374
 375 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 376 {
 377         if (cpu_class_is_omap2()) {
 378                 u32 csdp;
 379
 380                 csdp = dma_read(CSDP(lch));
 381                 csdp &= ~(0x3 << 16);
 382                 csdp |= (mode << 16);
 383                 dma_write(csdp, CSDP(lch));
 384         }
 385 }
 386 EXPORT_SYMBOL(omap_set_dma_write_mode);
 387
 388 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 389 {
 390         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 391                 u32 l;
 392
 393                 l = dma_read(LCH_CTRL(lch));
 394                 l &= ~0x7;
 395                 l |= mode;
 396                 dma_write(l, LCH_CTRL(lch));
 397         }
 398 }
 399 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 400
 401 /* Note that src_port is only for omap1 */
 402 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 403                              unsigned long src_start,
 404                              int src_ei, int src_fi)
 405 {
 406         u32 l;
 407
 408         if (cpu_class_is_omap1()) {
 409                 u16 w;
 410
 411                 w = dma_read(CSDP(lch));
 412                 w &= ~(0x1f << 2);
 413                 w |= src_port << 2;
 414                 dma_write(w, CSDP(lch));
 415         }
 416
 417         l = dma_read(CCR(lch));
 418         l &= ~(0x03 << 12);
 419         l |= src_amode << 12;
 420         dma_write(l, CCR(lch));
 421
 422         if (cpu_class_is_omap1()) {
 423                 dma_write(src_start >> 16, CSSA_U(lch));
 424                 dma_write((u16)src_start, CSSA_L(lch));
 425         }
 426
 427         if (cpu_class_is_omap2())
 428                 dma_write(src_start, CSSA(lch));
 429
 430         dma_write(src_ei, CSEI(lch));
 431         dma_write(src_fi, CSFI(lch));
 432 }
 433 EXPORT_SYMBOL(omap_set_dma_src_params);
 434
 435 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 436 {
 437         omap_set_dma_transfer_params(lch, params->data_type,
 438                                      params->elem_count, params->frame_count,
 439                                      params->sync_mode, params->trigger,
 440                                      params->src_or_dst_synch);
 441         omap_set_dma_src_params(lch, params->src_port,
 442                                 params->src_amode, params->src_start,
 443                                 params->src_ei, params->src_fi);
 444
 445         omap_set_dma_dest_params(lch, params->dst_port,
 446                                  params->dst_amode, params->dst_start,
 447                                  params->dst_ei, params->dst_fi);
 448         if (params->read_prio || params->write_prio)
 449                 omap_dma_set_prio_lch(lch, params->read_prio,
 450                                       params->write_prio);
 451 }
 452 EXPORT_SYMBOL(omap_set_dma_params);
 453
 454 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 455 {
 456         if (cpu_class_is_omap2())
 457                 return;
 458
 459         dma_write(eidx, CSEI(lch));
 460         dma_write(fidx, CSFI(lch));
 461 }
 462 EXPORT_SYMBOL(omap_set_dma_src_index);
 463
 464 void omap_set_dma_src_data_pack(int lch, int enable)
 465 {
 466         u32 l;
 467
 468         l = dma_read(CSDP(lch));
 469         l &= ~(1 << 6);
 470         if (enable)
 471                 l |= (1 << 6);
 472         dma_write(l, CSDP(lch));
 473 }
 474 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 475
 476 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 477 {
 478         unsigned int burst = 0;
 479         u32 l;
 480
 481         l = dma_read(CSDP(lch));
 482         l &= ~(0x03 << 7);
 483
 484         switch (burst_mode) {
 485         case OMAP_DMA_DATA_BURST_DIS:
 486                 break;
 487         case OMAP_DMA_DATA_BURST_4:
 488                 if (cpu_class_is_omap2())
 489                         burst = 0x1;
 490                 else
 491                         burst = 0x2;
 492                 break;
 493         case OMAP_DMA_DATA_BURST_8:
 494                 if (cpu_class_is_omap2()) {
 495                         burst = 0x2;
 496                         break;
 497                 }
 498                 /* not supported by current hardware on OMAP1
 499                  * w |= (0x03 << 7);
 500                  * fall through
 501                  */
 502         case OMAP_DMA_DATA_BURST_16:
 503                 if (cpu_class_is_omap2()) {
 504                         burst = 0x3;
 505                         break;
 506                 }
 507                 /* OMAP1 don't support burst 16
 508                  * fall through
 509                  */
 510         default:
 511                 BUG();
 512         }
 513
 514         l |= (burst << 7);
 515         dma_write(l, CSDP(lch));
 516 }
 517 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 518
 519 /* Note that dest_port is only for OMAP1 */
 520 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 521                               unsigned long dest_start,
 522                               int dst_ei, int dst_fi)
 523 {
 524         u32 l;
 525
 526         if (cpu_class_is_omap1()) {
 527                 l = dma_read(CSDP(lch));
 528                 l &= ~(0x1f << 9);
 529                 l |= dest_port << 9;
 530                 dma_write(l, CSDP(lch));
 531         }
 532
 533         l = dma_read(CCR(lch));
 534         l &= ~(0x03 << 14);
 535         l |= dest_amode << 14;
 536         dma_write(l, CCR(lch));
 537
 538         if (cpu_class_is_omap1()) {
 539                 dma_write(dest_start >> 16, CDSA_U(lch));
 540                 dma_write(dest_start, CDSA_L(lch));
 541         }
 542
 543         if (cpu_class_is_omap2())
 544                 dma_write(dest_start, CDSA(lch));
 545
 546         dma_write(dst_ei, CDEI(lch));
 547         dma_write(dst_fi, CDFI(lch));
 548 }
 549 EXPORT_SYMBOL(omap_set_dma_dest_params);
 550
 551 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 552 {
 553         if (cpu_class_is_omap2())
 554                 return;
 555
 556         dma_write(eidx, CDEI(lch));
 557         dma_write(fidx, CDFI(lch));
 558 }
 559 EXPORT_SYMBOL(omap_set_dma_dest_index);
 560
 561 void omap_set_dma_dest_data_pack(int lch, int enable)
 562 {
 563         u32 l;
 564
 565         l = dma_read(CSDP(lch));
 566         l &= ~(1 << 13);
 567         if (enable)
 568                 l |= 1 << 13;
 569         dma_write(l, CSDP(lch));
 570 }
 571 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 572
 573 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 574 {
 575         unsigned int burst = 0;
 576         u32 l;
 577
 578         l = dma_read(CSDP(lch));
 579         l &= ~(0x03 << 14);
 580
 581         switch (burst_mode) {
 582         case OMAP_DMA_DATA_BURST_DIS:
 583                 break;
 584         case OMAP_DMA_DATA_BURST_4:
 585                 if (cpu_class_is_omap2())
 586                         burst = 0x1;
 587                 else
 588                         burst = 0x2;
 589                 break;
 590         case OMAP_DMA_DATA_BURST_8:
 591                 if (cpu_class_is_omap2())
 592                         burst = 0x2;
 593                 else
 594                         burst = 0x3;
 595                 break;
 596         case OMAP_DMA_DATA_BURST_16:
 597                 if (cpu_class_is_omap2()) {
 598                         burst = 0x3;
 599                         break;
 600                 }
 601                 /* OMAP1 don't support burst 16
 602                  * fall through
 603                  */
 604         default:
 605                 printk(KERN_ERR "Invalid DMA burst mode\n");
 606                 BUG();
 607                 return;
 608         }
 609         l |= (burst << 14);
 610         dma_write(l, CSDP(lch));
 611 }
 612 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 613
 614 static inline void omap_enable_channel_irq(int lch)
 615 {
 616         u32 status;
 617
 618         /* Clear CSR */
 619         if (cpu_class_is_omap1())
 620                 status = dma_read(CSR(lch));
 621         else if (cpu_class_is_omap2())
 622                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 623
 624         /* Enable some nice interrupts. */
 625         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 626 }
 627
 628 static void omap_disable_channel_irq(int lch)
 629 {
 630         if (cpu_class_is_omap2())
 631                 dma_write(0, CICR(lch));
 632 }
 633
 634 void omap_enable_dma_irq(int lch, u16 bits)
 635 {
 636         dma_chan[lch].enabled_irqs |= bits;
 637 }
 638 EXPORT_SYMBOL(omap_enable_dma_irq);
 639
 640 void omap_disable_dma_irq(int lch, u16 bits)
 641 {
 642         dma_chan[lch].enabled_irqs &= ~bits;
 643 }
 644 EXPORT_SYMBOL(omap_disable_dma_irq);
 645
 646 static inline void enable_lnk(int lch)
 647 {
 648         u32 l;
 649
 650         l = dma_read(CLNK_CTRL(lch));
 651
 652         if (cpu_class_is_omap1())
 653                 l &= ~(1 << 14);
 654
 655         /* Set the ENABLE_LNK bits */
 656         if (dma_chan[lch].next_lch != -1)
 657                 l = dma_chan[lch].next_lch | (1 << 15);
 658
 659 #ifndef CONFIG_ARCH_OMAP1
 660         if (cpu_class_is_omap2())
 661                 if (dma_chan[lch].next_linked_ch != -1)
 662                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 663 #endif
 664
 665         dma_write(l, CLNK_CTRL(lch));
 666 }
 667
 668 static inline void disable_lnk(int lch)
 669 {
 670         u32 l;
 671
 672         l = dma_read(CLNK_CTRL(lch));
 673
 674         /* Disable interrupts */
 675         if (cpu_class_is_omap1()) {
 676                 dma_write(0, CICR(lch));
 677                 /* Set the STOP_LNK bit */
 678                 l |= 1 << 14;
 679         }
 680
 681         if (cpu_class_is_omap2()) {
 682                 omap_disable_channel_irq(lch);
 683                 /* Clear the ENABLE_LNK bit */
 684                 l &= ~(1 << 15);
 685         }
 686
 687         dma_write(l, CLNK_CTRL(lch));
 688         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 689 }
 690
 691 static inline void omap2_enable_irq_lch(int lch)
 692 {
 693         u32 val;
 694         unsigned long flags;
 695
 696         if (!cpu_class_is_omap2())
 697                 return;
 698
 699         spin_lock_irqsave(&dma_chan_lock, flags);
 700         val = dma_read(IRQENABLE_L0);
 701         val |= 1 << lch;
 702         dma_write(val, IRQENABLE_L0);
 703         spin_unlock_irqrestore(&dma_chan_lock, flags);
 704 }
 705
 706 int omap_request_dma(int dev_id, const char *dev_name,
 707                      void (*callback)(int lch, u16 ch_status, void *data),
 708                      void *data, int *dma_ch_out)
 709 {
 710         int ch, free_ch = -1;
 711         unsigned long flags;
 712         struct omap_dma_lch *chan;
 713
 714         spin_lock_irqsave(&dma_chan_lock, flags);
 715         for (ch = 0; ch < dma_chan_count; ch++) {
 716                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 717                         free_ch = ch;
 718                         if (dev_id == 0)
 719                                 break;
 720                 }
 721         }
 722         if (free_ch == -1) {
 723                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 724                 return -EBUSY;
 725         }
 726         chan = dma_chan + free_ch;
 727         chan->dev_id = dev_id;
 728
 729         if (cpu_class_is_omap1())
 730                 clear_lch_regs(free_ch);
 731
 732         if (cpu_class_is_omap2())
 733                 omap_clear_dma(free_ch);
 734
 735         spin_unlock_irqrestore(&dma_chan_lock, flags);
 736
 737         chan->dev_name = dev_name;
 738         chan->callback = callback;
 739         chan->data = data;
 740         chan->flags = 0;
 741
 742 #ifndef CONFIG_ARCH_OMAP1
 743         if (cpu_class_is_omap2()) {
 744                 chan->chain_id = -1;
 745                 chan->next_linked_ch = -1;
 746         }
 747 #endif
 748
 749         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 750
 751         if (cpu_class_is_omap1())
 752                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 753         else if (cpu_class_is_omap2())
 754                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 755                         OMAP2_DMA_TRANS_ERR_IRQ;
 756
 757         if (cpu_is_omap16xx()) {
 758                 /* If the sync device is set, configure it dynamically. */
 759                 if (dev_id != 0) {
 760                         set_gdma_dev(free_ch + 1, dev_id);
 761                         dev_id = free_ch + 1;
 762                 }
 763                 /*
 764                  * Disable the 1510 compatibility mode and set the sync device
 765                  * id.
 766                  */
 767                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 768         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 769                 dma_write(dev_id, CCR(free_ch));
 770         }
 771
 772         if (cpu_class_is_omap2()) {
 773                 omap2_enable_irq_lch(free_ch);
 774                 omap_enable_channel_irq(free_ch);
 775                 /* Clear the CSR register and IRQ status register */
 776                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 777                 dma_write(1 << free_ch, IRQSTATUS_L0);
 778         }
 779
 780         *dma_ch_out = free_ch;
 781
 782         return 0;
 783 }
 784 EXPORT_SYMBOL(omap_request_dma);
 785
 786 void omap_free_dma(int lch)
 787 {
 788         unsigned long flags;
 789
 790         if (dma_chan[lch].dev_id == -1) {
 791                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 792                        lch);
 793                 return;
 794         }
 795
 796         if (cpu_class_is_omap1()) {
 797                 /* Disable all DMA interrupts for the channel. */
 798                 dma_write(0, CICR(lch));
 799                 /* Make sure the DMA transfer is stopped. */
 800                 dma_write(0, CCR(lch));
 801         }
 802
 803         if (cpu_class_is_omap2()) {
 804                 u32 val;
 805
 806                 spin_lock_irqsave(&dma_chan_lock, flags);
 807                 /* Disable interrupts */
 808                 val = dma_read(IRQENABLE_L0);
 809                 val &= ~(1 << lch);
 810                 dma_write(val, IRQENABLE_L0);
 811                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 812
 813                 /* Clear the CSR register and IRQ status register */
 814                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 815                 dma_write(1 << lch, IRQSTATUS_L0);
 816
 817                 /* Disable all DMA interrupts for the channel. */
 818                 dma_write(0, CICR(lch));
 819
 820                 /* Make sure the DMA transfer is stopped. */
 821                 dma_write(0, CCR(lch));
 822                 omap_clear_dma(lch);
 823         }
 824
 825         spin_lock_irqsave(&dma_chan_lock, flags);
 826         dma_chan[lch].dev_id = -1;
 827         dma_chan[lch].next_lch = -1;
 828         dma_chan[lch].callback = NULL;
 829         spin_unlock_irqrestore(&dma_chan_lock, flags);
 830 }
 831 EXPORT_SYMBOL(omap_free_dma);
 832
 833 /**
 834  * @brief omap_dma_set_global_params : Set global priority settings for dma
 835  *
 836  * @param arb_rate
 837  * @param max_fifo_depth
 838  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 839  *                                                 DMA_THREAD_RESERVE_ONET
 840  *                                                 DMA_THREAD_RESERVE_TWOT
 841  *                                                 DMA_THREAD_RESERVE_THREET
 842  */
 843 void
 844 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 845 {
 846         u32 reg;
 847
 848         if (!cpu_class_is_omap2()) {
 849                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 850                 return;
 851         }
 852
 853         if (max_fifo_depth == 0)
 854                 max_fifo_depth = 1;
 855         if (arb_rate == 0)
 856                 arb_rate = 1;
 857
 858         reg = 0xff & max_fifo_depth;
 859         reg |= (0x3 & tparams) << 12;
 860         reg |= (arb_rate & 0xff) << 16;
 861
 862         dma_write(reg, GCR);
 863 }
 864 EXPORT_SYMBOL(omap_dma_set_global_params);
 865
 866 /**
 867  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 868  *
 869  * @param lch
 870  * @param read_prio - Read priority
 871  * @param write_prio - Write priority
 872  * Both of the above can be set with one of the following values :
 873  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 874  */
 875 int
 876 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 877                       unsigned char write_prio)
 878 {
 879         u32 l;
 880
 881         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 882                 printk(KERN_ERR "Invalid channel id\n");
 883                 return -EINVAL;
 884         }
 885         l = dma_read(CCR(lch));
 886         l &= ~((1 << 6) | (1 << 26));
 887         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 888                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 889         else
 890                 l |= ((read_prio & 0x1) << 6);
 891
 892         dma_write(l, CCR(lch));
 893
 894         return 0;
 895 }
 896 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 897
 898 /*
 899  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 900  * through omap_start_dma(). Any buffers in flight are discarded.
 901  */
 902 void omap_clear_dma(int lch)
 903 {
 904         unsigned long flags;
 905
 906         local_irq_save(flags);
 907
 908         if (cpu_class_is_omap1()) {
 909                 u32 l;
 910
 911                 l = dma_read(CCR(lch));
 912                 l &= ~OMAP_DMA_CCR_EN;
 913                 dma_write(l, CCR(lch));
 914
 915                 /* Clear pending interrupts */
 916                 l = dma_read(CSR(lch));
 917         }
 918
 919         if (cpu_class_is_omap2()) {
 920                 int i;
 921                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 922                 for (i = 0; i < 0x44; i += 4)
 923                         __raw_writel(0, lch_base + i);
 924         }
 925
 926         local_irq_restore(flags);
 927 }
 928 EXPORT_SYMBOL(omap_clear_dma);
 929
 930 void omap_start_dma(int lch)
 931 {
 932         u32 l;
 933
 934         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 935                 int next_lch, cur_lch;
 936                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 937
 938                 dma_chan_link_map[lch] = 1;
 939                 /* Set the link register of the first channel */
 940                 enable_lnk(lch);
 941
 942                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 943                 cur_lch = dma_chan[lch].next_lch;
 944                 do {
 945                         next_lch = dma_chan[cur_lch].next_lch;
 946
 947                         /* The loop case: we've been here already */
 948                         if (dma_chan_link_map[cur_lch])
 949                                 break;
 950                         /* Mark the current channel */
 951                         dma_chan_link_map[cur_lch] = 1;
 952
 953                         enable_lnk(cur_lch);
 954                         omap_enable_channel_irq(cur_lch);
 955
 956                         cur_lch = next_lch;
 957                 } while (next_lch != -1);
 958         } else if (cpu_is_omap242x() ||
 959                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 960
 961                 /* Errata: Need to write lch even if not using chaining */
 962                 dma_write(lch, CLNK_CTRL(lch));
 963         }
 964
 965         omap_enable_channel_irq(lch);
 966
 967         l = dma_read(CCR(lch));
 968
 969         /*
 970          * Errata: On ES2.0 BUFFERING disable must be set.
 971          * This will always fail on ES1.0
 972          */
 973         if (cpu_is_omap24xx())
 974                 l |= OMAP_DMA_CCR_EN;
 975
 976         l |= OMAP_DMA_CCR_EN;
 977         dma_write(l, CCR(lch));
 978
 979         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 980 }
 981 EXPORT_SYMBOL(omap_start_dma);
 982
 983 void omap_stop_dma(int lch)
 984 {
 985         u32 l;
 986
 987         /* Disable all interrupts on the channel */
 988         if (cpu_class_is_omap1())
 989                 dma_write(0, CICR(lch));
 990
 991         l = dma_read(CCR(lch));
 992         l &= ~OMAP_DMA_CCR_EN;
 993         dma_write(l, CCR(lch));
 994
 995         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 996                 int next_lch, cur_lch = lch;
 997                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 998
 999                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1000                 do {
1001                         /* The loop case: we've been here already */
1002                         if (dma_chan_link_map[cur_lch])
1003                                 break;
1004                         /* Mark the current channel */
1005                         dma_chan_link_map[cur_lch] = 1;
1006
1007                         disable_lnk(cur_lch);
1008
1009                         next_lch = dma_chan[cur_lch].next_lch;
1010                         cur_lch = next_lch;
1011                 } while (next_lch != -1);
1012         }
1013
1014         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1015 }
1016 EXPORT_SYMBOL(omap_stop_dma);
1017
1018 /*
1019  * Allows changing the DMA callback function or data. This may be needed if
1020  * the driver shares a single DMA channel for multiple dma triggers.
1021  */
1022 int omap_set_dma_callback(int lch,
1023                           void (*callback)(int lch, u16 ch_status, void *data),
1024                           void *data)
1025 {
1026         unsigned long flags;
1027
1028         if (lch < 0)
1029                 return -ENODEV;
1030
1031         spin_lock_irqsave(&dma_chan_lock, flags);
1032         if (dma_chan[lch].dev_id == -1) {
1033                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1034                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1035                 return -EINVAL;
1036         }
1037         dma_chan[lch].callback = callback;
1038         dma_chan[lch].data = data;
1039         spin_unlock_irqrestore(&dma_chan_lock, flags);
1040
1041         return 0;
1042 }
1043 EXPORT_SYMBOL(omap_set_dma_callback);
1044
1045 /*
1046  * Returns current physical source address for the given DMA channel.
1047  * If the channel is running the caller must disable interrupts prior calling
1048  * this function and process the returned value before re-enabling interrupt to
1049  * prevent races with the interrupt handler. Note that in continuous mode there
1050  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1051  * in incorrect return value.
1052  */
1053 dma_addr_t omap_get_dma_src_pos(int lch)
1054 {
1055         dma_addr_t offset = 0;
1056
1057         if (cpu_is_omap15xx())
1058                 offset = dma_read(CPC(lch));
1059         else
1060                 offset = dma_read(CSAC(lch));
1061
1062         /*
1063          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064          * read before the DMA controller finished disabling the channel.
1065          */
1066         if (!cpu_is_omap15xx() && offset == 0)
1067                 offset = dma_read(CSAC(lch));
1068
1069         if (cpu_class_is_omap1())
1070                 offset |= (dma_read(CSSA_U(lch)) << 16);
1071
1072         return offset;
1073 }
1074 EXPORT_SYMBOL(omap_get_dma_src_pos);
1075
1076 /*
1077  * Returns current physical destination address for the given DMA channel.
1078  * If the channel is running the caller must disable interrupts prior calling
1079  * this function and process the returned value before re-enabling interrupt to
1080  * prevent races with the interrupt handler. Note that in continuous mode there
1081  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1082  * in incorrect return value.
1083  */
1084 dma_addr_t omap_get_dma_dst_pos(int lch)
1085 {
1086         dma_addr_t offset = 0;
1087
1088         if (cpu_is_omap15xx())
1089                 offset = dma_read(CPC(lch));
1090         else
1091                 offset = dma_read(CDAC(lch));
1092
1093         /*
1094          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1095          * read before the DMA controller finished disabling the channel.
1096          */
1097         if (!cpu_is_omap15xx() && offset == 0)
1098                 offset = dma_read(CDAC(lch));
1099
1100         if (cpu_class_is_omap1())
1101                 offset |= (dma_read(CDSA_U(lch)) << 16);
1102
1103         return offset;
1104 }
1105 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1106
1107 int omap_get_dma_active_status(int lch)
1108 {
1109         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1110 }
1111 EXPORT_SYMBOL(omap_get_dma_active_status);
1112
1113 int omap_dma_running(void)
1114 {
1115         int lch;
1116
1117         /*
1118          * On OMAP1510, internal LCD controller will start the transfer
1119          * when it gets enabled, so assume DMA running if LCD enabled.
1120          */
1121         if (cpu_is_omap1510())
1122                 if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
1123                         return 1;
1124
1125         /* Check if LCD DMA is running */
1126         if (cpu_is_omap16xx())
1127                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1128                         return 1;
1129
1130         for (lch = 0; lch < dma_chan_count; lch++)
1131                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1132                         return 1;
1133
1134         return 0;
1135 }
1136
1137 /*
1138  * lch_queue DMA will start right after lch_head one is finished.
1139  * For this DMA link to start, you still need to start (see omap_start_dma)
1140  * the first one. That will fire up the entire queue.
1141  */
1142 void omap_dma_link_lch(int lch_head, int lch_queue)
1143 {
1144         if (omap_dma_in_1510_mode()) {
1145                 if (lch_head == lch_queue) {
1146                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1147                                                                 CCR(lch_head));
1148                         return;
1149                 }
1150                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1151                 BUG();
1152                 return;
1153         }
1154
1155         if ((dma_chan[lch_head].dev_id == -1) ||
1156             (dma_chan[lch_queue].dev_id == -1)) {
1157                 printk(KERN_ERR "omap_dma: trying to link "
1158                        "non requested channels\n");
1159                 dump_stack();
1160         }
1161
1162         dma_chan[lch_head].next_lch = lch_queue;
1163 }
1164 EXPORT_SYMBOL(omap_dma_link_lch);
1165
1166 /*
1167  * Once the DMA queue is stopped, we can destroy it.
1168  */
1169 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1170 {
1171         if (omap_dma_in_1510_mode()) {
1172                 if (lch_head == lch_queue) {
1173                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1174                                                                 CCR(lch_head));
1175                         return;
1176                 }
1177                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1178                 BUG();
1179                 return;
1180         }
1181
1182         if (dma_chan[lch_head].next_lch != lch_queue ||
1183             dma_chan[lch_head].next_lch == -1) {
1184                 printk(KERN_ERR "omap_dma: trying to unlink "
1185                        "non linked channels\n");
1186                 dump_stack();
1187         }
1188
1189         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1190             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1191                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1192                        "before unlinking\n");
1193                 dump_stack();
1194         }
1195
1196         dma_chan[lch_head].next_lch = -1;
1197 }
1198 EXPORT_SYMBOL(omap_dma_unlink_lch);
1199
1200 /*----------------------------------------------------------------------------*/
1201
1202 #ifndef CONFIG_ARCH_OMAP1
1203 /* Create chain of DMA channesls */
1204 static void create_dma_lch_chain(int lch_head, int lch_queue)
1205 {
1206         u32 l;
1207
1208         /* Check if this is the first link in chain */
1209         if (dma_chan[lch_head].next_linked_ch == -1) {
1210                 dma_chan[lch_head].next_linked_ch = lch_queue;
1211                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1212                 dma_chan[lch_queue].next_linked_ch = lch_head;
1213                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1214         }
1215
1216         /* a link exists, link the new channel in circular chain */
1217         else {
1218                 dma_chan[lch_queue].next_linked_ch =
1219                                         dma_chan[lch_head].next_linked_ch;
1220                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1221                 dma_chan[lch_head].next_linked_ch = lch_queue;
1222                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1223                                         lch_queue;
1224         }
1225
1226         l = dma_read(CLNK_CTRL(lch_head));
1227         l &= ~(0x1f);
1228         l |= lch_queue;
1229         dma_write(l, CLNK_CTRL(lch_head));
1230
1231         l = dma_read(CLNK_CTRL(lch_queue));
1232         l &= ~(0x1f);
1233         l |= (dma_chan[lch_queue].next_linked_ch);
1234         dma_write(l, CLNK_CTRL(lch_queue));
1235 }
1236
1237 /**
1238  * @brief omap_request_dma_chain : Request a chain of DMA channels
1239  *
1240  * @param dev_id - Device id using the dma channel
1241  * @param dev_name - Device name
1242  * @param callback - Call back function
1243  * @chain_id -
1244  * @no_of_chans - Number of channels requested
1245  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1246  *                                            OMAP_DMA_DYNAMIC_CHAIN
1247  * @params - Channel parameters
1248  *
1249  * @return - Succes : 0
1250  *           Failure: -EINVAL/-ENOMEM
1251  */
1252 int omap_request_dma_chain(int dev_id, const char *dev_name,
1253                            void (*callback) (int lch, u16 ch_status,
1254                                              void *data),
1255                            int *chain_id, int no_of_chans, int chain_mode,
1256                            struct omap_dma_channel_params params)
1257 {
1258         int *channels;
1259         int i, err;
1260
1261         /* Is the chain mode valid ? */
1262         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1263                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1264                 printk(KERN_ERR "Invalid chain mode requested\n");
1265                 return -EINVAL;
1266         }
1267
1268         if (unlikely((no_of_chans < 1
1269                         || no_of_chans > dma_lch_count))) {
1270                 printk(KERN_ERR "Invalid Number of channels requested\n");
1271                 return -EINVAL;
1272         }
1273
1274         /* Allocate a queue to maintain the status of the channels
1275          * in the chain */
1276         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1277         if (channels == NULL) {
1278                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1279                 return -ENOMEM;
1280         }
1281
1282         /* request and reserve DMA channels for the chain */
1283         for (i = 0; i < no_of_chans; i++) {
1284                 err = omap_request_dma(dev_id, dev_name,
1285                                         callback, NULL, &channels[i]);
1286                 if (err < 0) {
1287                         int j;
1288                         for (j = 0; j < i; j++)
1289                                 omap_free_dma(channels[j]);
1290                         kfree(channels);
1291                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1292                         return err;
1293                 }
1294                 dma_chan[channels[i]].prev_linked_ch = -1;
1295                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1296
1297                 /*
1298                  * Allowing client drivers to set common parameters now,
1299                  * so that later only relevant (src_start, dest_start
1300                  * and element count) can be set
1301                  */
1302                 omap_set_dma_params(channels[i], &params);
1303         }
1304
1305         *chain_id = channels[0];
1306         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1307         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1308         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1309         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1310
1311         for (i = 0; i < no_of_chans; i++)
1312                 dma_chan[channels[i]].chain_id = *chain_id;
1313
1314         /* Reset the Queue pointers */
1315         OMAP_DMA_CHAIN_QINIT(*chain_id);
1316
1317         /* Set up the chain */
1318         if (no_of_chans == 1)
1319                 create_dma_lch_chain(channels[0], channels[0]);
1320         else {
1321                 for (i = 0; i < (no_of_chans - 1); i++)
1322                         create_dma_lch_chain(channels[i], channels[i + 1]);
1323         }
1324
1325         return 0;
1326 }
1327 EXPORT_SYMBOL(omap_request_dma_chain);
1328
1329 /**
1330  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1331  * params after setting it. Dont do this while dma is running!!
1332  *
1333  * @param chain_id - Chained logical channel id.
1334  * @param params
1335  *
1336  * @return - Success : 0
1337  *           Failure : -EINVAL
1338  */
1339 int omap_modify_dma_chain_params(int chain_id,
1340                                 struct omap_dma_channel_params params)
1341 {
1342         int *channels;
1343         u32 i;
1344
1345         /* Check for input params */
1346         if (unlikely((chain_id < 0
1347                         || chain_id >= dma_lch_count))) {
1348                 printk(KERN_ERR "Invalid chain id\n");
1349                 return -EINVAL;
1350         }
1351
1352         /* Check if the chain exists */
1353         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1354                 printk(KERN_ERR "Chain doesn't exists\n");
1355                 return -EINVAL;
1356         }
1357         channels = dma_linked_lch[chain_id].linked_dmach_q;
1358
1359         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1360                 /*
1361                  * Allowing client drivers to set common parameters now,
1362                  * so that later only relevant (src_start, dest_start
1363                  * and element count) can be set
1364                  */
1365                 omap_set_dma_params(channels[i], &params);
1366         }
1367
1368         return 0;
1369 }
1370 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1371
1372 /**
1373  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1374  *
1375  * @param chain_id
1376  *
1377  * @return - Success : 0
1378  *           Failure : -EINVAL
1379  */
1380 int omap_free_dma_chain(int chain_id)
1381 {
1382         int *channels;
1383         u32 i;
1384
1385         /* Check for input params */
1386         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1387                 printk(KERN_ERR "Invalid chain id\n");
1388                 return -EINVAL;
1389         }
1390
1391         /* Check if the chain exists */
1392         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1393                 printk(KERN_ERR "Chain doesn't exists\n");
1394                 return -EINVAL;
1395         }
1396
1397         channels = dma_linked_lch[chain_id].linked_dmach_q;
1398         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1399                 dma_chan[channels[i]].next_linked_ch = -1;
1400                 dma_chan[channels[i]].prev_linked_ch = -1;
1401                 dma_chan[channels[i]].chain_id = -1;
1402                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1403                 omap_free_dma(channels[i]);
1404         }
1405
1406         kfree(channels);
1407
1408         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1409         dma_linked_lch[chain_id].chain_mode = -1;
1410         dma_linked_lch[chain_id].chain_state = -1;
1411
1412         return (0);
1413 }
1414 EXPORT_SYMBOL(omap_free_dma_chain);
1415
1416 /**
1417  * @brief omap_dma_chain_status - Check if the chain is in
1418  * active / inactive state.
1419  * @param chain_id
1420  *
1421  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1422  *           Failure : -EINVAL
1423  */
1424 int omap_dma_chain_status(int chain_id)
1425 {
1426         /* Check for input params */
1427         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1428                 printk(KERN_ERR "Invalid chain id\n");
1429                 return -EINVAL;
1430         }
1431
1432         /* Check if the chain exists */
1433         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1434                 printk(KERN_ERR "Chain doesn't exists\n");
1435                 return -EINVAL;
1436         }
1437         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1438                         dma_linked_lch[chain_id].q_count);
1439
1440         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1441                 return OMAP_DMA_CHAIN_INACTIVE;
1442
1443         return OMAP_DMA_CHAIN_ACTIVE;
1444 }
1445 EXPORT_SYMBOL(omap_dma_chain_status);
1446
1447 /**
1448  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1449  * set the params and start the transfer.
1450  *
1451  * @param chain_id
1452  * @param src_start - buffer start address
1453  * @param dest_start - Dest address
1454  * @param elem_count
1455  * @param frame_count
1456  * @param callbk_data - channel callback parameter data.
1457  *
1458  * @return  - Success : 0
1459  *            Failure: -EINVAL/-EBUSY
1460  */
1461 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1462                         int elem_count, int frame_count, void *callbk_data)
1463 {
1464         int *channels;
1465         u32 l, lch;
1466         int start_dma = 0;
1467
1468         /*
1469          * if buffer size is less than 1 then there is
1470          * no use of starting the chain
1471          */
1472         if (elem_count < 1) {
1473                 printk(KERN_ERR "Invalid buffer size\n");
1474                 return -EINVAL;
1475         }
1476
1477         /* Check for input params */
1478         if (unlikely((chain_id < 0
1479                         || chain_id >= dma_lch_count))) {
1480                 printk(KERN_ERR "Invalid chain id\n");
1481                 return -EINVAL;
1482         }
1483
1484         /* Check if the chain exists */
1485         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1486                 printk(KERN_ERR "Chain doesn't exist\n");
1487                 return -EINVAL;
1488         }
1489
1490         /* Check if all the channels in chain are in use */
1491         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1492                 return -EBUSY;
1493
1494         /* Frame count may be negative in case of indexed transfers */
1495         channels = dma_linked_lch[chain_id].linked_dmach_q;
1496
1497         /* Get a free channel */
1498         lch = channels[dma_linked_lch[chain_id].q_tail];
1499
1500         /* Store the callback data */
1501         dma_chan[lch].data = callbk_data;
1502
1503         /* Increment the q_tail */
1504         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1505
1506         /* Set the params to the free channel */
1507         if (src_start != 0)
1508                 dma_write(src_start, CSSA(lch));
1509         if (dest_start != 0)
1510                 dma_write(dest_start, CDSA(lch));
1511
1512         /* Write the buffer size */
1513         dma_write(elem_count, CEN(lch));
1514         dma_write(frame_count, CFN(lch));
1515
1516         /*
1517          * If the chain is dynamically linked,
1518          * then we may have to start the chain if its not active
1519          */
1520         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1521
1522                 /*
1523                  * In Dynamic chain, if the chain is not started,
1524                  * queue the channel
1525                  */
1526                 if (dma_linked_lch[chain_id].chain_state ==
1527                                                 DMA_CHAIN_NOTSTARTED) {
1528                         /* Enable the link in previous channel */
1529                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1530                                                                 DMA_CH_QUEUED)
1531                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1532                         dma_chan[lch].state = DMA_CH_QUEUED;
1533                 }
1534
1535                 /*
1536                  * Chain is already started, make sure its active,
1537                  * if not then start the chain
1538                  */
1539                 else {
1540                         start_dma = 1;
1541
1542                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1543                                                         DMA_CH_STARTED) {
1544                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1545                                 dma_chan[lch].state = DMA_CH_QUEUED;
1546                                 start_dma = 0;
1547                                 if (0 == ((1 << 7) & dma_read(
1548                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1549                                         disable_lnk(dma_chan[lch].
1550                                                     prev_linked_ch);
1551                                         pr_debug("\n prev ch is stopped\n");
1552                                         start_dma = 1;
1553                                 }
1554                         }
1555
1556                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1557                                                         == DMA_CH_QUEUED) {
1558                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1559                                 dma_chan[lch].state = DMA_CH_QUEUED;
1560                                 start_dma = 0;
1561                         }
1562                         omap_enable_channel_irq(lch);
1563
1564                         l = dma_read(CCR(lch));
1565
1566                         if ((0 == (l & (1 << 24))))
1567                                 l &= ~(1 << 25);
1568                         else
1569                                 l |= (1 << 25);
1570                         if (start_dma == 1) {
1571                                 if (0 == (l & (1 << 7))) {
1572                                         l |= (1 << 7);
1573                                         dma_chan[lch].state = DMA_CH_STARTED;
1574                                         pr_debug("starting %d\n", lch);
1575                                         dma_write(l, CCR(lch));
1576                                 } else
1577                                         start_dma = 0;
1578                         } else {
1579                                 if (0 == (l & (1 << 7)))
1580                                         dma_write(l, CCR(lch));
1581                         }
1582                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1583                 }
1584         }
1585
1586         return 0;
1587 }
1588 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1589
1590 /**
1591  * @brief omap_start_dma_chain_transfers - Start the chain
1592  *
1593  * @param chain_id
1594  *
1595  * @return - Success : 0
1596  *           Failure : -EINVAL/-EBUSY
1597  */
1598 int omap_start_dma_chain_transfers(int chain_id)
1599 {
1600         int *channels;
1601         u32 l, i;
1602
1603         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1604                 printk(KERN_ERR "Invalid chain id\n");
1605                 return -EINVAL;
1606         }
1607
1608         channels = dma_linked_lch[chain_id].linked_dmach_q;
1609
1610         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1611                 printk(KERN_ERR "Chain is already started\n");
1612                 return -EBUSY;
1613         }
1614
1615         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1616                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1617                                                                         i++) {
1618                         enable_lnk(channels[i]);
1619                         omap_enable_channel_irq(channels[i]);
1620                 }
1621         } else {
1622                 omap_enable_channel_irq(channels[0]);
1623         }
1624
1625         l = dma_read(CCR(channels[0]));
1626         l |= (1 << 7);
1627         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1628         dma_chan[channels[0]].state = DMA_CH_STARTED;
1629
1630         if ((0 == (l & (1 << 24))))
1631                 l &= ~(1 << 25);
1632         else
1633                 l |= (1 << 25);
1634         dma_write(l, CCR(channels[0]));
1635
1636         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1637
1638         return 0;
1639 }
1640 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1641
1642 /**
1643  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1644  *
1645  * @param chain_id
1646  *
1647  * @return - Success : 0
1648  *           Failure : EINVAL
1649  */
1650 int omap_stop_dma_chain_transfers(int chain_id)
1651 {
1652         int *channels;
1653         u32 l, i;
1654         u32 sys_cf;
1655
1656         /* Check for input params */
1657         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1658                 printk(KERN_ERR "Invalid chain id\n");
1659                 return -EINVAL;
1660         }
1661
1662         /* Check if the chain exists */
1663         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1664                 printk(KERN_ERR "Chain doesn't exists\n");
1665                 return -EINVAL;
1666         }
1667         channels = dma_linked_lch[chain_id].linked_dmach_q;
1668
1669         /*
1670          * DMA Errata:
1671          * Special programming model needed to disable DMA before end of block
1672          */
1673         sys_cf = dma_read(OCP_SYSCONFIG);
1674         l = sys_cf;
1675         /* Middle mode reg set no Standby */
1676         l &= ~((1 << 12)|(1 << 13));
1677         dma_write(l, OCP_SYSCONFIG);
1678
1679         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1680
1681                 /* Stop the Channel transmission */
1682                 l = dma_read(CCR(channels[i]));
1683                 l &= ~(1 << 7);
1684                 dma_write(l, CCR(channels[i]));
1685
1686                 /* Disable the link in all the channels */
1687                 disable_lnk(channels[i]);
1688                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1689
1690         }
1691         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1692
1693         /* Reset the Queue pointers */
1694         OMAP_DMA_CHAIN_QINIT(chain_id);
1695
1696         /* Errata - put in the old value */
1697         dma_write(sys_cf, OCP_SYSCONFIG);
1698
1699         return 0;
1700 }
1701 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1702
1703 /* Get the index of the ongoing DMA in chain */
1704 /**
1705  * @brief omap_get_dma_chain_index - Get the element and frame index
1706  * of the ongoing DMA in chain
1707  *
1708  * @param chain_id
1709  * @param ei - Element index
1710  * @param fi - Frame index
1711  *
1712  * @return - Success : 0
1713  *           Failure : -EINVAL
1714  */
1715 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1716 {
1717         int lch;
1718         int *channels;
1719
1720         /* Check for input params */
1721         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1722                 printk(KERN_ERR "Invalid chain id\n");
1723                 return -EINVAL;
1724         }
1725
1726         /* Check if the chain exists */
1727         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1728                 printk(KERN_ERR "Chain doesn't exists\n");
1729                 return -EINVAL;
1730         }
1731         if ((!ei) || (!fi))
1732                 return -EINVAL;
1733
1734         channels = dma_linked_lch[chain_id].linked_dmach_q;
1735
1736         /* Get the current channel */
1737         lch = channels[dma_linked_lch[chain_id].q_head];
1738
1739         *ei = dma_read(CCEN(lch));
1740         *fi = dma_read(CCFN(lch));
1741
1742         return 0;
1743 }
1744 EXPORT_SYMBOL(omap_get_dma_chain_index);
1745
1746 /**
1747  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1748  * ongoing DMA in chain
1749  *
1750  * @param chain_id
1751  *
1752  * @return - Success : Destination position
1753  *           Failure : -EINVAL
1754  */
1755 int omap_get_dma_chain_dst_pos(int chain_id)
1756 {
1757         int lch;
1758         int *channels;
1759
1760         /* Check for input params */
1761         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1762                 printk(KERN_ERR "Invalid chain id\n");
1763                 return -EINVAL;
1764         }
1765
1766         /* Check if the chain exists */
1767         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1768                 printk(KERN_ERR "Chain doesn't exists\n");
1769                 return -EINVAL;
1770         }
1771
1772         channels = dma_linked_lch[chain_id].linked_dmach_q;
1773
1774         /* Get the current channel */
1775         lch = channels[dma_linked_lch[chain_id].q_head];
1776
1777         return dma_read(CDAC(lch));
1778 }
1779 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1780
1781 /**
1782  * @brief omap_get_dma_chain_src_pos - Get the source position
1783  * of the ongoing DMA in chain
1784  * @param chain_id
1785  *
1786  * @return - Success : Destination position
1787  *           Failure : -EINVAL
1788  */
1789 int omap_get_dma_chain_src_pos(int chain_id)
1790 {
1791         int lch;
1792         int *channels;
1793
1794         /* Check for input params */
1795         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1796                 printk(KERN_ERR "Invalid chain id\n");
1797                 return -EINVAL;
1798         }
1799
1800         /* Check if the chain exists */
1801         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1802                 printk(KERN_ERR "Chain doesn't exists\n");
1803                 return -EINVAL;
1804         }
1805
1806         channels = dma_linked_lch[chain_id].linked_dmach_q;
1807
1808         /* Get the current channel */
1809         lch = channels[dma_linked_lch[chain_id].q_head];
1810
1811         return dma_read(CSAC(lch));
1812 }
1813 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1814 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1815
1816 /*----------------------------------------------------------------------------*/
1817
1818 #ifdef CONFIG_ARCH_OMAP1
1819
1820 static int omap1_dma_handle_ch(int ch)
1821 {
1822         u32 csr;
1823
1824         if (enable_1510_mode && ch >= 6) {
1825                 csr = dma_chan[ch].saved_csr;
1826                 dma_chan[ch].saved_csr = 0;
1827         } else
1828                 csr = dma_read(CSR(ch));
1829         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1830                 dma_chan[ch + 6].saved_csr = csr >> 7;
1831                 csr &= 0x7f;
1832         }
1833         if ((csr & 0x3f) == 0)
1834                 return 0;
1835         if (unlikely(dma_chan[ch].dev_id == -1)) {
1836                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1837                        "%d (CSR %04x)\n", ch, csr);
1838                 return 0;
1839         }
1840         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1841                 printk(KERN_WARNING "DMA timeout with device %d\n",
1842                        dma_chan[ch].dev_id);
1843         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1844                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1845                        "with device %d\n", dma_chan[ch].dev_id);
1846         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1847                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1848         if (likely(dma_chan[ch].callback != NULL))
1849                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1850
1851         return 1;
1852 }
1853
1854 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1855 {
1856         int ch = ((int) dev_id) - 1;
1857         int handled = 0;
1858
1859         for (;;) {
1860                 int handled_now = 0;
1861
1862                 handled_now += omap1_dma_handle_ch(ch);
1863                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1864                         handled_now += omap1_dma_handle_ch(ch + 6);
1865                 if (!handled_now)
1866                         break;
1867                 handled += handled_now;
1868         }
1869
1870         return handled ? IRQ_HANDLED : IRQ_NONE;
1871 }
1872
1873 #else
1874 #define omap1_dma_irq_handler   NULL
1875 #endif
1876
1877 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1878                         defined(CONFIG_ARCH_OMAP4)
1879
1880 static int omap2_dma_handle_ch(int ch)
1881 {
1882         u32 status = dma_read(CSR(ch));
1883
1884         if (!status) {
1885                 if (printk_ratelimit())
1886                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1887                                 ch);
1888                 dma_write(1 << ch, IRQSTATUS_L0);
1889                 return 0;
1890         }
1891         if (unlikely(dma_chan[ch].dev_id == -1)) {
1892                 if (printk_ratelimit())
1893                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1894                                         "channel %d\n", status, ch);
1895                 return 0;
1896         }
1897         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1898                 printk(KERN_INFO
1899                        "DMA synchronization event drop occurred with device "
1900                        "%d\n", dma_chan[ch].dev_id);
1901         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1902                 printk(KERN_INFO "DMA transaction error with device %d\n",
1903                        dma_chan[ch].dev_id);
1904                 if (cpu_class_is_omap2()) {
1905                         /* Errata: sDMA Channel is not disabled
1906                          * after a transaction error. So we explicitely
1907                          * disable the channel
1908                          */
1909                         u32 ccr;
1910
1911                         ccr = dma_read(CCR(ch));
1912                         ccr &= ~OMAP_DMA_CCR_EN;
1913                         dma_write(ccr, CCR(ch));
1914                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1915                 }
1916         }
1917         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1918                 printk(KERN_INFO "DMA secure error with device %d\n",
1919                        dma_chan[ch].dev_id);
1920         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1921                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1922                        dma_chan[ch].dev_id);
1923
1924         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1925         dma_write(1 << ch, IRQSTATUS_L0);
1926
1927         /* If the ch is not chained then chain_id will be -1 */
1928         if (dma_chan[ch].chain_id != -1) {
1929                 int chain_id = dma_chan[ch].chain_id;
1930                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1931                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1932                         dma_chan[dma_chan[ch].next_linked_ch].state =
1933                                                         DMA_CH_STARTED;
1934                 if (dma_linked_lch[chain_id].chain_mode ==
1935                                                 OMAP_DMA_DYNAMIC_CHAIN)
1936                         disable_lnk(ch);
1937
1938                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1939                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1940
1941                 status = dma_read(CSR(ch));
1942         }
1943
1944         dma_write(status, CSR(ch));
1945
1946         if (likely(dma_chan[ch].callback != NULL))
1947                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1948
1949         return 0;
1950 }
1951
1952 /* STATUS register count is from 1-32 while our is 0-31 */
1953 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1954 {
1955         u32 val, enable_reg;
1956         int i;
1957
1958         val = dma_read(IRQSTATUS_L0);
1959         if (val == 0) {
1960                 if (printk_ratelimit())
1961                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1962                 return IRQ_HANDLED;
1963         }
1964         enable_reg = dma_read(IRQENABLE_L0);
1965         val &= enable_reg; /* Dispatch only relevant interrupts */
1966         for (i = 0; i < dma_lch_count && val != 0; i++) {
1967                 if (val & 1)
1968                         omap2_dma_handle_ch(i);
1969                 val >>= 1;
1970         }
1971
1972         return IRQ_HANDLED;
1973 }
1974
1975 static struct irqaction omap24xx_dma_irq = {
1976         .name = "DMA",
1977         .handler = omap2_dma_irq_handler,
1978         .flags = IRQF_DISABLED
1979 };
1980
1981 #else
1982 static struct irqaction omap24xx_dma_irq;
1983 #endif
1984
1985 /*----------------------------------------------------------------------------*/
1986
1987 static struct lcd_dma_info {
1988         spinlock_t lock;
1989         int reserved;
1990         void (*callback)(u16 status, void *data);
1991         void *cb_data;
1992
1993         int active;
1994         unsigned long addr, size;
1995         int rotate, data_type, xres, yres;
1996         int vxres;
1997         int mirror;
1998         int xscale, yscale;
1999         int ext_ctrl;
2000         int src_port;
2001         int single_transfer;
2002 } lcd_dma;
2003
2004 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
2005                          int data_type)
2006 {
2007         lcd_dma.addr = addr;
2008         lcd_dma.data_type = data_type;
2009         lcd_dma.xres = fb_xres;
2010         lcd_dma.yres = fb_yres;
2011 }
2012 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2013
2014 void omap_set_lcd_dma_src_port(int port)
2015 {
2016         lcd_dma.src_port = port;
2017 }
2018
2019 void omap_set_lcd_dma_ext_controller(int external)
2020 {
2021         lcd_dma.ext_ctrl = external;
2022 }
2023 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2024
2025 void omap_set_lcd_dma_single_transfer(int single)
2026 {
2027         lcd_dma.single_transfer = single;
2028 }
2029 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2030
2031 void omap_set_lcd_dma_b1_rotation(int rotate)
2032 {
2033         if (omap_dma_in_1510_mode()) {
2034                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2035                 BUG();
2036                 return;
2037         }
2038         lcd_dma.rotate = rotate;
2039 }
2040 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2041
2042 void omap_set_lcd_dma_b1_mirror(int mirror)
2043 {
2044         if (omap_dma_in_1510_mode()) {
2045                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2046                 BUG();
2047         }
2048         lcd_dma.mirror = mirror;
2049 }
2050 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2051
2052 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2053 {
2054         if (omap_dma_in_1510_mode()) {
2055                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2056                                 "in 1510 mode\n");
2057                 BUG();
2058         }
2059         lcd_dma.vxres = vxres;
2060 }
2061 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2062
2063 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2064 {
2065         if (omap_dma_in_1510_mode()) {
2066                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2067                 BUG();
2068         }
2069         lcd_dma.xscale = xscale;
2070         lcd_dma.yscale = yscale;
2071 }
2072 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2073
2074 static void set_b1_regs(void)
2075 {
2076         unsigned long top, bottom;
2077         int es;
2078         u16 w;
2079         unsigned long en, fn;
2080         long ei, fi;
2081         unsigned long vxres;
2082         unsigned int xscale, yscale;
2083
2084         switch (lcd_dma.data_type) {
2085         case OMAP_DMA_DATA_TYPE_S8:
2086                 es = 1;
2087                 break;
2088         case OMAP_DMA_DATA_TYPE_S16:
2089                 es = 2;
2090                 break;
2091         case OMAP_DMA_DATA_TYPE_S32:
2092                 es = 4;
2093                 break;
2094         default:
2095                 BUG();
2096                 return;
2097         }
2098
2099         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2100         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2101         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2102         BUG_ON(vxres < lcd_dma.xres);
2103
2104 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2105                 ((y) * vxres * yscale + (x) * xscale) * es)
2106 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2107
2108         switch (lcd_dma.rotate) {
2109         case 0:
2110                 if (!lcd_dma.mirror) {
2111                         top = PIXADDR(0, 0);
2112                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2113                         /* 1510 DMA requires the bottom address to be 2 more
2114                          * than the actual last memory access location. */
2115                         if (omap_dma_in_1510_mode() &&
2116                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2117                                         bottom += 2;
2118                         ei = PIXSTEP(0, 0, 1, 0);
2119                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2120                 } else {
2121                         top = PIXADDR(lcd_dma.xres - 1, 0);
2122                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2123                         ei = PIXSTEP(1, 0, 0, 0);
2124                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2125                 }
2126                 en = lcd_dma.xres;
2127                 fn = lcd_dma.yres;
2128                 break;
2129         case 90:
2130                 if (!lcd_dma.mirror) {
2131                         top = PIXADDR(0, lcd_dma.yres - 1);
2132                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2133                         ei = PIXSTEP(0, 1, 0, 0);
2134                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2135                 } else {
2136                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2137                         bottom = PIXADDR(0, 0);
2138                         ei = PIXSTEP(0, 1, 0, 0);
2139                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2140                 }
2141                 en = lcd_dma.yres;
2142                 fn = lcd_dma.xres;
2143                 break;
2144         case 180:
2145                 if (!lcd_dma.mirror) {
2146                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2147                         bottom = PIXADDR(0, 0);
2148                         ei = PIXSTEP(1, 0, 0, 0);
2149                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2150                 } else {
2151                         top = PIXADDR(0, lcd_dma.yres - 1);
2152                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2153                         ei = PIXSTEP(0, 0, 1, 0);
2154                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2155                 }
2156                 en = lcd_dma.xres;
2157                 fn = lcd_dma.yres;
2158                 break;
2159         case 270:
2160                 if (!lcd_dma.mirror) {
2161                         top = PIXADDR(lcd_dma.xres - 1, 0);
2162                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2163                         ei = PIXSTEP(0, 0, 0, 1);
2164                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2165                 } else {
2166                         top = PIXADDR(0, 0);
2167                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2168                         ei = PIXSTEP(0, 0, 0, 1);
2169                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2170                 }
2171                 en = lcd_dma.yres;
2172                 fn = lcd_dma.xres;
2173                 break;
2174         default:
2175                 BUG();
2176                 return; /* Suppress warning about uninitialized vars */
2177         }
2178
2179         if (omap_dma_in_1510_mode()) {
2180                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2181                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2182                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2183                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2184
2185                 return;
2186         }
2187
2188         /* 1610 regs */
2189         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2190         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2191         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2192         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2193
2194         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2195         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2196
2197         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2198         w &= ~0x03;
2199         w |= lcd_dma.data_type;
2200         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2201
2202         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2203         /* Always set the source port as SDRAM for now*/
2204         w &= ~(0x03 << 6);
2205         if (lcd_dma.callback != NULL)
2206                 w |= 1 << 1;            /* Block interrupt enable */
2207         else
2208                 w &= ~(1 << 1);
2209         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2210
2211         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2212               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2213                 return;
2214
2215         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2216         /* Set the double-indexed addressing mode */
2217         w |= (0x03 << 12);
2218         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2219
2220         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2221         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2222         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2223 }
2224
2225 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2226 {
2227         u16 w;
2228
2229         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2230         if (unlikely(!(w & (1 << 3)))) {
2231                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2232                 return IRQ_NONE;
2233         }
2234         /* Ack the IRQ */
2235         w |= (1 << 3);
2236         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2237         lcd_dma.active = 0;
2238         if (lcd_dma.callback != NULL)
2239                 lcd_dma.callback(w, lcd_dma.cb_data);
2240
2241         return IRQ_HANDLED;
2242 }
2243
2244 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2245                          void *data)
2246 {
2247         spin_lock_irq(&lcd_dma.lock);
2248         if (lcd_dma.reserved) {
2249                 spin_unlock_irq(&lcd_dma.lock);
2250                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2251                 BUG();
2252                 return -EBUSY;
2253         }
2254         lcd_dma.reserved = 1;
2255         spin_unlock_irq(&lcd_dma.lock);
2256         lcd_dma.callback = callback;
2257         lcd_dma.cb_data = data;
2258         lcd_dma.active = 0;
2259         lcd_dma.single_transfer = 0;
2260         lcd_dma.rotate = 0;
2261         lcd_dma.vxres = 0;
2262         lcd_dma.mirror = 0;
2263         lcd_dma.xscale = 0;
2264         lcd_dma.yscale = 0;
2265         lcd_dma.ext_ctrl = 0;
2266         lcd_dma.src_port = 0;
2267
2268         return 0;
2269 }
2270 EXPORT_SYMBOL(omap_request_lcd_dma);
2271
2272 void omap_free_lcd_dma(void)
2273 {
2274         spin_lock(&lcd_dma.lock);
2275         if (!lcd_dma.reserved) {
2276                 spin_unlock(&lcd_dma.lock);
2277                 printk(KERN_ERR "LCD DMA is not reserved\n");
2278                 BUG();
2279                 return;
2280         }
2281         if (!enable_1510_mode)
2282                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2283                             OMAP1610_DMA_LCD_CCR);
2284         lcd_dma.reserved = 0;
2285         spin_unlock(&lcd_dma.lock);
2286 }
2287 EXPORT_SYMBOL(omap_free_lcd_dma);
2288
2289 void omap_enable_lcd_dma(void)
2290 {
2291         u16 w;
2292
2293         /*
2294          * Set the Enable bit only if an external controller is
2295          * connected. Otherwise the OMAP internal controller will
2296          * start the transfer when it gets enabled.
2297          */
2298         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2299                 return;
2300
2301         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2302         w |= 1 << 8;
2303         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2304
2305         lcd_dma.active = 1;
2306
2307         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2308         w |= 1 << 7;
2309         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2310 }
2311 EXPORT_SYMBOL(omap_enable_lcd_dma);
2312
2313 void omap_setup_lcd_dma(void)
2314 {
2315         BUG_ON(lcd_dma.active);
2316         if (!enable_1510_mode) {
2317                 /* Set some reasonable defaults */
2318                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2319                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2320                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2321         }
2322         set_b1_regs();
2323         if (!enable_1510_mode) {
2324                 u16 w;
2325
2326                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2327                 /*
2328                  * If DMA was already active set the end_prog bit to have
2329                  * the programmed register set loaded into the active
2330                  * register set.
2331                  */
2332                 w |= 1 << 11;           /* End_prog */
2333                 if (!lcd_dma.single_transfer)
2334                         w |= (3 << 8);  /* Auto_init, repeat */
2335                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2336         }
2337 }
2338 EXPORT_SYMBOL(omap_setup_lcd_dma);
2339
2340 void omap_stop_lcd_dma(void)
2341 {
2342         u16 w;
2343
2344         lcd_dma.active = 0;
2345         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2346                 return;
2347
2348         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2349         w &= ~(1 << 7);
2350         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2351
2352         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2353         w &= ~(1 << 8);
2354         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2355 }
2356 EXPORT_SYMBOL(omap_stop_lcd_dma);
2357
2358 /*----------------------------------------------------------------------------*/
2359
2360 static int __init omap_init_dma(void)
2361 {
2362         int ch, r;
2363
2364         if (cpu_class_is_omap1()) {
2365                 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2366                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2367         } else if (cpu_is_omap24xx()) {
2368                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2369                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2370         } else if (cpu_is_omap34xx()) {
2371                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2372                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2373         } else if (cpu_is_omap44xx()) {
2374                 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2375                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2376         } else {
2377                 pr_err("DMA init failed for unsupported omap\n");
2378                 return -ENODEV;
2379         }
2380
2381         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2382                         && (omap_dma_reserve_channels <= dma_lch_count))
2383                 dma_lch_count = omap_dma_reserve_channels;
2384
2385         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2386                                 GFP_KERNEL);
2387         if (!dma_chan)
2388                 return -ENOMEM;
2389
2390         if (cpu_class_is_omap2()) {
2391                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2392                                                 dma_lch_count, GFP_KERNEL);
2393                 if (!dma_linked_lch) {
2394                         kfree(dma_chan);
2395                         return -ENOMEM;
2396                 }
2397         }
2398
2399         if (cpu_is_omap15xx()) {
2400                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2401                 dma_chan_count = 9;
2402                 enable_1510_mode = 1;
2403         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2404                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2405                        dma_read(HW_ID));
2406                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2407                        (dma_read(CAPS_0_U) << 16) |
2408                        dma_read(CAPS_0_L),
2409                        (dma_read(CAPS_1_U) << 16) |
2410                        dma_read(CAPS_1_L),
2411                        dma_read(CAPS_2), dma_read(CAPS_3),
2412                        dma_read(CAPS_4));
2413                 if (!enable_1510_mode) {
2414                         u16 w;
2415
2416                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2417                         w = dma_read(GSCR);
2418                         w |= 1 << 3;
2419                         dma_write(w, GSCR);
2420                         dma_chan_count = 16;
2421                 } else
2422                         dma_chan_count = 9;
2423                 if (cpu_is_omap16xx()) {
2424                         u16 w;
2425
2426                         /* this would prevent OMAP sleep */
2427                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2428                         w &= ~(1 << 8);
2429                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2430                 }
2431         } else if (cpu_class_is_omap2()) {
2432                 u8 revision = dma_read(REVISION) & 0xff;
2433                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2434                        revision >> 4, revision & 0xf);
2435                 dma_chan_count = dma_lch_count;
2436         } else {
2437                 dma_chan_count = 0;
2438                 return 0;
2439         }
2440
2441         spin_lock_init(&lcd_dma.lock);
2442         spin_lock_init(&dma_chan_lock);
2443
2444         for (ch = 0; ch < dma_chan_count; ch++) {
2445                 omap_clear_dma(ch);
2446                 dma_chan[ch].dev_id = -1;
2447                 dma_chan[ch].next_lch = -1;
2448
2449                 if (ch >= 6 && enable_1510_mode)
2450                         continue;
2451
2452                 if (cpu_class_is_omap1()) {
2453                         /*
2454                          * request_irq() doesn't like dev_id (ie. ch) being
2455                          * zero, so we have to kludge around this.
2456                          */
2457                         r = request_irq(omap1_dma_irq[ch],
2458                                         omap1_dma_irq_handler, 0, "DMA",
2459                                         (void *) (ch + 1));
2460                         if (r != 0) {
2461                                 int i;
2462
2463                                 printk(KERN_ERR "unable to request IRQ %d "
2464                                        "for DMA (error %d)\n",
2465                                        omap1_dma_irq[ch], r);
2466                                 for (i = 0; i < ch; i++)
2467                                         free_irq(omap1_dma_irq[i],
2468                                                  (void *) (i + 1));
2469                                 return r;
2470                         }
2471                 }
2472         }
2473
2474         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2475                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2476                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2477
2478         if (cpu_class_is_omap2()) {
2479                 int irq;
2480                 if (cpu_is_omap44xx())
2481                         irq = INT_44XX_SDMA_IRQ0;
2482                 else
2483                         irq = INT_24XX_SDMA_IRQ0;
2484                 setup_irq(irq, &omap24xx_dma_irq);
2485         }
2486
2487         /* Enable smartidle idlemodes and autoidle */
2488         if (cpu_is_omap34xx()) {
2489                 u32 v = dma_read(OCP_SYSCONFIG);
2490                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2491                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2492                                 DMA_SYSCONFIG_AUTOIDLE);
2493                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2494                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2495                         DMA_SYSCONFIG_AUTOIDLE);
2496                 dma_write(v , OCP_SYSCONFIG);
2497         }
2498
2499
2500         /* FIXME: Update LCD DMA to work on 24xx */
2501         if (cpu_class_is_omap1()) {
2502                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2503                                 "LCD DMA", NULL);
2504                 if (r != 0) {
2505                         int i;
2506
2507                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2508                                "(error %d)\n", r);
2509                         for (i = 0; i < dma_chan_count; i++)
2510                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2511                         return r;
2512                 }
2513         }
2514
2515         return 0;
2516 }
2517
2518 arch_initcall(omap_init_dma);
2519
2520 /*
2521  * Reserve the omap SDMA channels using cmdline bootarg
2522  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2523  */
2524 static int __init omap_dma_cmdline_reserve_ch(char *str)
2525 {
2526         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2527                 omap_dma_reserve_channels = 0;
2528         return 1;
2529 }
2530
2531 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2532
2533