arch/arm/plat-iop/adma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * platform device definitions for the iop3xx dma/xor engines
   4  * Copyright © 2006, Intel Corporation.
   5  */
   6 #include <linux/platform_device.h>
   7 #include <asm/hardware/iop3xx.h>
   8 #include <linux/dma-mapping.h>
   9 #include <mach/adma.h>
  10 #include <asm/hardware/iop_adma.h>
  11
  12 #ifdef CONFIG_ARCH_IOP32X
  13 #define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT
  14 #define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC
  15 #define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR
  16
  17 #define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT
  18 #define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC
  19 #define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR
  20
  21 #define IRQ_AA_EOT IRQ_IOP32X_AA_EOT
  22 #define IRQ_AA_EOC IRQ_IOP32X_AA_EOC
  23 #define IRQ_AA_ERR IRQ_IOP32X_AA_ERR
  24 #endif
  25 #ifdef CONFIG_ARCH_IOP33X
  26 #define IRQ_DMA0_EOT IRQ_IOP33X_DMA0_EOT
  27 #define IRQ_DMA0_EOC IRQ_IOP33X_DMA0_EOC
  28 #define IRQ_DMA0_ERR IRQ_IOP33X_DMA0_ERR
  29
  30 #define IRQ_DMA1_EOT IRQ_IOP33X_DMA1_EOT
  31 #define IRQ_DMA1_EOC IRQ_IOP33X_DMA1_EOC
  32 #define IRQ_DMA1_ERR IRQ_IOP33X_DMA1_ERR
  33
  34 #define IRQ_AA_EOT IRQ_IOP33X_AA_EOT
  35 #define IRQ_AA_EOC IRQ_IOP33X_AA_EOC
  36 #define IRQ_AA_ERR IRQ_IOP33X_AA_ERR
  37 #endif
  38 /* AAU and DMA Channels */
  39 static struct resource iop3xx_dma_0_resources[] = {
  40         [0] = {
  41                 .start = IOP3XX_DMA_PHYS_BASE(0),
  42                 .end = IOP3XX_DMA_UPPER_PA(0),
  43                 .flags = IORESOURCE_MEM,
  44         },
  45         [1] = {
  46                 .start = IRQ_DMA0_EOT,
  47                 .end = IRQ_DMA0_EOT,
  48                 .flags = IORESOURCE_IRQ
  49         },
  50         [2] = {
  51                 .start = IRQ_DMA0_EOC,
  52                 .end = IRQ_DMA0_EOC,
  53                 .flags = IORESOURCE_IRQ
  54         },
  55         [3] = {
  56                 .start = IRQ_DMA0_ERR,
  57                 .end = IRQ_DMA0_ERR,
  58                 .flags = IORESOURCE_IRQ
  59         }
  60 };
  61
  62 static struct resource iop3xx_dma_1_resources[] = {
  63         [0] = {
  64                 .start = IOP3XX_DMA_PHYS_BASE(1),
  65                 .end = IOP3XX_DMA_UPPER_PA(1),
  66                 .flags = IORESOURCE_MEM,
  67         },
  68         [1] = {
  69                 .start = IRQ_DMA1_EOT,
  70                 .end = IRQ_DMA1_EOT,
  71                 .flags = IORESOURCE_IRQ
  72         },
  73         [2] = {
  74                 .start = IRQ_DMA1_EOC,
  75                 .end = IRQ_DMA1_EOC,
  76                 .flags = IORESOURCE_IRQ
  77         },
  78         [3] = {
  79                 .start = IRQ_DMA1_ERR,
  80                 .end = IRQ_DMA1_ERR,
  81                 .flags = IORESOURCE_IRQ
  82         }
  83 };
  84
  85
  86 static struct resource iop3xx_aau_resources[] = {
  87         [0] = {
  88                 .start = IOP3XX_AAU_PHYS_BASE,
  89                 .end = IOP3XX_AAU_UPPER_PA,
  90                 .flags = IORESOURCE_MEM,
  91         },
  92         [1] = {
  93                 .start = IRQ_AA_EOT,
  94                 .end = IRQ_AA_EOT,
  95                 .flags = IORESOURCE_IRQ
  96         },
  97         [2] = {
  98                 .start = IRQ_AA_EOC,
  99                 .end = IRQ_AA_EOC,
 100                 .flags = IORESOURCE_IRQ
 101         },
 102         [3] = {
 103                 .start = IRQ_AA_ERR,
 104                 .end = IRQ_AA_ERR,
 105                 .flags = IORESOURCE_IRQ
 106         }
 107 };
 108
 109 static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32);
 110
 111 static struct iop_adma_platform_data iop3xx_dma_0_data = {
 112         .hw_id = DMA0_ID,
 113         .pool_size = PAGE_SIZE,
 114 };
 115
 116 static struct iop_adma_platform_data iop3xx_dma_1_data = {
 117         .hw_id = DMA1_ID,
 118         .pool_size = PAGE_SIZE,
 119 };
 120
 121 static struct iop_adma_platform_data iop3xx_aau_data = {
 122         .hw_id = AAU_ID,
 123         .pool_size = 3 * PAGE_SIZE,
 124 };
 125
 126 struct platform_device iop3xx_dma_0_channel = {
 127         .name = "iop-adma",
 128         .id = 0,
 129         .num_resources = 4,
 130         .resource = iop3xx_dma_0_resources,
 131         .dev = {
 132                 .dma_mask = &iop3xx_adma_dmamask,
 133                 .coherent_dma_mask = DMA_BIT_MASK(32),
 134                 .platform_data = (void *) &iop3xx_dma_0_data,
 135         },
 136 };
 137
 138 struct platform_device iop3xx_dma_1_channel = {
 139         .name = "iop-adma",
 140         .id = 1,
 141         .num_resources = 4,
 142         .resource = iop3xx_dma_1_resources,
 143         .dev = {
 144                 .dma_mask = &iop3xx_adma_dmamask,
 145                 .coherent_dma_mask = DMA_BIT_MASK(32),
 146                 .platform_data = (void *) &iop3xx_dma_1_data,
 147         },
 148 };
 149
 150 struct platform_device iop3xx_aau_channel = {
 151         .name = "iop-adma",
 152         .id = 2,
 153         .num_resources = 4,
 154         .resource = iop3xx_aau_resources,
 155         .dev = {
 156                 .dma_mask = &iop3xx_adma_dmamask,
 157                 .coherent_dma_mask = DMA_BIT_MASK(32),
 158                 .platform_data = (void *) &iop3xx_aau_data,
 159         },
 160 };
 161
 162 static int __init iop3xx_adma_cap_init(void)
 163 {
 164         #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
 165         dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
 166         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
 167         #else
 168         dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask);
 169         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask);
 170         #endif
 171
 172         #ifdef CONFIG_ARCH_IOP32X /* the 32x DMA does not perform CRC32C */
 173         dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
 174         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
 175         #else
 176         dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask);
 177         dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask);
 178         #endif
 179
 180         #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
 181         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
 182         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
 183         #else
 184         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
 185         dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
 186         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
 187         #endif
 188
 189         return 0;
 190 }
 191
 192 arch_initcall(iop3xx_adma_cap_init);