2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35 #define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB
36 #define PMD_FLAGS PMD_SECT_WB
38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39 #define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40 #define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
43 ENTRY(cpu_v7_proc_init)
45 ENDPROC(cpu_v7_proc_init)
47 ENTRY(cpu_v7_proc_fin)
49 ENDPROC(cpu_v7_proc_fin)
54 * Perform a soft reset of the system. Put the CPU into the
55 * same state as it would be if it had been reset, and branch
56 * to what would be the reset vector.
58 * - loc - location to jump to for soft reset
70 * Idle the processor (eg, wait for interrupt).
72 * IRQs are already disabled.
75 dsb @ WFI may enter a low-power mode
78 ENDPROC(cpu_v7_do_idle)
80 ENTRY(cpu_v7_dcache_clean_area)
81 #ifndef TLB_CAN_READ_FROM_L1_CACHE
82 dcache_line_size r2, r3
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
90 ENDPROC(cpu_v7_dcache_clean_area)
93 * cpu_v7_switch_mm(pgd_phys, tsk)
95 * Set the translation table base pointer to be pgd_phys
97 * - pgd_phys - physical address of new TTB
100 * - we are not using split page tables
102 ENTRY(cpu_v7_switch_mm)
105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
106 orr r0, r0, #TTB_FLAGS
107 #ifdef CONFIG_ARM_ERRATA_430973
108 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
112 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
118 ENDPROC(cpu_v7_switch_mm)
121 * cpu_v7_set_pte_ext(ptep, pte)
123 * Set a level 2 translation table entry.
125 * - ptep - pointer to level 2 translation table entry
126 * (hardware version is stored at -1024 bytes)
127 * - pte - PTE value to store
128 * - ext - value for extended PTE bits
130 ENTRY(cpu_v7_set_pte_ext)
132 ARM( str r1, [r0], #-2048 ) @ linux version
133 THUMB( str r1, [r0] ) @ linux version
134 THUMB( sub r0, r0, #2048 )
136 bic r3, r1, #0x000003f0
137 bic r3, r3, #PTE_TYPE_MASK
139 orr r3, r3, #PTE_EXT_AP0 | 2
142 orrne r3, r3, #PTE_EXT_TEX(1)
145 tstne r1, #L_PTE_DIRTY
146 orreq r3, r3, #PTE_EXT_APX
149 orrne r3, r3, #PTE_EXT_AP1
150 tstne r3, #PTE_EXT_APX
151 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
154 orreq r3, r3, #PTE_EXT_XN
157 tstne r1, #L_PTE_PRESENT
161 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
164 ENDPROC(cpu_v7_set_pte_ext)
167 .ascii "ARMv7 Processor"
175 * Initialise TLB, Caches, and MMU state ready to switch the MMU
176 * on. Return in r0 the new CP15 C1 control register setting.
178 * We automatically detect if we have a Harvard cache, and use the
179 * Harvard cache control instructions insead of the unified cache
180 * control instructions.
182 * This should be able to cover all ARMv7 cores.
184 * It is assumed that:
185 * - cache type register is implemented
189 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and
190 orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting
191 mcr p15, 0, r0, c1, c0, 1
193 adr r12, __v7_setup_stack @ the local stack
194 stmia r12, {r0-r5, r7, r9, r11, lr}
195 bl v7_flush_dcache_all
196 ldmia r12, {r0-r5, r7, r9, r11, lr}
198 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
199 and r10, r0, #0xff000000 @ ARM?
202 and r5, r0, #0x00f00000 @ variant
203 and r6, r0, #0x0000000f @ revision
204 orr r0, r6, r5, lsr #20-4 @ combine variant and revision
206 #ifdef CONFIG_ARM_ERRATA_430973
207 teq r5, #0x00100000 @ only present in r1p*
208 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
209 orreq r10, r10, #(1 << 6) @ set IBE to 1
210 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
212 #ifdef CONFIG_ARM_ERRATA_458693
213 teq r0, #0x20 @ only present in r2p0
214 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
215 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
216 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
217 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
219 #ifdef CONFIG_ARM_ERRATA_460075
220 teq r0, #0x20 @ only present in r2p0
221 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
223 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
224 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
229 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
233 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
234 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
235 orr r4, r4, #TTB_FLAGS
236 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
237 mov r10, #0x1f @ domains 0, 1 = manager
238 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
240 * Memory region attributes with SCTLR.TRE=1
243 * TR = PRRR[2n+1:2n] - memory type
244 * IR = NMRR[2n+1:2n] - inner cacheable property
245 * OR = NMRR[2n+17:2n+16] - outer cacheable property
249 * BUFFERABLE 001 10 00 00
250 * WRITETHROUGH 010 10 10 10
251 * WRITEBACK 011 10 11 11
253 * WRITEALLOC 111 10 01 01
255 * DEV_NONSHARED 100 01
261 * DS0 = PRRR[16] = 0 - device shareable property
262 * DS1 = PRRR[17] = 1 - device shareable property
263 * NS0 = PRRR[18] = 0 - normal shareable property
264 * NS1 = PRRR[19] = 1 - normal shareable property
265 * NOS = PRRR[24+n] = 1 - not outer shareable
267 ldr r5, =0xff0a81a8 @ PRRR
268 ldr r6, =0x40e040e0 @ NMRR
269 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
270 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
274 #ifdef CONFIG_CPU_ENDIAN_BE8
275 orr r6, r6, #1 << 25 @ big-endian page tables
277 mrc p15, 0, r0, c1, c0, 0 @ read control register
278 bic r0, r0, r5 @ clear bits them
279 orr r0, r0, r6 @ set them
280 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
281 mov pc, lr @ return to head.S:__ret
285 * TFR EV X F I D LR S
286 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
287 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
288 * 1 0 110 0011 1100 .111 1101 < we want
290 .type v7_crval, #object
292 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
295 .space 4 * 11 @ 11 registers
297 .type v7_processor_functions, #object
298 ENTRY(v7_processor_functions)
301 .word cpu_v7_proc_init
302 .word cpu_v7_proc_fin
305 .word cpu_v7_dcache_clean_area
306 .word cpu_v7_switch_mm
307 .word cpu_v7_set_pte_ext
308 .size v7_processor_functions, . - v7_processor_functions
310 .type cpu_arch_name, #object
313 .size cpu_arch_name, . - cpu_arch_name
315 .type cpu_elf_name, #object
318 .size cpu_elf_name, . - cpu_elf_name
321 .section ".proc.info.init", #alloc, #execinstr
324 * Match any ARMv7 processor core.
326 .type __v7_proc_info, #object
328 .long 0x000f0000 @ Required ID value
329 .long 0x000f0000 @ Mask for ID
330 .long PMD_TYPE_SECT | \
331 PMD_SECT_AP_WRITE | \
334 .long PMD_TYPE_SECT | \
336 PMD_SECT_AP_WRITE | \
341 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
343 .long v7_processor_functions
347 .size __v7_proc_info, . - __v7_proc_info