141906eae26057b10e145c07ef194438dec71e51
[sfrench/cifs-2.6.git] / arch / arm / mm / proc-arm6_7.S
1 /*
2  *  linux/arch/arm/mm/proc-arm6,7.S
3  *
4  *  Copyright (C) 1997-2000 Russell King
5  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  *  These are the low level assembler for performing cache and TLB
12  *  functions on the ARM610 & ARM710.
13  */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/pgtable.h>
21 #include <asm/ptrace.h>
22
23 #include "proc-macros.S"
24
25 ENTRY(cpu_arm6_dcache_clean_area)
26 ENTRY(cpu_arm7_dcache_clean_area)
27                 mov     pc, lr
28
29 /*
30  * Function: arm6_7_data_abort ()
31  *
32  * Params  : r2 = pt_regs
33  *         : r4 = aborted context pc
34  *         : r5 = aborted context psr
35  *
36  * Purpose : obtain information about current aborted instruction
37  *
38  * Returns : r0 = address of abort
39  *         : r1 = FSR
40  */
41
42 ENTRY(cpu_arm7_data_abort)
43         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
44         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
45         ldr     r8, [r4]                        @ read arm instruction
46         tst     r8, #1 << 20                    @ L = 0 -> write?
47         orreq   r1, r1, #1 << 11                @ yes.
48         and     r7, r8, #15 << 24
49         add     pc, pc, r7, lsr #22             @ Now branch to the relevant processing routine
50         nop
51
52 /* 0 */ b       .data_unknown
53 /* 1 */ b       do_DataAbort                    @ swp
54 /* 2 */ b       .data_unknown
55 /* 3 */ b       .data_unknown
56 /* 4 */ b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
57 /* 5 */ b       .data_arm_lateldrpreconst       @ ldr   rd, [rn, #m]
58 /* 6 */ b       .data_arm_lateldrpostreg        @ ldr   rd, [rn], rm
59 /* 7 */ b       .data_arm_lateldrprereg         @ ldr   rd, [rn, rm]
60 /* 8 */ b       .data_arm_ldmstm                @ ldm*a rn, <rlist>
61 /* 9 */ b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
62 /* a */ b       .data_unknown
63 /* b */ b       .data_unknown
64 /* c */ b       do_DataAbort                    @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
65 /* d */ b       do_DataAbort                    @ ldc   rd, [rn, #m]
66 /* e */ b       .data_unknown
67 /* f */
68 .data_unknown:  @ Part of jumptable
69         mov     r0, r4
70         mov     r1, r8
71         b       baddataabort
72
73 ENTRY(cpu_arm6_data_abort)
74         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
75         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
76         ldr     r8, [r4]                        @ read arm instruction
77         tst     r8, #1 << 20                    @ L = 0 -> write?
78         orreq   r1, r1, #1 << 11                @ yes.
79         and     r7, r8, #14 << 24
80         teq     r7, #8 << 24                    @ was it ldm/stm
81         bne     do_DataAbort
82
83 .data_arm_ldmstm:
84         tst     r8, #1 << 21                    @ check writeback bit
85         beq     do_DataAbort                    @ no writeback -> no fixup
86         mov     r7, #0x11
87         orr     r7, r7, #0x1100
88         and     r6, r8, r7
89         and     r9, r8, r7, lsl #1
90         add     r6, r6, r9, lsr #1
91         and     r9, r8, r7, lsl #2
92         add     r6, r6, r9, lsr #2
93         and     r9, r8, r7, lsl #3
94         add     r6, r6, r9, lsr #3
95         add     r6, r6, r6, lsr #8
96         add     r6, r6, r6, lsr #4
97         and     r6, r6, #15                     @ r6 = no. of registers to transfer.
98         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
99         ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
100         tst     r8, #1 << 23                    @ Check U bit
101         subne   r7, r7, r6, lsl #2              @ Undo increment
102         addeq   r7, r7, r6, lsl #2              @ Undo decrement
103         str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
104         b       do_DataAbort
105
106 .data_arm_apply_r6_and_rn:
107         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
108         ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
109         tst     r8, #1 << 23                    @ Check U bit
110         subne   r7, r7, r6                      @ Undo incrmenet
111         addeq   r7, r7, r6                      @ Undo decrement
112         str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
113         b       do_DataAbort
114
115 .data_arm_lateldrpreconst:
116         tst     r8, #1 << 21                    @ check writeback bit
117         beq     do_DataAbort                    @ no writeback -> no fixup
118 .data_arm_lateldrpostconst:
119         movs    r9, r8, lsl #20                 @ Get offset
120         beq     do_DataAbort                    @ zero -> no fixup
121         and     r5, r8, #15 << 16               @ Extract 'n' from instruction
122         ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
123         tst     r8, #1 << 23                    @ Check U bit
124         subne   r7, r7, r9, lsr #20             @ Undo increment
125         addeq   r7, r7, r9, lsr #20             @ Undo decrement
126         str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
127         b       do_DataAbort
128
129 .data_arm_lateldrprereg:
130         tst     r8, #1 << 21                    @ check writeback bit
131         beq     do_DataAbort                    @ no writeback -> no fixup
132 .data_arm_lateldrpostreg:
133         and     r7, r8, #15                     @ Extract 'm' from instruction
134         ldr     r6, [r2, r7, lsl #2]            @ Get register 'Rm'
135         mov     r5, r8, lsr #7                  @ get shift count
136         ands    r5, r5, #31
137         and     r7, r8, #0x70                   @ get shift type
138         orreq   r7, r7, #8                      @ shift count = 0
139         add     pc, pc, r7
140         nop
141
142         mov     r6, r6, lsl r5                  @ 0: LSL #!0
143         b       .data_arm_apply_r6_and_rn
144         b       .data_arm_apply_r6_and_rn       @ 1: LSL #0
145         nop
146         b       .data_unknown                   @ 2: MUL?
147         nop
148         b       .data_unknown                   @ 3: MUL?
149         nop
150         mov     r6, r6, lsr r5                  @ 4: LSR #!0
151         b       .data_arm_apply_r6_and_rn
152         mov     r6, r6, lsr #32                 @ 5: LSR #32
153         b       .data_arm_apply_r6_and_rn
154         b       .data_unknown                   @ 6: MUL?
155         nop
156         b       .data_unknown                   @ 7: MUL?
157         nop
158         mov     r6, r6, asr r5                  @ 8: ASR #!0
159         b       .data_arm_apply_r6_and_rn
160         mov     r6, r6, asr #32                 @ 9: ASR #32
161         b       .data_arm_apply_r6_and_rn
162         b       .data_unknown                   @ A: MUL?
163         nop
164         b       .data_unknown                   @ B: MUL?
165         nop
166         mov     r6, r6, ror r5                  @ C: ROR #!0
167         b       .data_arm_apply_r6_and_rn
168         mov     r6, r6, rrx                     @ D: RRX
169         b       .data_arm_apply_r6_and_rn
170         b       .data_unknown                   @ E: MUL?
171         nop
172         b       .data_unknown                   @ F: MUL?
173
174 /*
175  * Function: arm6_7_proc_init (void)
176  *         : arm6_7_proc_fin (void)
177  *
178  * Notes   : This processor does not require these
179  */
180 ENTRY(cpu_arm6_proc_init)
181 ENTRY(cpu_arm7_proc_init)
182                 mov     pc, lr
183
184 ENTRY(cpu_arm6_proc_fin)
185 ENTRY(cpu_arm7_proc_fin)
186                 mov     r0, #0x31                       @ ....S..DP...M
187                 mcr     p15, 0, r0, c1, c0, 0           @ disable caches
188                 mov     pc, lr
189
190 ENTRY(cpu_arm6_do_idle)
191 ENTRY(cpu_arm7_do_idle)
192                 mov     pc, lr
193
194 /*
195  * Function: arm6_7_switch_mm(unsigned long pgd_phys)
196  * Params  : pgd_phys   Physical address of page table
197  * Purpose : Perform a task switch, saving the old processes state, and restoring
198  *           the new.
199  */
200 ENTRY(cpu_arm6_switch_mm)
201 ENTRY(cpu_arm7_switch_mm)
202 #ifdef CONFIG_MMU
203                 mov     r1, #0
204                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
205                 mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
206                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
207 #endif
208                 mov     pc, lr
209
210 /*
211  * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
212  * Params  : r0 = Address to set
213  *         : r1 = value to set
214  * Purpose : Set a PTE and flush it out of any WB cache
215  */
216         .align  5
217 ENTRY(cpu_arm6_set_pte_ext)
218 ENTRY(cpu_arm7_set_pte_ext)
219 #ifdef CONFIG_MMU
220         armv3_set_pte_ext wc_disable=0
221 #endif /* CONFIG_MMU */
222         mov     pc, lr
223
224 /*
225  * Function: _arm6_7_reset
226  * Params  : r0 = address to jump to
227  * Notes   : This sets up everything for a reset
228  */
229 ENTRY(cpu_arm6_reset)
230 ENTRY(cpu_arm7_reset)
231                 mov     r1, #0
232                 mcr     p15, 0, r1, c7, c0, 0           @ flush cache
233 #ifdef CONFIG_MMU
234                 mcr     p15, 0, r1, c5, c0, 0           @ flush TLB
235 #endif
236                 mov     r1, #0x30
237                 mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
238                 mov     pc, r0
239
240                 __CPUINIT
241
242                 .type   __arm6_setup, #function
243 __arm6_setup:   mov     r0, #0
244                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
245 #ifdef CONFIG_MMU
246                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
247                 mov     r0, #0x3d                       @ . ..RS BLDP WCAM
248                 orr     r0, r0, #0x100                  @ . ..01 0011 1101
249 #else
250                 mov     r0, #0x3c                       @ . ..RS BLDP WCA.
251 #endif
252                 mov     pc, lr
253                 .size   __arm6_setup, . - __arm6_setup
254
255                 .type   __arm7_setup, #function
256 __arm7_setup:   mov     r0, #0
257                 mcr     p15, 0, r0, c7, c0              @ flush caches on v3
258 #ifdef CONFIG_MMU
259                 mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
260                 mcr     p15, 0, r0, c3, c0              @ load domain access register
261                 mov     r0, #0x7d                       @ . ..RS BLDP WCAM
262                 orr     r0, r0, #0x100                  @ . ..01 0111 1101
263 #else
264                 mov     r0, #0x7c                       @ . ..RS BLDP WCA.
265 #endif
266                 mov     pc, lr
267                 .size   __arm7_setup, . - __arm7_setup
268
269                 __INITDATA
270
271 /*
272  * Purpose : Function pointers used to access above functions - all calls
273  *           come through these
274  */
275                 .type   arm6_processor_functions, #object
276 ENTRY(arm6_processor_functions)
277                 .word   cpu_arm6_data_abort
278                 .word   legacy_pabort
279                 .word   cpu_arm6_proc_init
280                 .word   cpu_arm6_proc_fin
281                 .word   cpu_arm6_reset
282                 .word   cpu_arm6_do_idle
283                 .word   cpu_arm6_dcache_clean_area
284                 .word   cpu_arm6_switch_mm
285                 .word   cpu_arm6_set_pte_ext
286                 .word   0
287                 .word   0
288                 .word   0
289                 .size   arm6_processor_functions, . - arm6_processor_functions
290
291 /*
292  * Purpose : Function pointers used to access above functions - all calls
293  *           come through these
294  */
295                 .type   arm7_processor_functions, #object
296 ENTRY(arm7_processor_functions)
297                 .word   cpu_arm7_data_abort
298                 .word   legacy_pabort
299                 .word   cpu_arm7_proc_init
300                 .word   cpu_arm7_proc_fin
301                 .word   cpu_arm7_reset
302                 .word   cpu_arm7_do_idle
303                 .word   cpu_arm7_dcache_clean_area
304                 .word   cpu_arm7_switch_mm
305                 .word   cpu_arm7_set_pte_ext
306                 .word   0
307                 .word   0
308                 .word   0
309                 .size   arm7_processor_functions, . - arm7_processor_functions
310
311                 .section ".rodata"
312
313                 .type   cpu_arch_name, #object
314 cpu_arch_name:  .asciz  "armv3"
315                 .size   cpu_arch_name, . - cpu_arch_name
316
317                 .type   cpu_elf_name, #object
318 cpu_elf_name:   .asciz  "v3"
319                 .size   cpu_elf_name, . - cpu_elf_name
320
321                 .type   cpu_arm6_name, #object
322 cpu_arm6_name:  .asciz  "ARM6"
323                 .size   cpu_arm6_name, . - cpu_arm6_name
324
325                 .type   cpu_arm610_name, #object
326 cpu_arm610_name:
327                 .asciz  "ARM610"
328                 .size   cpu_arm610_name, . - cpu_arm610_name
329
330                 .type   cpu_arm7_name, #object
331 cpu_arm7_name:  .asciz  "ARM7"
332                 .size   cpu_arm7_name, . - cpu_arm7_name
333
334                 .type   cpu_arm710_name, #object
335 cpu_arm710_name:
336                 .asciz  "ARM710"
337                 .size   cpu_arm710_name, . - cpu_arm710_name
338
339                 .align
340
341                 .section ".proc.info.init", #alloc, #execinstr
342
343                 .type   __arm6_proc_info, #object
344 __arm6_proc_info:
345                 .long   0x41560600
346                 .long   0xfffffff0
347                 .long   0x00000c1e
348                 .long   PMD_TYPE_SECT | \
349                         PMD_BIT4 | \
350                         PMD_SECT_AP_WRITE | \
351                         PMD_SECT_AP_READ
352                 b       __arm6_setup
353                 .long   cpu_arch_name
354                 .long   cpu_elf_name
355                 .long   HWCAP_SWP | HWCAP_26BIT
356                 .long   cpu_arm6_name
357                 .long   arm6_processor_functions
358                 .long   v3_tlb_fns
359                 .long   v3_user_fns
360                 .long   v3_cache_fns
361                 .size   __arm6_proc_info, . - __arm6_proc_info
362
363                 .type   __arm610_proc_info, #object
364 __arm610_proc_info:
365                 .long   0x41560610
366                 .long   0xfffffff0
367                 .long   0x00000c1e
368                 .long   PMD_TYPE_SECT | \
369                         PMD_BIT4 | \
370                         PMD_SECT_AP_WRITE | \
371                         PMD_SECT_AP_READ
372                 b       __arm6_setup
373                 .long   cpu_arch_name
374                 .long   cpu_elf_name
375                 .long   HWCAP_SWP | HWCAP_26BIT
376                 .long   cpu_arm610_name
377                 .long   arm6_processor_functions
378                 .long   v3_tlb_fns
379                 .long   v3_user_fns
380                 .long   v3_cache_fns
381                 .size   __arm610_proc_info, . - __arm610_proc_info
382
383                 .type   __arm7_proc_info, #object
384 __arm7_proc_info:
385                 .long   0x41007000
386                 .long   0xffffff00
387                 .long   0x00000c1e
388                 .long   PMD_TYPE_SECT | \
389                         PMD_BIT4 | \
390                         PMD_SECT_AP_WRITE | \
391                         PMD_SECT_AP_READ
392                 b       __arm7_setup
393                 .long   cpu_arch_name
394                 .long   cpu_elf_name
395                 .long   HWCAP_SWP | HWCAP_26BIT
396                 .long   cpu_arm7_name
397                 .long   arm7_processor_functions
398                 .long   v3_tlb_fns
399                 .long   v3_user_fns
400                 .long   v3_cache_fns
401                 .size   __arm7_proc_info, . - __arm7_proc_info
402
403                 .type   __arm710_proc_info, #object
404 __arm710_proc_info:
405                 .long   0x41007100
406                 .long   0xfff8ff00
407                 .long   PMD_TYPE_SECT | \
408                         PMD_SECT_BUFFERABLE | \
409                         PMD_SECT_CACHEABLE | \
410                         PMD_BIT4 | \
411                         PMD_SECT_AP_WRITE | \
412                         PMD_SECT_AP_READ
413                 .long   PMD_TYPE_SECT | \
414                         PMD_BIT4 | \
415                         PMD_SECT_AP_WRITE | \
416                         PMD_SECT_AP_READ
417                 b       __arm7_setup
418                 .long   cpu_arch_name
419                 .long   cpu_elf_name
420                 .long   HWCAP_SWP | HWCAP_26BIT
421                 .long   cpu_arm710_name
422                 .long   arm7_processor_functions
423                 .long   v3_tlb_fns
424                 .long   v3_user_fns
425                 .long   v3_cache_fns
426                 .size   __arm710_proc_info, . - __arm710_proc_info