arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/mman.h>
  16 #include <linux/nodemask.h>
  17 #include <linux/sort.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/sections.h>
  21 #include <asm/cachetype.h>
  22 #include <asm/setup.h>
  23 #include <asm/sizes.h>
  24 #include <asm/smp_plat.h>
  25 #include <asm/tlb.h>
  26 #include <asm/highmem.h>
  27
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30
  31 #include "mm.h"
  32
  33 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  34
  35 /*
  36  * empty_zero_page is a special page that is used for
  37  * zero-initialized data and COW.
  38  */
  39 struct page *empty_zero_page;
  40 EXPORT_SYMBOL(empty_zero_page);
  41
  42 /*
  43  * The pmd table for the upper-most set of pages.
  44  */
  45 pmd_t *top_pmd;
  46
  47 #define CPOLICY_UNCACHED        0
  48 #define CPOLICY_BUFFERED        1
  49 #define CPOLICY_WRITETHROUGH    2
  50 #define CPOLICY_WRITEBACK       3
  51 #define CPOLICY_WRITEALLOC      4
  52
  53 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  54 static unsigned int ecc_mask __initdata = 0;
  55 pgprot_t pgprot_user;
  56 pgprot_t pgprot_kernel;
  57
  58 EXPORT_SYMBOL(pgprot_user);
  59 EXPORT_SYMBOL(pgprot_kernel);
  60
  61 struct cachepolicy {
  62         const char      policy[16];
  63         unsigned int    cr_mask;
  64         unsigned int    pmd;
  65         unsigned int    pte;
  66 };
  67
  68 static struct cachepolicy cache_policies[] __initdata = {
  69         {
  70                 .policy         = "uncached",
  71                 .cr_mask        = CR_W|CR_C,
  72                 .pmd            = PMD_SECT_UNCACHED,
  73                 .pte            = L_PTE_MT_UNCACHED,
  74         }, {
  75                 .policy         = "buffered",
  76                 .cr_mask        = CR_C,
  77                 .pmd            = PMD_SECT_BUFFERED,
  78                 .pte            = L_PTE_MT_BUFFERABLE,
  79         }, {
  80                 .policy         = "writethrough",
  81                 .cr_mask        = 0,
  82                 .pmd            = PMD_SECT_WT,
  83                 .pte            = L_PTE_MT_WRITETHROUGH,
  84         }, {
  85                 .policy         = "writeback",
  86                 .cr_mask        = 0,
  87                 .pmd            = PMD_SECT_WB,
  88                 .pte            = L_PTE_MT_WRITEBACK,
  89         }, {
  90                 .policy         = "writealloc",
  91                 .cr_mask        = 0,
  92                 .pmd            = PMD_SECT_WBWA,
  93                 .pte            = L_PTE_MT_WRITEALLOC,
  94         }
  95 };
  96
  97 /*
  98  * These are useful for identifying cache coherency
  99  * problems by allowing the cache or the cache and
 100  * writebuffer to be turned off.  (Note: the write
 101  * buffer should not be on and the cache off).
 102  */
 103 static int __init early_cachepolicy(char *p)
 104 {
 105         int i;
 106
 107         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 108                 int len = strlen(cache_policies[i].policy);
 109
 110                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 111                         cachepolicy = i;
 112                         cr_alignment &= ~cache_policies[i].cr_mask;
 113                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 114                         break;
 115                 }
 116         }
 117         if (i == ARRAY_SIZE(cache_policies))
 118                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 119         /*
 120          * This restriction is partly to do with the way we boot; it is
 121          * unpredictable to have memory mapped using two different sets of
 122          * memory attributes (shared, type, and cache attribs).  We can not
 123          * change these attributes once the initial assembly has setup the
 124          * page tables.
 125          */
 126         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 127                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 128                 cachepolicy = CPOLICY_WRITEBACK;
 129         }
 130         flush_cache_all();
 131         set_cr(cr_alignment);
 132         return 0;
 133 }
 134 early_param("cachepolicy", early_cachepolicy);
 135
 136 static int __init early_nocache(char *__unused)
 137 {
 138         char *p = "buffered";
 139         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 140         early_cachepolicy(p);
 141         return 0;
 142 }
 143 early_param("nocache", early_nocache);
 144
 145 static int __init early_nowrite(char *__unused)
 146 {
 147         char *p = "uncached";
 148         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 149         early_cachepolicy(p);
 150         return 0;
 151 }
 152 early_param("nowb", early_nowrite);
 153
 154 static int __init early_ecc(char *p)
 155 {
 156         if (memcmp(p, "on", 2) == 0)
 157                 ecc_mask = PMD_PROTECTION;
 158         else if (memcmp(p, "off", 3) == 0)
 159                 ecc_mask = 0;
 160         return 0;
 161 }
 162 early_param("ecc", early_ecc);
 163
 164 static int __init noalign_setup(char *__unused)
 165 {
 166         cr_alignment &= ~CR_A;
 167         cr_no_alignment &= ~CR_A;
 168         set_cr(cr_alignment);
 169         return 1;
 170 }
 171 __setup("noalign", noalign_setup);
 172
 173 #ifndef CONFIG_SMP
 174 void adjust_cr(unsigned long mask, unsigned long set)
 175 {
 176         unsigned long flags;
 177
 178         mask &= ~CR_A;
 179
 180         set &= mask;
 181
 182         local_irq_save(flags);
 183
 184         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 185         cr_alignment = (cr_alignment & ~mask) | set;
 186
 187         set_cr((get_cr() & ~mask) | set);
 188
 189         local_irq_restore(flags);
 190 }
 191 #endif
 192
 193 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
 194 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 195
 196 static struct mem_type mem_types[] = {
 197         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 198                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 199                                   L_PTE_SHARED,
 200                 .prot_l1        = PMD_TYPE_TABLE,
 201                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 202                 .domain         = DOMAIN_IO,
 203         },
 204         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 205                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 206                 .prot_l1        = PMD_TYPE_TABLE,
 207                 .prot_sect      = PROT_SECT_DEVICE,
 208                 .domain         = DOMAIN_IO,
 209         },
 210         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 211                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 212                 .prot_l1        = PMD_TYPE_TABLE,
 213                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 214                 .domain         = DOMAIN_IO,
 215         },
 216         [MT_DEVICE_WC] = {      /* ioremap_wc */
 217                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 218                 .prot_l1        = PMD_TYPE_TABLE,
 219                 .prot_sect      = PROT_SECT_DEVICE,
 220                 .domain         = DOMAIN_IO,
 221         },
 222         [MT_UNCACHED] = {
 223                 .prot_pte       = PROT_PTE_DEVICE,
 224                 .prot_l1        = PMD_TYPE_TABLE,
 225                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 226                 .domain         = DOMAIN_IO,
 227         },
 228         [MT_CACHECLEAN] = {
 229                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 230                 .domain    = DOMAIN_KERNEL,
 231         },
 232         [MT_MINICLEAN] = {
 233                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 234                 .domain    = DOMAIN_KERNEL,
 235         },
 236         [MT_LOW_VECTORS] = {
 237                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 238                                 L_PTE_EXEC,
 239                 .prot_l1   = PMD_TYPE_TABLE,
 240                 .domain    = DOMAIN_USER,
 241         },
 242         [MT_HIGH_VECTORS] = {
 243                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 244                                 L_PTE_USER | L_PTE_EXEC,
 245                 .prot_l1   = PMD_TYPE_TABLE,
 246                 .domain    = DOMAIN_USER,
 247         },
 248         [MT_MEMORY] = {
 249                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 250                 .domain    = DOMAIN_KERNEL,
 251         },
 252         [MT_ROM] = {
 253                 .prot_sect = PMD_TYPE_SECT,
 254                 .domain    = DOMAIN_KERNEL,
 255         },
 256         [MT_MEMORY_NONCACHED] = {
 257                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 258                 .domain    = DOMAIN_KERNEL,
 259         },
 260 };
 261
 262 const struct mem_type *get_mem_type(unsigned int type)
 263 {
 264         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 265 }
 266 EXPORT_SYMBOL(get_mem_type);
 267
 268 /*
 269  * Adjust the PMD section entries according to the CPU in use.
 270  */
 271 static void __init build_mem_type_table(void)
 272 {
 273         struct cachepolicy *cp;
 274         unsigned int cr = get_cr();
 275         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 276         int cpu_arch = cpu_architecture();
 277         int i;
 278
 279         if (cpu_arch < CPU_ARCH_ARMv6) {
 280 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 281                 if (cachepolicy > CPOLICY_BUFFERED)
 282                         cachepolicy = CPOLICY_BUFFERED;
 283 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 284                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 285                         cachepolicy = CPOLICY_WRITETHROUGH;
 286 #endif
 287         }
 288         if (cpu_arch < CPU_ARCH_ARMv5) {
 289                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 290                         cachepolicy = CPOLICY_WRITEBACK;
 291                 ecc_mask = 0;
 292         }
 293 #ifdef CONFIG_SMP
 294         cachepolicy = CPOLICY_WRITEALLOC;
 295 #endif
 296
 297         /*
 298          * Strip out features not present on earlier architectures.
 299          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 300          * without extended page tables don't have the 'Shared' bit.
 301          */
 302         if (cpu_arch < CPU_ARCH_ARMv5)
 303                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 304                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 305         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 306                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 307                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 308
 309         /*
 310          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 311          * "update-able on write" bit on ARM610).  However, Xscale and
 312          * Xscale3 require this bit to be cleared.
 313          */
 314         if (cpu_is_xscale() || cpu_is_xsc3()) {
 315                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 316                         mem_types[i].prot_sect &= ~PMD_BIT4;
 317                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 318                 }
 319         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 320                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 321                         if (mem_types[i].prot_l1)
 322                                 mem_types[i].prot_l1 |= PMD_BIT4;
 323                         if (mem_types[i].prot_sect)
 324                                 mem_types[i].prot_sect |= PMD_BIT4;
 325                 }
 326         }
 327
 328         /*
 329          * Mark the device areas according to the CPU/architecture.
 330          */
 331         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 332                 if (!cpu_is_xsc3()) {
 333                         /*
 334                          * Mark device regions on ARMv6+ as execute-never
 335                          * to prevent speculative instruction fetches.
 336                          */
 337                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 338                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 339                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 340                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 341                 }
 342                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 343                         /*
 344                          * For ARMv7 with TEX remapping,
 345                          * - shared device is SXCB=1100
 346                          * - nonshared device is SXCB=0100
 347                          * - write combine device mem is SXCB=0001
 348                          * (Uncached Normal memory)
 349                          */
 350                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 351                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 352                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 353                 } else if (cpu_is_xsc3()) {
 354                         /*
 355                          * For Xscale3,
 356                          * - shared device is TEXCB=00101
 357                          * - nonshared device is TEXCB=01000
 358                          * - write combine device mem is TEXCB=00100
 359                          * (Inner/Outer Uncacheable in xsc3 parlance)
 360                          */
 361                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 362                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 363                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 364                 } else {
 365                         /*
 366                          * For ARMv6 and ARMv7 without TEX remapping,
 367                          * - shared device is TEXCB=00001
 368                          * - nonshared device is TEXCB=01000
 369                          * - write combine device mem is TEXCB=00100
 370                          * (Uncached Normal in ARMv6 parlance).
 371                          */
 372                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 373                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 374                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 375                 }
 376         } else {
 377                 /*
 378                  * On others, write combining is "Uncached/Buffered"
 379                  */
 380                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 381         }
 382
 383         /*
 384          * Now deal with the memory-type mappings
 385          */
 386         cp = &cache_policies[cachepolicy];
 387         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 388
 389 #ifndef CONFIG_SMP
 390         /*
 391          * Only use write-through for non-SMP systems
 392          */
 393         if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 394                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 395 #endif
 396
 397         /*
 398          * Enable CPU-specific coherency if supported.
 399          * (Only available on XSC3 at the moment.)
 400          */
 401         if (arch_is_coherent() && cpu_is_xsc3())
 402                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 403
 404         /*
 405          * ARMv6 and above have extended page tables.
 406          */
 407         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 408                 /*
 409                  * Mark cache clean areas and XIP ROM read only
 410                  * from SVC mode and no access from userspace.
 411                  */
 412                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 413                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 414                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 415
 416 #ifdef CONFIG_SMP
 417                 /*
 418                  * Mark memory with the "shared" attribute for SMP systems
 419                  */
 420                 user_pgprot |= L_PTE_SHARED;
 421                 kern_pgprot |= L_PTE_SHARED;
 422                 vecs_pgprot |= L_PTE_SHARED;
 423                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 424                 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 425                 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 426                 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 427                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 428                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 429 #endif
 430         }
 431
 432         /*
 433          * Non-cacheable Normal - intended for memory areas that must
 434          * not cause dirty cache line writebacks when used
 435          */
 436         if (cpu_arch >= CPU_ARCH_ARMv6) {
 437                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 438                         /* Non-cacheable Normal is XCB = 001 */
 439                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 440                                 PMD_SECT_BUFFERED;
 441                 } else {
 442                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 443                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 444                                 PMD_SECT_TEX(1);
 445                 }
 446         } else {
 447                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 448         }
 449
 450         for (i = 0; i < 16; i++) {
 451                 unsigned long v = pgprot_val(protection_map[i]);
 452                 protection_map[i] = __pgprot(v | user_pgprot);
 453         }
 454
 455         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 456         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 457
 458         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 459         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 460                                  L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
 461
 462         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 463         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 464         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 465         mem_types[MT_ROM].prot_sect |= cp->pmd;
 466
 467         switch (cp->pmd) {
 468         case PMD_SECT_WT:
 469                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 470                 break;
 471         case PMD_SECT_WB:
 472         case PMD_SECT_WBWA:
 473                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 474                 break;
 475         }
 476         printk("Memory policy: ECC %sabled, Data cache %s\n",
 477                 ecc_mask ? "en" : "dis", cp->policy);
 478
 479         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 480                 struct mem_type *t = &mem_types[i];
 481                 if (t->prot_l1)
 482                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 483                 if (t->prot_sect)
 484                         t->prot_sect |= PMD_DOMAIN(t->domain);
 485         }
 486 }
 487
 488 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 489
 490 static void __init *early_alloc(unsigned long sz)
 491 {
 492         return alloc_bootmem_low_pages(sz);
 493 }
 494
 495 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 496 {
 497         if (pmd_none(*pmd)) {
 498                 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
 499                 __pmd_populate(pmd, __pa(pte) | prot);
 500         }
 501         BUG_ON(pmd_bad(*pmd));
 502         return pte_offset_kernel(pmd, addr);
 503 }
 504
 505 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 506                                   unsigned long end, unsigned long pfn,
 507                                   const struct mem_type *type)
 508 {
 509         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 510         do {
 511                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 512                 pfn++;
 513         } while (pte++, addr += PAGE_SIZE, addr != end);
 514 }
 515
 516 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 517                                       unsigned long end, unsigned long phys,
 518                                       const struct mem_type *type)
 519 {
 520         pmd_t *pmd = pmd_offset(pgd, addr);
 521
 522         /*
 523          * Try a section mapping - end, addr and phys must all be aligned
 524          * to a section boundary.  Note that PMDs refer to the individual
 525          * L1 entries, whereas PGDs refer to a group of L1 entries making
 526          * up one logical pointer to an L2 table.
 527          */
 528         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 529                 pmd_t *p = pmd;
 530
 531                 if (addr & SECTION_SIZE)
 532                         pmd++;
 533
 534                 do {
 535                         *pmd = __pmd(phys | type->prot_sect);
 536                         phys += SECTION_SIZE;
 537                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 538
 539                 flush_pmd_entry(p);
 540         } else {
 541                 /*
 542                  * No need to loop; pte's aren't interested in the
 543                  * individual L1 entries.
 544                  */
 545                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 546         }
 547 }
 548
 549 static void __init create_36bit_mapping(struct map_desc *md,
 550                                         const struct mem_type *type)
 551 {
 552         unsigned long phys, addr, length, end;
 553         pgd_t *pgd;
 554
 555         addr = md->virtual;
 556         phys = (unsigned long)__pfn_to_phys(md->pfn);
 557         length = PAGE_ALIGN(md->length);
 558
 559         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 560                 printk(KERN_ERR "MM: CPU does not support supersection "
 561                        "mapping for 0x%08llx at 0x%08lx\n",
 562                        __pfn_to_phys((u64)md->pfn), addr);
 563                 return;
 564         }
 565
 566         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 567          *      Since domain assignments can in fact be arbitrary, the
 568          *      'domain == 0' check below is required to insure that ARMv6
 569          *      supersections are only allocated for domain 0 regardless
 570          *      of the actual domain assignments in use.
 571          */
 572         if (type->domain) {
 573                 printk(KERN_ERR "MM: invalid domain in supersection "
 574                        "mapping for 0x%08llx at 0x%08lx\n",
 575                        __pfn_to_phys((u64)md->pfn), addr);
 576                 return;
 577         }
 578
 579         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 580                 printk(KERN_ERR "MM: cannot create mapping for "
 581                        "0x%08llx at 0x%08lx invalid alignment\n",
 582                        __pfn_to_phys((u64)md->pfn), addr);
 583                 return;
 584         }
 585
 586         /*
 587          * Shift bits [35:32] of address into bits [23:20] of PMD
 588          * (See ARMv6 spec).
 589          */
 590         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 591
 592         pgd = pgd_offset_k(addr);
 593         end = addr + length;
 594         do {
 595                 pmd_t *pmd = pmd_offset(pgd, addr);
 596                 int i;
 597
 598                 for (i = 0; i < 16; i++)
 599                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 600
 601                 addr += SUPERSECTION_SIZE;
 602                 phys += SUPERSECTION_SIZE;
 603                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 604         } while (addr != end);
 605 }
 606
 607 /*
 608  * Create the page directory entries and any necessary
 609  * page tables for the mapping specified by `md'.  We
 610  * are able to cope here with varying sizes and address
 611  * offsets, and we take full advantage of sections and
 612  * supersections.
 613  */
 614 static void __init create_mapping(struct map_desc *md)
 615 {
 616         unsigned long phys, addr, length, end;
 617         const struct mem_type *type;
 618         pgd_t *pgd;
 619
 620         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 621                 printk(KERN_WARNING "BUG: not creating mapping for "
 622                        "0x%08llx at 0x%08lx in user region\n",
 623                        __pfn_to_phys((u64)md->pfn), md->virtual);
 624                 return;
 625         }
 626
 627         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 628             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 629                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
 630                        "overlaps vmalloc space\n",
 631                        __pfn_to_phys((u64)md->pfn), md->virtual);
 632         }
 633
 634         type = &mem_types[md->type];
 635
 636         /*
 637          * Catch 36-bit addresses
 638          */
 639         if (md->pfn >= 0x100000) {
 640                 create_36bit_mapping(md, type);
 641                 return;
 642         }
 643
 644         addr = md->virtual & PAGE_MASK;
 645         phys = (unsigned long)__pfn_to_phys(md->pfn);
 646         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 647
 648         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 649                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 650                        "be mapped using pages, ignoring.\n",
 651                        __pfn_to_phys(md->pfn), addr);
 652                 return;
 653         }
 654
 655         pgd = pgd_offset_k(addr);
 656         end = addr + length;
 657         do {
 658                 unsigned long next = pgd_addr_end(addr, end);
 659
 660                 alloc_init_section(pgd, addr, next, phys, type);
 661
 662                 phys += next - addr;
 663                 addr = next;
 664         } while (pgd++, addr != end);
 665 }
 666
 667 /*
 668  * Create the architecture specific mappings
 669  */
 670 void __init iotable_init(struct map_desc *io_desc, int nr)
 671 {
 672         int i;
 673
 674         for (i = 0; i < nr; i++)
 675                 create_mapping(io_desc + i);
 676 }
 677
 678 static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M);
 679
 680 /*
 681  * vmalloc=size forces the vmalloc area to be exactly 'size'
 682  * bytes. This can be used to increase (or decrease) the vmalloc
 683  * area - the default is 128m.
 684  */
 685 static int __init early_vmalloc(char *arg)
 686 {
 687         unsigned long vmalloc_reserve = memparse(arg, NULL);
 688
 689         if (vmalloc_reserve < SZ_16M) {
 690                 vmalloc_reserve = SZ_16M;
 691                 printk(KERN_WARNING
 692                         "vmalloc area too small, limiting to %luMB\n",
 693                         vmalloc_reserve >> 20);
 694         }
 695
 696         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 697                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 698                 printk(KERN_WARNING
 699                         "vmalloc area is too big, limiting to %luMB\n",
 700                         vmalloc_reserve >> 20);
 701         }
 702
 703         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 704         return 0;
 705 }
 706 early_param("vmalloc", early_vmalloc);
 707
 708 static void __init sanity_check_meminfo(void)
 709 {
 710         int i, j, highmem = 0;
 711
 712         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 713                 struct membank *bank = &meminfo.bank[j];
 714                 *bank = meminfo.bank[i];
 715
 716 #ifdef CONFIG_HIGHMEM
 717                 if (__va(bank->start) > vmalloc_min ||
 718                     __va(bank->start) < (void *)PAGE_OFFSET)
 719                         highmem = 1;
 720
 721                 bank->highmem = highmem;
 722
 723                 /*
 724                  * Split those memory banks which are partially overlapping
 725                  * the vmalloc area greatly simplifying things later.
 726                  */
 727                 if (__va(bank->start) < vmalloc_min &&
 728                     bank->size > vmalloc_min - __va(bank->start)) {
 729                         if (meminfo.nr_banks >= NR_BANKS) {
 730                                 printk(KERN_CRIT "NR_BANKS too low, "
 731                                                  "ignoring high memory\n");
 732                         } else {
 733                                 memmove(bank + 1, bank,
 734                                         (meminfo.nr_banks - i) * sizeof(*bank));
 735                                 meminfo.nr_banks++;
 736                                 i++;
 737                                 bank[1].size -= vmalloc_min - __va(bank->start);
 738                                 bank[1].start = __pa(vmalloc_min - 1) + 1;
 739                                 bank[1].highmem = highmem = 1;
 740                                 j++;
 741                         }
 742                         bank->size = vmalloc_min - __va(bank->start);
 743                 }
 744 #else
 745                 bank->highmem = highmem;
 746
 747                 /*
 748                  * Check whether this memory bank would entirely overlap
 749                  * the vmalloc area.
 750                  */
 751                 if (__va(bank->start) >= vmalloc_min ||
 752                     __va(bank->start) < (void *)PAGE_OFFSET) {
 753                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
 754                                "(vmalloc region overlap).\n",
 755                                bank->start, bank->start + bank->size - 1);
 756                         continue;
 757                 }
 758
 759                 /*
 760                  * Check whether this memory bank would partially overlap
 761                  * the vmalloc area.
 762                  */
 763                 if (__va(bank->start + bank->size) > vmalloc_min ||
 764                     __va(bank->start + bank->size) < __va(bank->start)) {
 765                         unsigned long newsize = vmalloc_min - __va(bank->start);
 766                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
 767                                "to -%.8lx (vmalloc region overlap).\n",
 768                                bank->start, bank->start + bank->size - 1,
 769                                bank->start + newsize - 1);
 770                         bank->size = newsize;
 771                 }
 772 #endif
 773                 j++;
 774         }
 775 #ifdef CONFIG_HIGHMEM
 776         if (highmem) {
 777                 const char *reason = NULL;
 778
 779                 if (cache_is_vipt_aliasing()) {
 780                         /*
 781                          * Interactions between kmap and other mappings
 782                          * make highmem support with aliasing VIPT caches
 783                          * rather difficult.
 784                          */
 785                         reason = "with VIPT aliasing cache";
 786 #ifdef CONFIG_SMP
 787                 } else if (tlb_ops_need_broadcast()) {
 788                         /*
 789                          * kmap_high needs to occasionally flush TLB entries,
 790                          * however, if the TLB entries need to be broadcast
 791                          * we may deadlock:
 792                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
 793                          *  flush_tlb_kernel_range->smp_call_function_many
 794                          *   (must not be called with irqs off)
 795                          */
 796                         reason = "without hardware TLB ops broadcasting";
 797 #endif
 798                 }
 799                 if (reason) {
 800                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 801                                 reason);
 802                         while (j > 0 && meminfo.bank[j - 1].highmem)
 803                                 j--;
 804                 }
 805         }
 806 #endif
 807         meminfo.nr_banks = j;
 808 }
 809
 810 static inline void prepare_page_table(void)
 811 {
 812         unsigned long addr;
 813
 814         /*
 815          * Clear out all the mappings below the kernel image.
 816          */
 817         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 818                 pmd_clear(pmd_off_k(addr));
 819
 820 #ifdef CONFIG_XIP_KERNEL
 821         /* The XIP kernel is mapped in the module area -- skip over it */
 822         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 823 #endif
 824         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 825                 pmd_clear(pmd_off_k(addr));
 826
 827         /*
 828          * Clear out all the kernel space mappings, except for the first
 829          * memory bank, up to the end of the vmalloc region.
 830          */
 831         for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
 832              addr < VMALLOC_END; addr += PGDIR_SIZE)
 833                 pmd_clear(pmd_off_k(addr));
 834 }
 835
 836 /*
 837  * Reserve the various regions
 838  */
 839 void __init reserve_special_regions(void)
 840 {
 841         /*
 842          * Register the kernel text and data with bootmem.
 843          * Note that this can only be in node 0.
 844          */
 845 #ifdef CONFIG_XIP_KERNEL
 846         reserve_bootmem(__pa(_data), _end - _data, BOOTMEM_DEFAULT);
 847 #else
 848         reserve_bootmem(__pa(_stext), _end - _stext, BOOTMEM_DEFAULT);
 849 #endif
 850
 851         /*
 852          * Reserve the page tables.  These are already in use,
 853          * and can only be in node 0.
 854          */
 855         reserve_bootmem(__pa(swapper_pg_dir),
 856                         PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
 857
 858 #ifdef CONFIG_SA1111
 859         /*
 860          * Because of the SA1111 DMA bug, we want to preserve our
 861          * precious DMA-able memory...
 862          */
 863         reserve_bootmem(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET,
 864                         BOOTMEM_DEFAULT);
 865 #endif
 866 }
 867
 868 /*
 869  * Set up device the mappings.  Since we clear out the page tables for all
 870  * mappings above VMALLOC_END, we will remove any debug device mappings.
 871  * This means you have to be careful how you debug this function, or any
 872  * called function.  This means you can't use any function or debugging
 873  * method which may touch any device, otherwise the kernel _will_ crash.
 874  */
 875 static void __init devicemaps_init(struct machine_desc *mdesc)
 876 {
 877         struct map_desc map;
 878         unsigned long addr;
 879         void *vectors;
 880
 881         /*
 882          * Allocate the vector page early.
 883          */
 884         vectors = early_alloc(PAGE_SIZE);
 885
 886         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 887                 pmd_clear(pmd_off_k(addr));
 888
 889         /*
 890          * Map the kernel if it is XIP.
 891          * It is always first in the modulearea.
 892          */
 893 #ifdef CONFIG_XIP_KERNEL
 894         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 895         map.virtual = MODULES_VADDR;
 896         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 897         map.type = MT_ROM;
 898         create_mapping(&map);
 899 #endif
 900
 901         /*
 902          * Map the cache flushing regions.
 903          */
 904 #ifdef FLUSH_BASE
 905         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 906         map.virtual = FLUSH_BASE;
 907         map.length = SZ_1M;
 908         map.type = MT_CACHECLEAN;
 909         create_mapping(&map);
 910 #endif
 911 #ifdef FLUSH_BASE_MINICACHE
 912         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 913         map.virtual = FLUSH_BASE_MINICACHE;
 914         map.length = SZ_1M;
 915         map.type = MT_MINICLEAN;
 916         create_mapping(&map);
 917 #endif
 918
 919         /*
 920          * Create a mapping for the machine vectors at the high-vectors
 921          * location (0xffff0000).  If we aren't using high-vectors, also
 922          * create a mapping at the low-vectors virtual address.
 923          */
 924         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
 925         map.virtual = 0xffff0000;
 926         map.length = PAGE_SIZE;
 927         map.type = MT_HIGH_VECTORS;
 928         create_mapping(&map);
 929
 930         if (!vectors_high()) {
 931                 map.virtual = 0;
 932                 map.type = MT_LOW_VECTORS;
 933                 create_mapping(&map);
 934         }
 935
 936         /*
 937          * Ask the machine support to map in the statically mapped devices.
 938          */
 939         if (mdesc->map_io)
 940                 mdesc->map_io();
 941
 942         /*
 943          * Finally flush the caches and tlb to ensure that we're in a
 944          * consistent state wrt the writebuffer.  This also ensures that
 945          * any write-allocated cache lines in the vector page are written
 946          * back.  After this point, we can start to touch devices again.
 947          */
 948         local_flush_tlb_all();
 949         flush_cache_all();
 950 }
 951
 952 static void __init kmap_init(void)
 953 {
 954 #ifdef CONFIG_HIGHMEM
 955         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
 956                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
 957 #endif
 958 }
 959
 960 static inline void map_memory_bank(struct membank *bank)
 961 {
 962         struct map_desc map;
 963
 964         map.pfn = bank_pfn_start(bank);
 965         map.virtual = __phys_to_virt(bank_phys_start(bank));
 966         map.length = bank_phys_size(bank);
 967         map.type = MT_MEMORY;
 968
 969         create_mapping(&map);
 970 }
 971
 972 static void __init map_lowmem(void)
 973 {
 974         struct meminfo *mi = &meminfo;
 975         int i;
 976
 977         /* Map all the lowmem memory banks. */
 978         for (i = 0; i < mi->nr_banks; i++) {
 979                 struct membank *bank = &mi->bank[i];
 980
 981                 if (!bank->highmem)
 982                         map_memory_bank(bank);
 983         }
 984 }
 985
 986 static int __init meminfo_cmp(const void *_a, const void *_b)
 987 {
 988         const struct membank *a = _a, *b = _b;
 989         long cmp = bank_pfn_start(a) - bank_pfn_start(b);
 990         return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
 991 }
 992
 993 /*
 994  * paging_init() sets up the page tables, initialises the zone memory
 995  * maps, and sets up the zero page, bad page and bad page tables.
 996  */
 997 void __init paging_init(struct machine_desc *mdesc)
 998 {
 999         void *zero_page;
1000
1001         sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
1002
1003         build_mem_type_table();
1004         sanity_check_meminfo();
1005         prepare_page_table();
1006         map_lowmem();
1007         bootmem_init(mdesc);
1008         devicemaps_init(mdesc);
1009         kmap_init();
1010
1011         top_pmd = pmd_off_k(0xffff0000);
1012
1013         /* allocate the zero page. */
1014         zero_page = early_alloc(PAGE_SIZE);
1015         empty_zero_page = virt_to_page(zero_page);
1016         __flush_dcache_page(NULL, empty_zero_page);
1017 }
1018
1019 /*
1020  * In order to soft-boot, we need to insert a 1:1 mapping in place of
1021  * the user-mode pages.  This will then ensure that we have predictable
1022  * results when turning the mmu off
1023  */
1024 void setup_mm_for_reboot(char mode)
1025 {
1026         unsigned long base_pmdval;
1027         pgd_t *pgd;
1028         int i;
1029
1030         /*
1031          * We need to access to user-mode page tables here. For kernel threads
1032          * we don't have any user-mode mappings so we use the context that we
1033          * "borrowed".
1034          */
1035         pgd = current->active_mm->pgd;
1036
1037         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1038         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1039                 base_pmdval |= PMD_BIT4;
1040
1041         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1042                 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1043                 pmd_t *pmd;
1044
1045                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1046                 pmd[0] = __pmd(pmdval);
1047                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1048                 flush_pmd_entry(pmd);
1049         }
1050
1051         local_flush_tlb_all();
1052 }