1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/arm/mach-w90x900/include/mach/regs-serial.h
5 * Copyright (c) 2009 Nuvoton technology corporation
9 * Nuvoton Display, LCM Register list
10 * Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11
14 #ifndef __ASM_ARM_W90X900_REGS_LDM_H
15 #define __ASM_ARM_W90X900_REGS_LDM_H
19 /* Display Controller Control/Status Register */
20 #define REG_LCM_DCCS (0x00)
22 #define LCM_DCCS_ENG_RST (1 << 0)
23 #define LCM_DCCS_VA_EN (1 << 1)
24 #define LCM_DCCS_OSD_EN (1 << 2)
25 #define LCM_DCCS_DISP_OUT_EN (1 << 3)
26 #define LCM_DCCS_DISP_INT_EN (1 << 4)
27 #define LCM_DCCS_CMD_ON (1 << 5)
28 #define LCM_DCCS_FIELD_INTR (1 << 6)
29 #define LCM_DCCS_SINGLE (1 << 7)
31 enum LCM_DCCS_VA_SRC {
32 LCM_DCCS_VA_SRC_YUV422 = (0 << 8),
33 LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8),
34 LCM_DCCS_VA_SRC_RGB888 = (2 << 8),
35 LCM_DCCS_VA_SRC_RGB666 = (3 << 8),
36 LCM_DCCS_VA_SRC_RGB565 = (4 << 8),
37 LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8),
38 LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8)
42 /* Display Device Control Register */
43 #define REG_LCM_DEV_CTRL (0x04)
45 enum LCM_DEV_CTRL_SWAP_YCbCr {
46 LCM_DEV_CTRL_SWAP_UYVY = (0 << 1),
47 LCM_DEV_CTRL_SWAP_YUYV = (1 << 1),
48 LCM_DEV_CTRL_SWAP_VYUY = (2 << 1),
49 LCM_DEV_CTRL_SWAP_YVYU = (3 << 1)
52 enum LCM_DEV_CTRL_RGB_SHIFT {
53 LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3),
54 LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3),
55 LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3),
56 LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3)
59 enum LCM_DEV_CTRL_DEVICE {
60 LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5),
61 LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5),
62 LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5),
63 LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5),
64 LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5),
65 LCM_DEV_CTRL_DEVICE_MPU = (7 << 5)
68 #define LCM_DEV_CTRL_LCD_DDA (8)
69 #define LCM_DEV_CTRL_YUV2CCIR (16)
71 enum LCM_DEV_CTRL_LCD_SEL {
72 LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17),
73 LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17),
74 LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17),
75 LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17)
78 enum LCM_DEV_CTRL_FAL_D {
79 LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19),
80 LCM_DEV_CTRL_FAL_D_RISING = (1 << 19),
83 enum LCM_DEV_CTRL_H_POL {
84 LCM_DEV_CTRL_H_POL_LOW = (0 << 20),
85 LCM_DEV_CTRL_H_POL_HIGH = (1 << 20),
88 enum LCM_DEV_CTRL_V_POL {
89 LCM_DEV_CTRL_V_POL_LOW = (0 << 21),
90 LCM_DEV_CTRL_V_POL_HIGH = (1 << 21),
93 enum LCM_DEV_CTRL_VR_LACE {
94 LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22),
95 LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22),
98 enum LCM_DEV_CTRL_LACE {
99 LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23),
100 LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23),
103 enum LCM_DEV_CTRL_RGB_SCALE {
104 LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24),
105 LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24),
106 LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24),
107 LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24),
110 enum LCM_DEV_CTRL_DBWORD {
111 LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26),
112 LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26),
115 enum LCM_DEV_CTRL_MPU68 {
116 LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27),
117 LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27),
120 enum LCM_DEV_CTRL_DE_POL {
121 LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28),
122 LCM_DEV_CTRL_DE_POL_LOW = (1 << 28),
125 #define LCM_DEV_CTRL_CMD16 (29)
126 #define LCM_DEV_CTRL_CM16t18 (30)
127 #define LCM_DEV_CTRL_CMD_LOW (31)
129 /* MPU-Interface LCD Write Command */
130 #define REG_LCM_MPU_CMD (0x08)
132 /* Interrupt Control/Status Register */
133 #define REG_LCM_INT_CS (0x0c)
134 #define LCM_INT_CS_DISP_F_EN (1 << 0)
135 #define LCM_INT_CS_UNDERRUN_EN (1 << 1)
136 #define LCM_INT_CS_BUS_ERROR_INT (1 << 28)
137 #define LCM_INT_CS_UNDERRUN_INT (1 << 29)
138 #define LCM_INT_CS_DISP_F_STATUS (1 << 30)
139 #define LCM_INT_CS_DISP_F_INT (1 << 31)
141 /* CRTC Display Size Control Register */
142 #define REG_LCM_CRTC_SIZE (0x10)
143 #define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16)
144 #define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0)
146 /* CRTC Display Enable End */
147 #define REG_LCM_CRTC_DEND (0x14)
148 #define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16)
149 #define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0)
151 /* CRTC Internal Horizontal Retrace Control Register */
152 #define REG_LCM_CRTC_HR (0x18)
153 #define LCM_CRTC_HR_EVAL(x) ((x) << 16)
154 #define LCM_CRTC_HR_SVAL(x) ((x) << 0)
156 /* CRTC Horizontal Sync Control Register */
157 #define REG_LCM_CRTC_HSYNC (0x1C)
158 #define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30)
159 #define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16)
160 #define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0)
162 /* CRTC Internal Vertical Retrace Control Register */
163 #define REG_LCM_CRTC_VR (0x20)
164 #define LCM_CRTC_VR_EVAL(x) ((x) << 16)
165 #define LCM_CRTC_VR_SVAL(x) ((x) << 0)
167 /* Video Stream Frame Buffer-0 Starting Address */
168 #define REG_LCM_VA_BADDR0 (0x24)
170 /* Video Stream Frame Buffer-1 Starting Address */
171 #define REG_LCM_VA_BADDR1 (0x28)
173 /* Video Stream Frame Buffer Control Register */
174 #define REG_LCM_VA_FBCTRL (0x2C)
175 #define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28)
176 #define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29)
177 #define LCM_VA_FBCTRL_START_BUF (1 << 30)
178 #define LCM_VA_FBCTRL_DB_EN (1 << 31)
180 /* Video Stream Scaling Control Register */
181 #define REG_LCM_VA_SCALE (0x30)
182 #define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15)
183 #define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15)
185 /* Image Stream Active Window Coordinates */
186 #define REG_LCM_VA_WIN (0x38)
188 /* Image Stream Stuff Pixel */
189 #define REG_LCM_VA_STUFF (0x3C)
191 /* OSD Window Starting Coordinates */
192 #define REG_LCM_OSD_WINS (0x40)
194 /* OSD Window Ending Coordinates */
195 #define REG_LCM_OSD_WINE (0x44)
197 /* OSD Stream Frame Buffer Starting Address */
198 #define REG_LCM_OSD_BADDR (0x48)
200 /* OSD Stream Frame Buffer Control Register */
201 #define REG_LCM_OSD_FBCTRL (0x4c)
203 /* OSD Overlay Control Register */
204 #define REG_LCM_OSD_OVERLAY (0x50)
206 /* OSD Overlay Color-Key Pattern Register */
207 #define REG_LCM_OSD_CKEY (0x54)
209 /* OSD Overlay Color-Key Mask Register */
210 #define REG_LCM_OSD_CMASK (0x58)
212 /* OSD Window Skip1 Register */
213 #define REG_LCM_OSD_SKIP1 (0x5C)
215 /* OSD Window Skip2 Register */
216 #define REG_LCM_OSD_SKIP2 (0x60)
218 /* OSD horizontal up scaling control register */
219 #define REG_LCM_OSD_SCALE (0x64)
221 /* MPU Vsync control register */
222 #define REG_LCM_MPU_VSYNC (0x68)
224 /* Hardware cursor control Register */
225 #define REG_LCM_HC_CTRL (0x6C)
227 /* Hardware cursot tip point potison on va picture */
228 #define REG_LCM_HC_POS (0x70)
230 /* Hardware Cursor Window Buffer Control Register */
231 #define REG_LCM_HC_WBCTRL (0x74)
233 /* Hardware cursor memory base address register */
234 #define REG_LCM_HC_BADDR (0x78)
236 /* Hardware cursor color ram register mapped to bpp = 0 */
237 #define REG_LCM_HC_COLOR0 (0x7C)
239 /* Hardware cursor color ram register mapped to bpp = 1 */
240 #define REG_LCM_HC_COLOR1 (0x80)
242 /* Hardware cursor color ram register mapped to bpp = 2 */
243 #define REG_LCM_HC_COLOR2 (0x84)
245 /* Hardware cursor color ram register mapped to bpp = 3 */
246 #define REG_LCM_HC_COLOR3 (0x88)
248 #endif /* __ASM_ARM_W90X900_REGS_LDM_H */