arch/arm/mach-w90x900/include/mach/regs-irq.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * arch/arm/mach-w90x900/include/mach/regs-irq.h
   4  *
   5  * Copyright (c) 2008 Nuvoton technology corporation
   6  * All rights reserved.
   7  *
   8  * Wan ZongShun <mcuos.com@gmail.com>
   9  *
  10  * Based on arch/arm/mach-s3c2410/include/mach/regs-irq.h
  11  */
  12
  13 #ifndef ___ASM_ARCH_REGS_IRQ_H
  14 #define ___ASM_ARCH_REGS_IRQ_H
  15
  16 /* Advance Interrupt Controller (AIC) Registers */
  17
  18 #define AIC_BA                  W90X900_VA_IRQ
  19
  20 #define REG_AIC_IRQSC           (AIC_BA+0x80)
  21 #define REG_AIC_GEN             (AIC_BA+0x84)
  22 #define REG_AIC_GASR            (AIC_BA+0x88)
  23 #define REG_AIC_GSCR            (AIC_BA+0x8C)
  24 #define REG_AIC_IRSR            (AIC_BA+0x100)
  25 #define REG_AIC_IASR            (AIC_BA+0x104)
  26 #define REG_AIC_ISR             (AIC_BA+0x108)
  27 #define REG_AIC_IPER            (AIC_BA+0x10C)
  28 #define REG_AIC_ISNR            (AIC_BA+0x110)
  29 #define REG_AIC_IMR             (AIC_BA+0x114)
  30 #define REG_AIC_OISR            (AIC_BA+0x118)
  31 #define REG_AIC_MECR            (AIC_BA+0x120)
  32 #define REG_AIC_MDCR            (AIC_BA+0x124)
  33 #define REG_AIC_SSCR            (AIC_BA+0x128)
  34 #define REG_AIC_SCCR            (AIC_BA+0x12C)
  35 #define REG_AIC_EOSCR           (AIC_BA+0x130)
  36 #define AIC_IPER                (0x10C)
  37 #define AIC_ISNR                (0x110)
  38
  39 /*16-18 bits of REG_AIC_GEN define irq(2-4) group*/
  40
  41 #define TIMER2_IRQ              (1 << 16)
  42 #define TIMER3_IRQ              (1 << 17)
  43 #define TIMER4_IRQ              (1 << 18)
  44 #define TIME_GROUP_IRQ          (TIMER2_IRQ|TIMER3_IRQ|TIMER4_IRQ)
  45
  46 #endif /* ___ASM_ARCH_REGS_IRQ_H */