arch/arm/mach-w90x900/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * linux/arch/arm/mach-w90x900/cpu.c
   4  *
   5  * Copyright (c) 2009 Nuvoton corporation.
   6  *
   7  * Wan ZongShun <mcuos.com@gmail.com>
   8  *
   9  * NUC900 series cpu common support
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/io.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/delay.h>
  22
  23 #include <asm/mach/arch.h>
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/irq.h>
  26 #include <asm/irq.h>
  27 #include <asm/system_misc.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/regs-serial.h>
  31 #include <mach/regs-clock.h>
  32 #include "regs-ebi.h"
  33 #include "regs-timer.h"
  34
  35 #include "cpu.h"
  36 #include "clock.h"
  37 #include "nuc9xx.h"
  38
  39 /* Initial IO mappings */
  40
  41 static struct map_desc nuc900_iodesc[] __initdata = {
  42         IODESC_ENT(IRQ),
  43         IODESC_ENT(GCR),
  44         IODESC_ENT(UART),
  45         IODESC_ENT(TIMER),
  46         IODESC_ENT(EBI),
  47         IODESC_ENT(GPIO),
  48 };
  49
  50 /* Initial clock declarations. */
  51 static DEFINE_CLK(lcd, 0);
  52 static DEFINE_CLK(audio, 1);
  53 static DEFINE_CLK(fmi, 4);
  54 static DEFINE_SUBCLK(ms, 0);
  55 static DEFINE_SUBCLK(sd, 1);
  56 static DEFINE_CLK(dmac, 5);
  57 static DEFINE_CLK(atapi, 6);
  58 static DEFINE_CLK(emc, 7);
  59 static DEFINE_SUBCLK(rmii, 2);
  60 static DEFINE_CLK(usbd, 8);
  61 static DEFINE_CLK(usbh, 9);
  62 static DEFINE_CLK(g2d, 10);
  63 static DEFINE_CLK(pwm, 18);
  64 static DEFINE_CLK(ps2, 24);
  65 static DEFINE_CLK(kpi, 25);
  66 static DEFINE_CLK(wdt, 26);
  67 static DEFINE_CLK(gdma, 27);
  68 static DEFINE_CLK(adc, 28);
  69 static DEFINE_CLK(usi, 29);
  70 static DEFINE_CLK(ext, 0);
  71 static DEFINE_CLK(timer0, 19);
  72 static DEFINE_CLK(timer1, 20);
  73 static DEFINE_CLK(timer2, 21);
  74 static DEFINE_CLK(timer3, 22);
  75 static DEFINE_CLK(timer4, 23);
  76
  77 static struct clk_lookup nuc900_clkregs[] = {
  78         DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
  79         DEF_CLKLOOK(&clk_audio, "nuc900-ac97", NULL),
  80         DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
  81         DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
  82         DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
  83         DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
  84         DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
  85         DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
  86         DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
  87         DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
  88         DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
  89         DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
  90         DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
  91         DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
  92         DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
  93         DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
  94         DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
  95         DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
  96         DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
  97         DEF_CLKLOOK(&clk_ext, NULL, "ext"),
  98         DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
  99         DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
 100         DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
 101         DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
 102         DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
 103 };
 104
 105 /* Initial serial platform data */
 106
 107 struct plat_serial8250_port nuc900_uart_data[] = {
 108         NUC900_8250PORT(UART0),
 109         {},
 110 };
 111
 112 struct platform_device nuc900_serial_device = {
 113         .name                   = "serial8250",
 114         .id                     = PLAT8250_DEV_PLATFORM,
 115         .dev                    = {
 116                 .platform_data  = nuc900_uart_data,
 117         },
 118 };
 119
 120 /*Set NUC900 series cpu frequence*/
 121 static int __init nuc900_set_clkval(unsigned int cpufreq)
 122 {
 123         unsigned int pllclk, ahbclk, apbclk, val;
 124
 125         pllclk = 0;
 126         ahbclk = 0;
 127         apbclk = 0;
 128
 129         switch (cpufreq) {
 130         case 66:
 131                 pllclk = PLL_66MHZ;
 132                 ahbclk = AHB_CPUCLK_1_1;
 133                 apbclk = APB_AHB_1_2;
 134                 break;
 135
 136         case 100:
 137                 pllclk = PLL_100MHZ;
 138                 ahbclk = AHB_CPUCLK_1_1;
 139                 apbclk = APB_AHB_1_2;
 140                 break;
 141
 142         case 120:
 143                 pllclk = PLL_120MHZ;
 144                 ahbclk = AHB_CPUCLK_1_2;
 145                 apbclk = APB_AHB_1_2;
 146                 break;
 147
 148         case 166:
 149                 pllclk = PLL_166MHZ;
 150                 ahbclk = AHB_CPUCLK_1_2;
 151                 apbclk = APB_AHB_1_2;
 152                 break;
 153
 154         case 200:
 155                 pllclk = PLL_200MHZ;
 156                 ahbclk = AHB_CPUCLK_1_2;
 157                 apbclk = APB_AHB_1_2;
 158                 break;
 159         }
 160
 161         __raw_writel(pllclk, REG_PLLCON0);
 162
 163         val = __raw_readl(REG_CLKDIV);
 164         val &= ~(0x03 << 24 | 0x03 << 26);
 165         val |= (ahbclk << 24 | apbclk << 26);
 166         __raw_writel(val, REG_CLKDIV);
 167
 168         return  0;
 169 }
 170 static int __init nuc900_set_cpufreq(char *str)
 171 {
 172         unsigned long cpufreq, val;
 173
 174         if (!*str)
 175                 return 0;
 176
 177         if (kstrtoul(str, 0, &cpufreq))
 178                 return 0;
 179
 180         nuc900_clock_source(NULL, "ext");
 181
 182         nuc900_set_clkval(cpufreq);
 183
 184         mdelay(1);
 185
 186         val = __raw_readl(REG_CKSKEW);
 187         val &= ~0xff;
 188         val |= DEFAULTSKEW;
 189         __raw_writel(val, REG_CKSKEW);
 190
 191         nuc900_clock_source(NULL, "pll0");
 192
 193         return 1;
 194 }
 195
 196 __setup("cpufreq=", nuc900_set_cpufreq);
 197
 198 /*Init NUC900 evb io*/
 199
 200 void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
 201 {
 202         unsigned long idcode = 0x0;
 203
 204         iotable_init(mach_desc, mach_size);
 205         iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
 206
 207         idcode = __raw_readl(NUC900PDID);
 208         if (idcode == NUC910_CPUID)
 209                 printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
 210         else if (idcode == NUC920_CPUID)
 211                 printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
 212         else if (idcode == NUC950_CPUID)
 213                 printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
 214         else if (idcode == NUC960_CPUID)
 215                 printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
 216 }
 217
 218 /*Init NUC900 clock*/
 219
 220 void __init nuc900_init_clocks(void)
 221 {
 222         clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
 223 }
 224
 225 #define WTCR    (TMR_BA + 0x1C)
 226 #define WTCLK   (1 << 10)
 227 #define WTE     (1 << 7)
 228 #define WTRE    (1 << 1)
 229
 230 void nuc9xx_restart(enum reboot_mode mode, const char *cmd)
 231 {
 232         if (mode == REBOOT_SOFT) {
 233                 /* Jump into ROM at address 0 */
 234                 soft_restart(0);
 235         } else {
 236                 __raw_writel(WTE | WTRE | WTCLK, WTCR);
 237         }
 238 }