arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11
  12 #include <asm/clkdev.h>
  13 #include <asm/hardware/arm_timer.h>
  14 #include <asm/hardware/cache-l2x0.h>
  15 #include <asm/hardware/gic.h>
  16 #include <asm/mach-types.h>
  17 #include <asm/pmu.h>
  18
  19 #include <mach/clkdev.h>
  20 #include <mach/ct-ca9x4.h>
  21
  22 #include <plat/timer-sp.h>
  23
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/time.h>
  27
  28 #include "core.h"
  29
  30 #include <mach/motherboard.h>
  31
  32 #define V2M_PA_CS7      0x10000000
  33
  34 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  35         {
  36                 .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
  37                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  38                 .length         = SZ_16K,
  39                 .type           = MT_DEVICE,
  40         }, {
  41                 .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
  42                 .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
  43                 .length         = SZ_4K,
  44                 .type           = MT_DEVICE,
  45         }, {
  46                 .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
  47                 .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
  48                 .length         = SZ_4K,
  49                 .type           = MT_DEVICE,
  50         },
  51 };
  52
  53 static void __init ct_ca9x4_map_io(void)
  54 {
  55         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  56 }
  57
  58 void __iomem *gic_cpu_base_addr;
  59
  60 static void __init ct_ca9x4_init_irq(void)
  61 {
  62         gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
  63         gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
  64         gic_cpu_init(0, gic_cpu_base_addr);
  65 }
  66
  67 #if 0
  68 static void ct_ca9x4_timer_init(void)
  69 {
  70         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
  71         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
  72
  73         sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
  74         sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
  75 }
  76
  77 static struct sys_timer ct_ca9x4_timer = {
  78         .init   = ct_ca9x4_timer_init,
  79 };
  80 #endif
  81
  82 static struct clcd_panel xvga_panel = {
  83         .mode           = {
  84                 .name           = "XVGA",
  85                 .refresh        = 60,
  86                 .xres           = 1024,
  87                 .yres           = 768,
  88                 .pixclock       = 15384,
  89                 .left_margin    = 168,
  90                 .right_margin   = 8,
  91                 .upper_margin   = 29,
  92                 .lower_margin   = 3,
  93                 .hsync_len      = 144,
  94                 .vsync_len      = 6,
  95                 .sync           = 0,
  96                 .vmode          = FB_VMODE_NONINTERLACED,
  97         },
  98         .width          = -1,
  99         .height         = -1,
 100         .tim2           = TIM2_BCD | TIM2_IPC,
 101         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 102         .bpp            = 16,
 103 };
 104
 105 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 106 {
 107         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
 108         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
 109 }
 110
 111 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 112 {
 113         unsigned long framesize = 1024 * 768 * 2;
 114         dma_addr_t dma;
 115
 116         fb->panel = &xvga_panel;
 117
 118         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 119                                 &dma, GFP_KERNEL);
 120         if (!fb->fb.screen_base) {
 121                 printk(KERN_ERR "CLCD: unable to map frame buffer\n");
 122                 return -ENOMEM;
 123         }
 124         fb->fb.fix.smem_start = dma;
 125         fb->fb.fix.smem_len = framesize;
 126
 127         return 0;
 128 }
 129
 130 static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 131 {
 132         return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
 133                 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
 134 }
 135
 136 static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
 137 {
 138         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 139                 fb->fb.screen_base, fb->fb.fix.smem_start);
 140 }
 141
 142 static struct clcd_board ct_ca9x4_clcd_data = {
 143         .name           = "CT-CA9X4",
 144         .check          = clcdfb_check,
 145         .decode         = clcdfb_decode,
 146         .enable         = ct_ca9x4_clcd_enable,
 147         .setup          = ct_ca9x4_clcd_setup,
 148         .mmap           = ct_ca9x4_clcd_mmap,
 149         .remove         = ct_ca9x4_clcd_remove,
 150 };
 151
 152 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 153 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 154 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 155 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 156
 157 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 158         &clcd_device,
 159         &dmc_device,
 160         &smc_device,
 161         &gpio_device,
 162 };
 163
 164
 165 static long ct_round(struct clk *clk, unsigned long rate)
 166 {
 167         return rate;
 168 }
 169
 170 static int ct_set(struct clk *clk, unsigned long rate)
 171 {
 172         return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 173 }
 174
 175 static const struct clk_ops osc1_clk_ops = {
 176         .round  = ct_round,
 177         .set    = ct_set,
 178 };
 179
 180 static struct clk osc1_clk = {
 181         .ops    = &osc1_clk_ops,
 182         .rate   = 24000000,
 183 };
 184
 185 static struct clk_lookup lookups[] = {
 186         {       /* CLCD */
 187                 .dev_id         = "ct:clcd",
 188                 .clk            = &osc1_clk,
 189         },
 190 };
 191
 192 static struct resource pmu_resources[] = {
 193         [0] = {
 194                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 195                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 196                 .flags  = IORESOURCE_IRQ,
 197         },
 198         [1] = {
 199                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 200                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203         [2] = {
 204                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 205                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 206                 .flags  = IORESOURCE_IRQ,
 207         },
 208         [3] = {
 209                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 210                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 211                 .flags  = IORESOURCE_IRQ,
 212         },
 213 };
 214
 215 static struct platform_device pmu_device = {
 216         .name           = "arm-pmu",
 217         .id             = ARM_PMU_DEVICE_CPU,
 218         .num_resources  = ARRAY_SIZE(pmu_resources),
 219         .resource       = pmu_resources,
 220 };
 221
 222 static void ct_ca9x4_init(void)
 223 {
 224         int i;
 225
 226 #ifdef CONFIG_CACHE_L2X0
 227         l2x0_init(MMIO_P2V(CT_CA9X4_L2CC), 0x00000000, 0xfe0fffff);
 228 #endif
 229
 230         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 231
 232         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 233                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 234
 235         platform_device_register(&pmu_device);
 236 }
 237
 238 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
 239         .phys_io        = V2M_UART0,
 240         .io_pg_offst    = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
 241         .boot_params    = PHYS_OFFSET + 0x00000100,
 242         .map_io         = ct_ca9x4_map_io,
 243         .init_irq       = ct_ca9x4_init_irq,
 244 #if 0
 245         .timer          = &ct_ca9x4_timer,
 246 #else
 247         .timer          = &v2m_timer,
 248 #endif
 249         .init_machine   = ct_ca9x4_init,
 250 MACHINE_END