arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/amba/pl022.h>
  32 #include <linux/io.h>
  33 #include <linux/gfp.h>
  34
  35 #include <asm/clkdev.h>
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <mach/clkdev.h>
  50 #include <mach/hardware.h>
  51 #include <mach/platform.h>
  52 #include <plat/timer-sp.h>
  53
  54 #include "core.h"
  55
  56 /*
  57  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  58  * is the (PA >> 12).
  59  *
  60  * Setup a VA for the Versatile Vectored Interrupt Controller.
  61  */
  62 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  63 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  64
  65 static void sic_mask_irq(unsigned int irq)
  66 {
  67         irq -= IRQ_SIC_START;
  68         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  69 }
  70
  71 static void sic_unmask_irq(unsigned int irq)
  72 {
  73         irq -= IRQ_SIC_START;
  74         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  75 }
  76
  77 static struct irq_chip sic_chip = {
  78         .name   = "SIC",
  79         .ack    = sic_mask_irq,
  80         .mask   = sic_mask_irq,
  81         .unmask = sic_unmask_irq,
  82 };
  83
  84 static void
  85 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  86 {
  87         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  88
  89         if (status == 0) {
  90                 do_bad_IRQ(irq, desc);
  91                 return;
  92         }
  93
  94         do {
  95                 irq = ffs(status) - 1;
  96                 status &= ~(1 << irq);
  97
  98                 irq += IRQ_SIC_START;
  99
 100                 generic_handle_irq(irq);
 101         } while (status);
 102 }
 103
 104 #if 1
 105 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 106 #define IRQ_AACI        IRQ_VICSOURCE24
 107 #define IRQ_ETH         IRQ_VICSOURCE25
 108 #define PIC_MASK        0xFFD00000
 109 #else
 110 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 111 #define IRQ_AACI        IRQ_SIC_AACI
 112 #define IRQ_ETH         IRQ_SIC_ETH
 113 #define PIC_MASK        0
 114 #endif
 115
 116 void __init versatile_init_irq(void)
 117 {
 118         unsigned int i;
 119
 120         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 121
 122         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 123
 124         /* Do second interrupt controller */
 125         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 126
 127         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 128                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 129                         set_irq_chip(i, &sic_chip);
 130                         set_irq_handler(i, handle_level_irq);
 131                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 132                 }
 133         }
 134
 135         /*
 136          * Interrupts on secondary controller from 0 to 8 are routed to
 137          * source 31 on PIC.
 138          * Interrupts from 21 to 31 are routed directly to the VIC on
 139          * the corresponding number on primary controller. This is controlled
 140          * by setting PIC_ENABLEx.
 141          */
 142         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 143 }
 144
 145 static struct map_desc versatile_io_desc[] __initdata = {
 146         {
 147                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 148                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE
 151         }, {
 152                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 153                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE
 156         }, {
 157                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 158                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE
 161         }, {
 162                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 163                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 164                 .length         = SZ_4K * 9,
 165                 .type           = MT_DEVICE
 166         },
 167 #ifdef CONFIG_MACH_VERSATILE_AB
 168         {
 169                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 170                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 171                 .length         = SZ_4K,
 172                 .type           = MT_DEVICE
 173         }, {
 174                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 175                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 176                 .length         = SZ_64M,
 177                 .type           = MT_DEVICE
 178         },
 179 #endif
 180 #ifdef CONFIG_DEBUG_LL
 181         {
 182                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 183                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 184                 .length         = SZ_4K,
 185                 .type           = MT_DEVICE
 186         },
 187 #endif
 188 #ifdef CONFIG_PCI
 189         {
 190                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 191                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 192                 .length         = SZ_4K,
 193                 .type           = MT_DEVICE
 194         }, {
 195                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 196                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 197                 .length         = VERSATILE_PCI_BASE_SIZE,
 198                 .type           = MT_DEVICE
 199         }, {
 200                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 201                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 202                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 203                 .type           = MT_DEVICE
 204         },
 205 #if 0
 206         {
 207                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 208                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 209                 .length         = SZ_16M,
 210                 .type           = MT_DEVICE
 211         }, {
 212                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 213                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 214                 .length         = SZ_16M,
 215                 .type           = MT_DEVICE
 216         }, {
 217                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 218                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 219                 .length         = SZ_16M,
 220                 .type           = MT_DEVICE
 221         },
 222 #endif
 223 #endif
 224 };
 225
 226 void __init versatile_map_io(void)
 227 {
 228         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 229 }
 230
 231
 232 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 233
 234 static int versatile_flash_init(void)
 235 {
 236         u32 val;
 237
 238         val = __raw_readl(VERSATILE_FLASHCTRL);
 239         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 240         __raw_writel(val, VERSATILE_FLASHCTRL);
 241
 242         return 0;
 243 }
 244
 245 static void versatile_flash_exit(void)
 246 {
 247         u32 val;
 248
 249         val = __raw_readl(VERSATILE_FLASHCTRL);
 250         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 251         __raw_writel(val, VERSATILE_FLASHCTRL);
 252 }
 253
 254 static void versatile_flash_set_vpp(int on)
 255 {
 256         u32 val;
 257
 258         val = __raw_readl(VERSATILE_FLASHCTRL);
 259         if (on)
 260                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 261         else
 262                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 263         __raw_writel(val, VERSATILE_FLASHCTRL);
 264 }
 265
 266 static struct flash_platform_data versatile_flash_data = {
 267         .map_name               = "cfi_probe",
 268         .width                  = 4,
 269         .init                   = versatile_flash_init,
 270         .exit                   = versatile_flash_exit,
 271         .set_vpp                = versatile_flash_set_vpp,
 272 };
 273
 274 static struct resource versatile_flash_resource = {
 275         .start                  = VERSATILE_FLASH_BASE,
 276         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 277         .flags                  = IORESOURCE_MEM,
 278 };
 279
 280 static struct platform_device versatile_flash_device = {
 281         .name                   = "armflash",
 282         .id                     = 0,
 283         .dev                    = {
 284                 .platform_data  = &versatile_flash_data,
 285         },
 286         .num_resources          = 1,
 287         .resource               = &versatile_flash_resource,
 288 };
 289
 290 static struct resource smc91x_resources[] = {
 291         [0] = {
 292                 .start          = VERSATILE_ETH_BASE,
 293                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 294                 .flags          = IORESOURCE_MEM,
 295         },
 296         [1] = {
 297                 .start          = IRQ_ETH,
 298                 .end            = IRQ_ETH,
 299                 .flags          = IORESOURCE_IRQ,
 300         },
 301 };
 302
 303 static struct platform_device smc91x_device = {
 304         .name           = "smc91x",
 305         .id             = 0,
 306         .num_resources  = ARRAY_SIZE(smc91x_resources),
 307         .resource       = smc91x_resources,
 308 };
 309
 310 static struct resource versatile_i2c_resource = {
 311         .start                  = VERSATILE_I2C_BASE,
 312         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 313         .flags                  = IORESOURCE_MEM,
 314 };
 315
 316 static struct platform_device versatile_i2c_device = {
 317         .name                   = "versatile-i2c",
 318         .id                     = 0,
 319         .num_resources          = 1,
 320         .resource               = &versatile_i2c_resource,
 321 };
 322
 323 static struct i2c_board_info versatile_i2c_board_info[] = {
 324         {
 325                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 326         },
 327 };
 328
 329 static int __init versatile_i2c_init(void)
 330 {
 331         return i2c_register_board_info(0, versatile_i2c_board_info,
 332                                        ARRAY_SIZE(versatile_i2c_board_info));
 333 }
 334 arch_initcall(versatile_i2c_init);
 335
 336 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 337
 338 unsigned int mmc_status(struct device *dev)
 339 {
 340         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 341         u32 mask;
 342
 343         if (adev->res.start == VERSATILE_MMCI0_BASE)
 344                 mask = 1;
 345         else
 346                 mask = 2;
 347
 348         return readl(VERSATILE_SYSMCI) & mask;
 349 }
 350
 351 static struct mmci_platform_data mmc0_plat_data = {
 352         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 353         .status         = mmc_status,
 354         .gpio_wp        = -1,
 355         .gpio_cd        = -1,
 356 };
 357
 358 static struct resource char_lcd_resources[] = {
 359         {
 360                 .start = VERSATILE_CHAR_LCD_BASE,
 361                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 362                 .flags = IORESOURCE_MEM,
 363         },
 364 };
 365
 366 static struct platform_device char_lcd_device = {
 367         .name           =       "arm-charlcd",
 368         .id             =       -1,
 369         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 370         .resource       =       char_lcd_resources,
 371 };
 372
 373 /*
 374  * Clock handling
 375  */
 376 static const struct icst_params versatile_oscvco_params = {
 377         .ref            = 24000000,
 378         .vco_max        = ICST307_VCO_MAX,
 379         .vco_min        = ICST307_VCO_MIN,
 380         .vd_min         = 4 + 8,
 381         .vd_max         = 511 + 8,
 382         .rd_min         = 1 + 2,
 383         .rd_max         = 127 + 2,
 384         .s2div          = icst307_s2div,
 385         .idx2s          = icst307_idx2s,
 386 };
 387
 388 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 389 {
 390         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 391         u32 val;
 392
 393         val = readl(clk->vcoreg) & ~0x7ffff;
 394         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 395
 396         writel(0xa05f, sys_lock);
 397         writel(val, clk->vcoreg);
 398         writel(0, sys_lock);
 399 }
 400
 401 static const struct clk_ops osc4_clk_ops = {
 402         .round  = icst_clk_round,
 403         .set    = icst_clk_set,
 404         .setvco = versatile_oscvco_set,
 405 };
 406
 407 static struct clk osc4_clk = {
 408         .ops    = &osc4_clk_ops,
 409         .params = &versatile_oscvco_params,
 410 };
 411
 412 /*
 413  * These are fixed clocks.
 414  */
 415 static struct clk ref24_clk = {
 416         .rate   = 24000000,
 417 };
 418
 419 static struct clk dummy_apb_pclk;
 420
 421 static struct clk_lookup lookups[] = {
 422         {       /* AMBA bus clock */
 423                 .con_id         = "apb_pclk",
 424                 .clk            = &dummy_apb_pclk,
 425         }, {    /* UART0 */
 426                 .dev_id         = "dev:f1",
 427                 .clk            = &ref24_clk,
 428         }, {    /* UART1 */
 429                 .dev_id         = "dev:f2",
 430                 .clk            = &ref24_clk,
 431         }, {    /* UART2 */
 432                 .dev_id         = "dev:f3",
 433                 .clk            = &ref24_clk,
 434         }, {    /* UART3 */
 435                 .dev_id         = "fpga:09",
 436                 .clk            = &ref24_clk,
 437         }, {    /* KMI0 */
 438                 .dev_id         = "fpga:06",
 439                 .clk            = &ref24_clk,
 440         }, {    /* KMI1 */
 441                 .dev_id         = "fpga:07",
 442                 .clk            = &ref24_clk,
 443         }, {    /* MMC0 */
 444                 .dev_id         = "fpga:05",
 445                 .clk            = &ref24_clk,
 446         }, {    /* MMC1 */
 447                 .dev_id         = "fpga:0b",
 448                 .clk            = &ref24_clk,
 449         }, {    /* SSP */
 450                 .dev_id         = "dev:f4",
 451                 .clk            = &ref24_clk,
 452         }, {    /* CLCD */
 453                 .dev_id         = "dev:20",
 454                 .clk            = &osc4_clk,
 455         }
 456 };
 457
 458 /*
 459  * CLCD support.
 460  */
 461 #define SYS_CLCD_MODE_MASK      (3 << 0)
 462 #define SYS_CLCD_MODE_888       (0 << 0)
 463 #define SYS_CLCD_MODE_5551      (1 << 0)
 464 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 465 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 466 #define SYS_CLCD_NLCDIOON       (1 << 2)
 467 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 468 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 469 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 470 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 471 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 472 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 473 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 474 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 475
 476 static struct clcd_panel vga = {
 477         .mode           = {
 478                 .name           = "VGA",
 479                 .refresh        = 60,
 480                 .xres           = 640,
 481                 .yres           = 480,
 482                 .pixclock       = 39721,
 483                 .left_margin    = 40,
 484                 .right_margin   = 24,
 485                 .upper_margin   = 32,
 486                 .lower_margin   = 11,
 487                 .hsync_len      = 96,
 488                 .vsync_len      = 2,
 489                 .sync           = 0,
 490                 .vmode          = FB_VMODE_NONINTERLACED,
 491         },
 492         .width          = -1,
 493         .height         = -1,
 494         .tim2           = TIM2_BCD | TIM2_IPC,
 495         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 496         .bpp            = 16,
 497 };
 498
 499 static struct clcd_panel sanyo_3_8_in = {
 500         .mode           = {
 501                 .name           = "Sanyo QVGA",
 502                 .refresh        = 116,
 503                 .xres           = 320,
 504                 .yres           = 240,
 505                 .pixclock       = 100000,
 506                 .left_margin    = 6,
 507                 .right_margin   = 6,
 508                 .upper_margin   = 5,
 509                 .lower_margin   = 5,
 510                 .hsync_len      = 6,
 511                 .vsync_len      = 6,
 512                 .sync           = 0,
 513                 .vmode          = FB_VMODE_NONINTERLACED,
 514         },
 515         .width          = -1,
 516         .height         = -1,
 517         .tim2           = TIM2_BCD,
 518         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 519         .bpp            = 16,
 520 };
 521
 522 static struct clcd_panel sanyo_2_5_in = {
 523         .mode           = {
 524                 .name           = "Sanyo QVGA Portrait",
 525                 .refresh        = 116,
 526                 .xres           = 240,
 527                 .yres           = 320,
 528                 .pixclock       = 100000,
 529                 .left_margin    = 20,
 530                 .right_margin   = 10,
 531                 .upper_margin   = 2,
 532                 .lower_margin   = 2,
 533                 .hsync_len      = 10,
 534                 .vsync_len      = 2,
 535                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 536                 .vmode          = FB_VMODE_NONINTERLACED,
 537         },
 538         .width          = -1,
 539         .height         = -1,
 540         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 541         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 542         .bpp            = 16,
 543 };
 544
 545 static struct clcd_panel epson_2_2_in = {
 546         .mode           = {
 547                 .name           = "Epson QCIF",
 548                 .refresh        = 390,
 549                 .xres           = 176,
 550                 .yres           = 220,
 551                 .pixclock       = 62500,
 552                 .left_margin    = 3,
 553                 .right_margin   = 2,
 554                 .upper_margin   = 1,
 555                 .lower_margin   = 0,
 556                 .hsync_len      = 3,
 557                 .vsync_len      = 2,
 558                 .sync           = 0,
 559                 .vmode          = FB_VMODE_NONINTERLACED,
 560         },
 561         .width          = -1,
 562         .height         = -1,
 563         .tim2           = TIM2_BCD | TIM2_IPC,
 564         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 565         .bpp            = 16,
 566 };
 567
 568 /*
 569  * Detect which LCD panel is connected, and return the appropriate
 570  * clcd_panel structure.  Note: we do not have any information on
 571  * the required timings for the 8.4in panel, so we presently assume
 572  * VGA timings.
 573  */
 574 static struct clcd_panel *versatile_clcd_panel(void)
 575 {
 576         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 577         struct clcd_panel *panel = &vga;
 578         u32 val;
 579
 580         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 581         if (val == SYS_CLCD_ID_SANYO_3_8)
 582                 panel = &sanyo_3_8_in;
 583         else if (val == SYS_CLCD_ID_SANYO_2_5)
 584                 panel = &sanyo_2_5_in;
 585         else if (val == SYS_CLCD_ID_EPSON_2_2)
 586                 panel = &epson_2_2_in;
 587         else if (val == SYS_CLCD_ID_VGA)
 588                 panel = &vga;
 589         else {
 590                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 591                         val);
 592                 panel = &vga;
 593         }
 594
 595         return panel;
 596 }
 597
 598 /*
 599  * Disable all display connectors on the interface module.
 600  */
 601 static void versatile_clcd_disable(struct clcd_fb *fb)
 602 {
 603         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 604         u32 val;
 605
 606         val = readl(sys_clcd);
 607         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 608         writel(val, sys_clcd);
 609
 610 #ifdef CONFIG_MACH_VERSATILE_AB
 611         /*
 612          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 613          */
 614         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 615                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 616                 unsigned long ctrl;
 617
 618                 ctrl = readl(versatile_ib2_ctrl);
 619                 ctrl &= ~0x01;
 620                 writel(ctrl, versatile_ib2_ctrl);
 621         }
 622 #endif
 623 }
 624
 625 /*
 626  * Enable the relevant connector on the interface module.
 627  */
 628 static void versatile_clcd_enable(struct clcd_fb *fb)
 629 {
 630         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 631         u32 val;
 632
 633         val = readl(sys_clcd);
 634         val &= ~SYS_CLCD_MODE_MASK;
 635
 636         switch (fb->fb.var.green.length) {
 637         case 5:
 638                 val |= SYS_CLCD_MODE_5551;
 639                 break;
 640         case 6:
 641                 val |= SYS_CLCD_MODE_565_RLSB;
 642                 break;
 643         case 8:
 644                 val |= SYS_CLCD_MODE_888;
 645                 break;
 646         }
 647
 648         /*
 649          * Set the MUX
 650          */
 651         writel(val, sys_clcd);
 652
 653         /*
 654          * And now enable the PSUs
 655          */
 656         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 657         writel(val, sys_clcd);
 658
 659 #ifdef CONFIG_MACH_VERSATILE_AB
 660         /*
 661          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 662          */
 663         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 664                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 665                 unsigned long ctrl;
 666
 667                 ctrl = readl(versatile_ib2_ctrl);
 668                 ctrl |= 0x01;
 669                 writel(ctrl, versatile_ib2_ctrl);
 670         }
 671 #endif
 672 }
 673
 674 static unsigned long framesize = SZ_1M;
 675
 676 static int versatile_clcd_setup(struct clcd_fb *fb)
 677 {
 678         dma_addr_t dma;
 679
 680         fb->panel               = versatile_clcd_panel();
 681
 682         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 683                                                     &dma, GFP_KERNEL);
 684         if (!fb->fb.screen_base) {
 685                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 686                 return -ENOMEM;
 687         }
 688
 689         fb->fb.fix.smem_start   = dma;
 690         fb->fb.fix.smem_len     = framesize;
 691
 692         return 0;
 693 }
 694
 695 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 696 {
 697         return dma_mmap_writecombine(&fb->dev->dev, vma,
 698                                      fb->fb.screen_base,
 699                                      fb->fb.fix.smem_start,
 700                                      fb->fb.fix.smem_len);
 701 }
 702
 703 static void versatile_clcd_remove(struct clcd_fb *fb)
 704 {
 705         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 706                               fb->fb.screen_base, fb->fb.fix.smem_start);
 707 }
 708
 709 static struct clcd_board clcd_plat_data = {
 710         .name           = "Versatile",
 711         .check          = clcdfb_check,
 712         .decode         = clcdfb_decode,
 713         .disable        = versatile_clcd_disable,
 714         .enable         = versatile_clcd_enable,
 715         .setup          = versatile_clcd_setup,
 716         .mmap           = versatile_clcd_mmap,
 717         .remove         = versatile_clcd_remove,
 718 };
 719
 720 static struct pl061_platform_data gpio0_plat_data = {
 721         .gpio_base      = 0,
 722         .irq_base       = IRQ_GPIO0_START,
 723 };
 724
 725 static struct pl061_platform_data gpio1_plat_data = {
 726         .gpio_base      = 8,
 727         .irq_base       = IRQ_GPIO1_START,
 728 };
 729
 730 static struct pl022_ssp_controller ssp0_plat_data = {
 731         .bus_id = 0,
 732         .enable_dma = 0,
 733         .num_chipselect = 1,
 734 };
 735
 736 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 737 #define AACI_DMA        { 0x80, 0x81 }
 738 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 739 #define MMCI0_DMA       { 0x84, 0 }
 740 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 741 #define KMI0_DMA        { 0, 0 }
 742 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 743 #define KMI1_DMA        { 0, 0 }
 744
 745 /*
 746  * These devices are connected directly to the multi-layer AHB switch
 747  */
 748 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 749 #define SMC_DMA         { 0, 0 }
 750 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 751 #define MPMC_DMA        { 0, 0 }
 752 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 753 #define CLCD_DMA        { 0, 0 }
 754 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 755 #define DMAC_DMA        { 0, 0 }
 756
 757 /*
 758  * These devices are connected via the core APB bridge
 759  */
 760 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 761 #define SCTL_DMA        { 0, 0 }
 762 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 763 #define WATCHDOG_DMA    { 0, 0 }
 764 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 765 #define GPIO0_DMA       { 0, 0 }
 766 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 767 #define GPIO1_DMA       { 0, 0 }
 768 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 769 #define RTC_DMA         { 0, 0 }
 770
 771 /*
 772  * These devices are connected via the DMA APB bridge
 773  */
 774 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 775 #define SCI_DMA         { 7, 6 }
 776 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 777 #define UART0_DMA       { 15, 14 }
 778 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 779 #define UART1_DMA       { 13, 12 }
 780 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 781 #define UART2_DMA       { 11, 10 }
 782 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 783 #define SSP_DMA         { 9, 8 }
 784
 785 /* FPGA Primecells */
 786 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 787 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 788 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 789 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 790
 791 /* DevChip Primecells */
 792 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 793 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 794 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 795 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 796 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 797 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 798 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 799 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 800 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 801 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 802 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 803 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 804 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 805 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 806
 807 static struct amba_device *amba_devs[] __initdata = {
 808         &dmac_device,
 809         &uart0_device,
 810         &uart1_device,
 811         &uart2_device,
 812         &smc_device,
 813         &mpmc_device,
 814         &clcd_device,
 815         &sctl_device,
 816         &wdog_device,
 817         &gpio0_device,
 818         &gpio1_device,
 819         &rtc_device,
 820         &sci0_device,
 821         &ssp0_device,
 822         &aaci_device,
 823         &mmc0_device,
 824         &kmi0_device,
 825         &kmi1_device,
 826 };
 827
 828 #ifdef CONFIG_LEDS
 829 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 830
 831 static void versatile_leds_event(led_event_t ledevt)
 832 {
 833         unsigned long flags;
 834         u32 val;
 835
 836         local_irq_save(flags);
 837         val = readl(VA_LEDS_BASE);
 838
 839         switch (ledevt) {
 840         case led_idle_start:
 841                 val = val & ~VERSATILE_SYS_LED0;
 842                 break;
 843
 844         case led_idle_end:
 845                 val = val | VERSATILE_SYS_LED0;
 846                 break;
 847
 848         case led_timer:
 849                 val = val ^ VERSATILE_SYS_LED1;
 850                 break;
 851
 852         case led_halted:
 853                 val = 0;
 854                 break;
 855
 856         default:
 857                 break;
 858         }
 859
 860         writel(val, VA_LEDS_BASE);
 861         local_irq_restore(flags);
 862 }
 863 #endif  /* CONFIG_LEDS */
 864
 865 void __init versatile_init(void)
 866 {
 867         int i;
 868
 869         osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
 870
 871         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 872
 873         platform_device_register(&versatile_flash_device);
 874         platform_device_register(&versatile_i2c_device);
 875         platform_device_register(&smc91x_device);
 876         platform_device_register(&char_lcd_device);
 877
 878         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 879                 struct amba_device *d = amba_devs[i];
 880                 amba_device_register(d, &iomem_resource);
 881         }
 882
 883 #ifdef CONFIG_LEDS
 884         leds_event = versatile_leds_event;
 885 #endif
 886 }
 887
 888 /*
 889  * Where is the timer (VA)?
 890  */
 891 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 892 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 893 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 894 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 895
 896 /*
 897  * Set up timer interrupt, and return the current time in seconds.
 898  */
 899 static void __init versatile_timer_init(void)
 900 {
 901         u32 val;
 902
 903         /*
 904          * set clock frequency:
 905          *      VERSATILE_REFCLK is 32KHz
 906          *      VERSATILE_TIMCLK is 1MHz
 907          */
 908         val = readl(__io_address(VERSATILE_SCTL_BASE));
 909         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 910                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 911                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 912                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 913                __io_address(VERSATILE_SCTL_BASE));
 914
 915         /*
 916          * Initialise to a known state (all timers off)
 917          */
 918         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 919         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 920         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 921         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 922
 923         sp804_clocksource_init(TIMER3_VA_BASE);
 924         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 925 }
 926
 927 struct sys_timer versatile_timer = {
 928         .init           = versatile_timer_init,
 929 };
 930