arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sysdev.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/clcd.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/hardware.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst307.h>
  38 #include <asm/hardware/vic.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/time.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/mmc.h>
  46
  47 #include "core.h"
  48 #include "clock.h"
  49
  50 /*
  51  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  52  * is the (PA >> 12).
  53  *
  54  * Setup a VA for the Versatile Vectored Interrupt Controller.
  55  */
  56 #define __io_address(n)         __io(IO_ADDRESS(n))
  57 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  58 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  59
  60 static void sic_mask_irq(unsigned int irq)
  61 {
  62         irq -= IRQ_SIC_START;
  63         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  64 }
  65
  66 static void sic_unmask_irq(unsigned int irq)
  67 {
  68         irq -= IRQ_SIC_START;
  69         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  70 }
  71
  72 static struct irqchip sic_chip = {
  73         .ack    = sic_mask_irq,
  74         .mask   = sic_mask_irq,
  75         .unmask = sic_unmask_irq,
  76 };
  77
  78 static void
  79 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  80 {
  81         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  82
  83         if (status == 0) {
  84                 do_bad_IRQ(irq, desc, regs);
  85                 return;
  86         }
  87
  88         do {
  89                 irq = ffs(status) - 1;
  90                 status &= ~(1 << irq);
  91
  92                 irq += IRQ_SIC_START;
  93
  94                 desc = irq_desc + irq;
  95                 desc_handle_irq(irq, desc, regs);
  96         } while (status);
  97 }
  98
  99 #if 1
 100 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 101 #define IRQ_AACI        IRQ_VICSOURCE24
 102 #define IRQ_ETH         IRQ_VICSOURCE25
 103 #define PIC_MASK        0xFFD00000
 104 #else
 105 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 106 #define IRQ_AACI        IRQ_SIC_AACI
 107 #define IRQ_ETH         IRQ_SIC_ETH
 108 #define PIC_MASK        0
 109 #endif
 110
 111 void __init versatile_init_irq(void)
 112 {
 113         unsigned int i;
 114
 115         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
 116
 117         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 118
 119         /* Do second interrupt controller */
 120         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 121
 122         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 123                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 124                         set_irq_chip(i, &sic_chip);
 125                         set_irq_handler(i, do_level_IRQ);
 126                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 127                 }
 128         }
 129
 130         /*
 131          * Interrupts on secondary controller from 0 to 8 are routed to
 132          * source 31 on PIC.
 133          * Interrupts from 21 to 31 are routed directly to the VIC on
 134          * the corresponding number on primary controller. This is controlled
 135          * by setting PIC_ENABLEx.
 136          */
 137         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 138 }
 139
 140 static struct map_desc versatile_io_desc[] __initdata = {
 141         {
 142                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 143                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 144                 .length         = SZ_4K,
 145                 .type           = MT_DEVICE
 146         }, {
 147                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 148                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE
 151         }, {
 152                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 153                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE
 156         }, {
 157                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 158                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 159                 .length         = SZ_4K * 9,
 160                 .type           = MT_DEVICE
 161         },
 162 #ifdef CONFIG_MACH_VERSATILE_AB
 163         {
 164                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 165                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 166                 .length         = SZ_4K,
 167                 .type           = MT_DEVICE
 168         }, {
 169                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 170                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 171                 .length         = SZ_64M,
 172                 .type           = MT_DEVICE
 173         },
 174 #endif
 175 #ifdef CONFIG_DEBUG_LL
 176         {
 177                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 178                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 179                 .length         = SZ_4K,
 180                 .type           = MT_DEVICE
 181         },
 182 #endif
 183 #ifdef CONFIG_PCI
 184         {
 185                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 186                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 187                 .length         = SZ_4K,
 188                 .type           = MT_DEVICE
 189         }, {
 190                 .virtual        =  VERSATILE_PCI_VIRT_BASE,
 191                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 192                 .length         = VERSATILE_PCI_BASE_SIZE,
 193                 .type           = MT_DEVICE
 194         }, {
 195                 .virtual        =  VERSATILE_PCI_CFG_VIRT_BASE,
 196                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 197                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 198                 .type           = MT_DEVICE
 199         },
 200 #if 0
 201         {
 202                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 203                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 204                 .length         = SZ_16M,
 205                 .type           = MT_DEVICE
 206         }, {
 207                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 208                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 209                 .length         = SZ_16M,
 210                 .type           = MT_DEVICE
 211         }, {
 212                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 213                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 214                 .length         = SZ_16M,
 215                 .type           = MT_DEVICE
 216         },
 217 #endif
 218 #endif
 219 };
 220
 221 void __init versatile_map_io(void)
 222 {
 223         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 224 }
 225
 226 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 227
 228 /*
 229  * This is the Versatile sched_clock implementation.  This has
 230  * a resolution of 41.7ns, and a maximum value of about 179s.
 231  */
 232 unsigned long long sched_clock(void)
 233 {
 234         unsigned long long v;
 235
 236         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
 237         do_div(v, 3);
 238
 239         return v;
 240 }
 241
 242
 243 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 244
 245 static int versatile_flash_init(void)
 246 {
 247         u32 val;
 248
 249         val = __raw_readl(VERSATILE_FLASHCTRL);
 250         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 251         __raw_writel(val, VERSATILE_FLASHCTRL);
 252
 253         return 0;
 254 }
 255
 256 static void versatile_flash_exit(void)
 257 {
 258         u32 val;
 259
 260         val = __raw_readl(VERSATILE_FLASHCTRL);
 261         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 262         __raw_writel(val, VERSATILE_FLASHCTRL);
 263 }
 264
 265 static void versatile_flash_set_vpp(int on)
 266 {
 267         u32 val;
 268
 269         val = __raw_readl(VERSATILE_FLASHCTRL);
 270         if (on)
 271                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 272         else
 273                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 274         __raw_writel(val, VERSATILE_FLASHCTRL);
 275 }
 276
 277 static struct flash_platform_data versatile_flash_data = {
 278         .map_name               = "cfi_probe",
 279         .width                  = 4,
 280         .init                   = versatile_flash_init,
 281         .exit                   = versatile_flash_exit,
 282         .set_vpp                = versatile_flash_set_vpp,
 283 };
 284
 285 static struct resource versatile_flash_resource = {
 286         .start                  = VERSATILE_FLASH_BASE,
 287         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
 288         .flags                  = IORESOURCE_MEM,
 289 };
 290
 291 static struct platform_device versatile_flash_device = {
 292         .name                   = "armflash",
 293         .id                     = 0,
 294         .dev                    = {
 295                 .platform_data  = &versatile_flash_data,
 296         },
 297         .num_resources          = 1,
 298         .resource               = &versatile_flash_resource,
 299 };
 300
 301 static struct resource smc91x_resources[] = {
 302         [0] = {
 303                 .start          = VERSATILE_ETH_BASE,
 304                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 305                 .flags          = IORESOURCE_MEM,
 306         },
 307         [1] = {
 308                 .start          = IRQ_ETH,
 309                 .end            = IRQ_ETH,
 310                 .flags          = IORESOURCE_IRQ,
 311         },
 312 };
 313
 314 static struct platform_device smc91x_device = {
 315         .name           = "smc91x",
 316         .id             = 0,
 317         .num_resources  = ARRAY_SIZE(smc91x_resources),
 318         .resource       = smc91x_resources,
 319 };
 320
 321 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 322
 323 unsigned int mmc_status(struct device *dev)
 324 {
 325         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 326         u32 mask;
 327
 328         if (adev->res.start == VERSATILE_MMCI0_BASE)
 329                 mask = 1;
 330         else
 331                 mask = 2;
 332
 333         return readl(VERSATILE_SYSMCI) & mask;
 334 }
 335
 336 static struct mmc_platform_data mmc0_plat_data = {
 337         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 338         .status         = mmc_status,
 339 };
 340
 341 /*
 342  * Clock handling
 343  */
 344 static const struct icst307_params versatile_oscvco_params = {
 345         .ref            = 24000,
 346         .vco_max        = 200000,
 347         .vd_min         = 4 + 8,
 348         .vd_max         = 511 + 8,
 349         .rd_min         = 1 + 2,
 350         .rd_max         = 127 + 2,
 351 };
 352
 353 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
 354 {
 355         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 356 #if defined(CONFIG_ARCH_VERSATILE_PB)
 357         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
 358 #elif defined(CONFIG_MACH_VERSATILE_AB)
 359         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
 360 #endif
 361         u32 val;
 362
 363         val = readl(sys_osc) & ~0x7ffff;
 364         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 365
 366         writel(0xa05f, sys_lock);
 367         writel(val, sys_osc);
 368         writel(0, sys_lock);
 369 }
 370
 371 static struct clk versatile_clcd_clk = {
 372         .name   = "CLCDCLK",
 373         .params = &versatile_oscvco_params,
 374         .setvco = versatile_oscvco_set,
 375 };
 376
 377 /*
 378  * CLCD support.
 379  */
 380 #define SYS_CLCD_MODE_MASK      (3 << 0)
 381 #define SYS_CLCD_MODE_888       (0 << 0)
 382 #define SYS_CLCD_MODE_5551      (1 << 0)
 383 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 384 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 385 #define SYS_CLCD_NLCDIOON       (1 << 2)
 386 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 387 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 388 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 389 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 390 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 391 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 392 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 393 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 394
 395 static struct clcd_panel vga = {
 396         .mode           = {
 397                 .name           = "VGA",
 398                 .refresh        = 60,
 399                 .xres           = 640,
 400                 .yres           = 480,
 401                 .pixclock       = 39721,
 402                 .left_margin    = 40,
 403                 .right_margin   = 24,
 404                 .upper_margin   = 32,
 405                 .lower_margin   = 11,
 406                 .hsync_len      = 96,
 407                 .vsync_len      = 2,
 408                 .sync           = 0,
 409                 .vmode          = FB_VMODE_NONINTERLACED,
 410         },
 411         .width          = -1,
 412         .height         = -1,
 413         .tim2           = TIM2_BCD | TIM2_IPC,
 414         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 415         .bpp            = 16,
 416 };
 417
 418 static struct clcd_panel sanyo_3_8_in = {
 419         .mode           = {
 420                 .name           = "Sanyo QVGA",
 421                 .refresh        = 116,
 422                 .xres           = 320,
 423                 .yres           = 240,
 424                 .pixclock       = 100000,
 425                 .left_margin    = 6,
 426                 .right_margin   = 6,
 427                 .upper_margin   = 5,
 428                 .lower_margin   = 5,
 429                 .hsync_len      = 6,
 430                 .vsync_len      = 6,
 431                 .sync           = 0,
 432                 .vmode          = FB_VMODE_NONINTERLACED,
 433         },
 434         .width          = -1,
 435         .height         = -1,
 436         .tim2           = TIM2_BCD,
 437         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 438         .bpp            = 16,
 439 };
 440
 441 static struct clcd_panel sanyo_2_5_in = {
 442         .mode           = {
 443                 .name           = "Sanyo QVGA Portrait",
 444                 .refresh        = 116,
 445                 .xres           = 240,
 446                 .yres           = 320,
 447                 .pixclock       = 100000,
 448                 .left_margin    = 20,
 449                 .right_margin   = 10,
 450                 .upper_margin   = 2,
 451                 .lower_margin   = 2,
 452                 .hsync_len      = 10,
 453                 .vsync_len      = 2,
 454                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 455                 .vmode          = FB_VMODE_NONINTERLACED,
 456         },
 457         .width          = -1,
 458         .height         = -1,
 459         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 460         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 461         .bpp            = 16,
 462 };
 463
 464 static struct clcd_panel epson_2_2_in = {
 465         .mode           = {
 466                 .name           = "Epson QCIF",
 467                 .refresh        = 390,
 468                 .xres           = 176,
 469                 .yres           = 220,
 470                 .pixclock       = 62500,
 471                 .left_margin    = 3,
 472                 .right_margin   = 2,
 473                 .upper_margin   = 1,
 474                 .lower_margin   = 0,
 475                 .hsync_len      = 3,
 476                 .vsync_len      = 2,
 477                 .sync           = 0,
 478                 .vmode          = FB_VMODE_NONINTERLACED,
 479         },
 480         .width          = -1,
 481         .height         = -1,
 482         .tim2           = TIM2_BCD | TIM2_IPC,
 483         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 484         .bpp            = 16,
 485 };
 486
 487 /*
 488  * Detect which LCD panel is connected, and return the appropriate
 489  * clcd_panel structure.  Note: we do not have any information on
 490  * the required timings for the 8.4in panel, so we presently assume
 491  * VGA timings.
 492  */
 493 static struct clcd_panel *versatile_clcd_panel(void)
 494 {
 495         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 496         struct clcd_panel *panel = &vga;
 497         u32 val;
 498
 499         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 500         if (val == SYS_CLCD_ID_SANYO_3_8)
 501                 panel = &sanyo_3_8_in;
 502         else if (val == SYS_CLCD_ID_SANYO_2_5)
 503                 panel = &sanyo_2_5_in;
 504         else if (val == SYS_CLCD_ID_EPSON_2_2)
 505                 panel = &epson_2_2_in;
 506         else if (val == SYS_CLCD_ID_VGA)
 507                 panel = &vga;
 508         else {
 509                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 510                         val);
 511                 panel = &vga;
 512         }
 513
 514         return panel;
 515 }
 516
 517 /*
 518  * Disable all display connectors on the interface module.
 519  */
 520 static void versatile_clcd_disable(struct clcd_fb *fb)
 521 {
 522         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 523         u32 val;
 524
 525         val = readl(sys_clcd);
 526         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 527         writel(val, sys_clcd);
 528
 529 #ifdef CONFIG_MACH_VERSATILE_AB
 530         /*
 531          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 532          */
 533         if (fb->panel == &sanyo_2_5_in) {
 534                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 535                 unsigned long ctrl;
 536
 537                 ctrl = readl(versatile_ib2_ctrl);
 538                 ctrl &= ~0x01;
 539                 writel(ctrl, versatile_ib2_ctrl);
 540         }
 541 #endif
 542 }
 543
 544 /*
 545  * Enable the relevant connector on the interface module.
 546  */
 547 static void versatile_clcd_enable(struct clcd_fb *fb)
 548 {
 549         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 550         u32 val;
 551
 552         val = readl(sys_clcd);
 553         val &= ~SYS_CLCD_MODE_MASK;
 554
 555         switch (fb->fb.var.green.length) {
 556         case 5:
 557                 val |= SYS_CLCD_MODE_5551;
 558                 break;
 559         case 6:
 560                 val |= SYS_CLCD_MODE_565_RLSB;
 561                 break;
 562         case 8:
 563                 val |= SYS_CLCD_MODE_888;
 564                 break;
 565         }
 566
 567         /*
 568          * Set the MUX
 569          */
 570         writel(val, sys_clcd);
 571
 572         /*
 573          * And now enable the PSUs
 574          */
 575         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 576         writel(val, sys_clcd);
 577
 578 #ifdef CONFIG_MACH_VERSATILE_AB
 579         /*
 580          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 581          */
 582         if (fb->panel == &sanyo_2_5_in) {
 583                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 584                 unsigned long ctrl;
 585
 586                 ctrl = readl(versatile_ib2_ctrl);
 587                 ctrl |= 0x01;
 588                 writel(ctrl, versatile_ib2_ctrl);
 589         }
 590 #endif
 591 }
 592
 593 static unsigned long framesize = SZ_1M;
 594
 595 static int versatile_clcd_setup(struct clcd_fb *fb)
 596 {
 597         dma_addr_t dma;
 598
 599         fb->panel               = versatile_clcd_panel();
 600
 601         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 602                                                     &dma, GFP_KERNEL);
 603         if (!fb->fb.screen_base) {
 604                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 605                 return -ENOMEM;
 606         }
 607
 608         fb->fb.fix.smem_start   = dma;
 609         fb->fb.fix.smem_len     = framesize;
 610
 611         return 0;
 612 }
 613
 614 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 615 {
 616         return dma_mmap_writecombine(&fb->dev->dev, vma,
 617                                      fb->fb.screen_base,
 618                                      fb->fb.fix.smem_start,
 619                                      fb->fb.fix.smem_len);
 620 }
 621
 622 static void versatile_clcd_remove(struct clcd_fb *fb)
 623 {
 624         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 625                               fb->fb.screen_base, fb->fb.fix.smem_start);
 626 }
 627
 628 static struct clcd_board clcd_plat_data = {
 629         .name           = "Versatile",
 630         .check          = clcdfb_check,
 631         .decode         = clcdfb_decode,
 632         .disable        = versatile_clcd_disable,
 633         .enable         = versatile_clcd_enable,
 634         .setup          = versatile_clcd_setup,
 635         .mmap           = versatile_clcd_mmap,
 636         .remove         = versatile_clcd_remove,
 637 };
 638
 639 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 640 #define AACI_DMA        { 0x80, 0x81 }
 641 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 642 #define MMCI0_DMA       { 0x84, 0 }
 643 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 644 #define KMI0_DMA        { 0, 0 }
 645 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 646 #define KMI1_DMA        { 0, 0 }
 647
 648 /*
 649  * These devices are connected directly to the multi-layer AHB switch
 650  */
 651 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 652 #define SMC_DMA         { 0, 0 }
 653 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 654 #define MPMC_DMA        { 0, 0 }
 655 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 656 #define CLCD_DMA        { 0, 0 }
 657 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 658 #define DMAC_DMA        { 0, 0 }
 659
 660 /*
 661  * These devices are connected via the core APB bridge
 662  */
 663 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 664 #define SCTL_DMA        { 0, 0 }
 665 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 666 #define WATCHDOG_DMA    { 0, 0 }
 667 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 668 #define GPIO0_DMA       { 0, 0 }
 669 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 670 #define GPIO1_DMA       { 0, 0 }
 671 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 672 #define RTC_DMA         { 0, 0 }
 673
 674 /*
 675  * These devices are connected via the DMA APB bridge
 676  */
 677 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 678 #define SCI_DMA         { 7, 6 }
 679 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 680 #define UART0_DMA       { 15, 14 }
 681 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 682 #define UART1_DMA       { 13, 12 }
 683 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 684 #define UART2_DMA       { 11, 10 }
 685 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 686 #define SSP_DMA         { 9, 8 }
 687
 688 /* FPGA Primecells */
 689 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 690 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 691 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 692 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 693
 694 /* DevChip Primecells */
 695 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 696 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 697 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 698 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 699 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 700 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 701 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 702 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 703 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 704 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 705 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 706 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 707 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 708 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 709
 710 static struct amba_device *amba_devs[] __initdata = {
 711         &dmac_device,
 712         &uart0_device,
 713         &uart1_device,
 714         &uart2_device,
 715         &smc_device,
 716         &mpmc_device,
 717         &clcd_device,
 718         &sctl_device,
 719         &wdog_device,
 720         &gpio0_device,
 721         &gpio1_device,
 722         &rtc_device,
 723         &sci0_device,
 724         &ssp0_device,
 725         &aaci_device,
 726         &mmc0_device,
 727         &kmi0_device,
 728         &kmi1_device,
 729 };
 730
 731 #ifdef CONFIG_LEDS
 732 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 733
 734 static void versatile_leds_event(led_event_t ledevt)
 735 {
 736         unsigned long flags;
 737         u32 val;
 738
 739         local_irq_save(flags);
 740         val = readl(VA_LEDS_BASE);
 741
 742         switch (ledevt) {
 743         case led_idle_start:
 744                 val = val & ~VERSATILE_SYS_LED0;
 745                 break;
 746
 747         case led_idle_end:
 748                 val = val | VERSATILE_SYS_LED0;
 749                 break;
 750
 751         case led_timer:
 752                 val = val ^ VERSATILE_SYS_LED1;
 753                 break;
 754
 755         case led_halted:
 756                 val = 0;
 757                 break;
 758
 759         default:
 760                 break;
 761         }
 762
 763         writel(val, VA_LEDS_BASE);
 764         local_irq_restore(flags);
 765 }
 766 #endif  /* CONFIG_LEDS */
 767
 768 void __init versatile_init(void)
 769 {
 770         int i;
 771
 772         clk_register(&versatile_clcd_clk);
 773
 774         platform_device_register(&versatile_flash_device);
 775         platform_device_register(&smc91x_device);
 776
 777         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 778                 struct amba_device *d = amba_devs[i];
 779                 amba_device_register(d, &iomem_resource);
 780         }
 781
 782 #ifdef CONFIG_LEDS
 783         leds_event = versatile_leds_event;
 784 #endif
 785 }
 786
 787 /*
 788  * Where is the timer (VA)?
 789  */
 790 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 791 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 792 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 793 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 794 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE)
 795
 796 /*
 797  * How long is the timer interval?
 798  */
 799 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 800 #if TIMER_INTERVAL >= 0x100000
 801 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 802 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 803 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 804 #elif TIMER_INTERVAL >= 0x10000
 805 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 806 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 807 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 808 #else
 809 #define TIMER_RELOAD    (TIMER_INTERVAL)
 810 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 811 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 812 #endif
 813
 814 /*
 815  * Returns number of ms since last clock interrupt.  Note that interrupts
 816  * will have been disabled by do_gettimeoffset()
 817  */
 818 static unsigned long versatile_gettimeoffset(void)
 819 {
 820         unsigned long ticks1, ticks2, status;
 821
 822         /*
 823          * Get the current number of ticks.  Note that there is a race
 824          * condition between us reading the timer and checking for
 825          * an interrupt.  We get around this by ensuring that the
 826          * counter has not reloaded between our two reads.
 827          */
 828         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 829         do {
 830                 ticks1 = ticks2;
 831                 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
 832                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 833         } while (ticks2 > ticks1);
 834
 835         /*
 836          * Number of ticks since last interrupt.
 837          */
 838         ticks1 = TIMER_RELOAD - ticks2;
 839
 840         /*
 841          * Interrupt pending?  If so, we've reloaded once already.
 842          *
 843          * FIXME: Need to check this is effectively timer 0 that expires
 844          */
 845         if (status & IRQMASK_TIMERINT0_1)
 846                 ticks1 += TIMER_RELOAD;
 847
 848         /*
 849          * Convert the ticks to usecs
 850          */
 851         return TICKS2USECS(ticks1);
 852 }
 853
 854 /*
 855  * IRQ handler for the timer
 856  */
 857 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 858 {
 859         write_seqlock(&xtime_lock);
 860
 861         // ...clear the interrupt
 862         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 863
 864         timer_tick(regs);
 865
 866         write_sequnlock(&xtime_lock);
 867
 868         return IRQ_HANDLED;
 869 }
 870
 871 static struct irqaction versatile_timer_irq = {
 872         .name           = "Versatile Timer Tick",
 873         .flags          = SA_INTERRUPT | SA_TIMER,
 874         .handler        = versatile_timer_interrupt,
 875 };
 876
 877 /*
 878  * Set up timer interrupt, and return the current time in seconds.
 879  */
 880 static void __init versatile_timer_init(void)
 881 {
 882         u32 val;
 883
 884         /*
 885          * set clock frequency:
 886          *      VERSATILE_REFCLK is 32KHz
 887          *      VERSATILE_TIMCLK is 1MHz
 888          */
 889         val = readl(__io_address(VERSATILE_SCTL_BASE));
 890         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 891                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 892                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 893                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 894                __io_address(VERSATILE_SCTL_BASE));
 895
 896         /*
 897          * Initialise to a known state (all timers off)
 898          */
 899         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 900         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 901         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 902         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 903
 904         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 905         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
 906         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
 907                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
 908
 909         /*
 910          * Make irqs happen for the system timer
 911          */
 912         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
 913 }
 914
 915 struct sys_timer versatile_timer = {
 916         .init           = versatile_timer_init,
 917         .offset         = versatile_gettimeoffset,
 918 };