arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/config.h>
  22 #include <linux/init.h>
  23 #include <linux/device.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sysdev.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/clcd.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/hardware.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35 #include <asm/leds.h>
  36 #include <asm/hardware/arm_timer.h>
  37 #include <asm/hardware/icst307.h>
  38 #include <asm/hardware/vic.h>
  39
  40 #include <asm/mach/arch.h>
  41 #include <asm/mach/flash.h>
  42 #include <asm/mach/irq.h>
  43 #include <asm/mach/time.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/mach/mmc.h>
  46
  47 #include "core.h"
  48 #include "clock.h"
  49
  50 /*
  51  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  52  * is the (PA >> 12).
  53  *
  54  * Setup a VA for the Versatile Vectored Interrupt Controller.
  55  */
  56 #define __io_address(n)         __io(IO_ADDRESS(n))
  57 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  58 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  59
  60 static void sic_mask_irq(unsigned int irq)
  61 {
  62         irq -= IRQ_SIC_START;
  63         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  64 }
  65
  66 static void sic_unmask_irq(unsigned int irq)
  67 {
  68         irq -= IRQ_SIC_START;
  69         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  70 }
  71
  72 static struct irqchip sic_chip = {
  73         .ack    = sic_mask_irq,
  74         .mask   = sic_mask_irq,
  75         .unmask = sic_unmask_irq,
  76 };
  77
  78 static void
  79 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
  80 {
  81         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  82
  83         if (status == 0) {
  84                 do_bad_IRQ(irq, desc, regs);
  85                 return;
  86         }
  87
  88         do {
  89                 irq = ffs(status) - 1;
  90                 status &= ~(1 << irq);
  91
  92                 irq += IRQ_SIC_START;
  93
  94                 desc = irq_desc + irq;
  95                 desc_handle_irq(irq, desc, regs);
  96         } while (status);
  97 }
  98
  99 #if 1
 100 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 101 #define IRQ_AACI        IRQ_VICSOURCE24
 102 #define IRQ_ETH         IRQ_VICSOURCE25
 103 #define PIC_MASK        0xFFD00000
 104 #else
 105 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 106 #define IRQ_AACI        IRQ_SIC_AACI
 107 #define IRQ_ETH         IRQ_SIC_ETH
 108 #define PIC_MASK        0
 109 #endif
 110
 111 void __init versatile_init_irq(void)
 112 {
 113         unsigned int i;
 114
 115         vic_init(VA_VIC_BASE, ~(1 << 31));
 116
 117         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
 118         enable_irq(IRQ_VICSOURCE31);
 119
 120         /* Do second interrupt controller */
 121         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 122
 123         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 124                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 125                         set_irq_chip(i, &sic_chip);
 126                         set_irq_handler(i, do_level_IRQ);
 127                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 128                 }
 129         }
 130
 131         /*
 132          * Interrupts on secondary controller from 0 to 8 are routed to
 133          * source 31 on PIC.
 134          * Interrupts from 21 to 31 are routed directly to the VIC on
 135          * the corresponding number on primary controller. This is controlled
 136          * by setting PIC_ENABLEx.
 137          */
 138         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 139 }
 140
 141 static struct map_desc versatile_io_desc[] __initdata = {
 142         {
 143                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 144                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 145                 .length         = SZ_4K,
 146                 .type           = MT_DEVICE
 147         }, {
 148                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 149                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 150                 .length         = SZ_4K,
 151                 .type           = MT_DEVICE
 152         }, {
 153                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 154                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 155                 .length         = SZ_4K,
 156                 .type           = MT_DEVICE
 157         }, {
 158                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 159                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 160                 .length         = SZ_4K * 9,
 161                 .type           = MT_DEVICE
 162         },
 163 #ifdef CONFIG_MACH_VERSATILE_AB
 164         {
 165                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 166                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 167                 .length         = SZ_4K,
 168                 .type           = MT_DEVICE
 169         }, {
 170                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 171                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 172                 .length         = SZ_64M,
 173                 .type           = MT_DEVICE
 174         },
 175 #endif
 176 #ifdef CONFIG_DEBUG_LL
 177         {
 178                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 179                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 180                 .length         = SZ_4K,
 181                 .type           = MT_DEVICE
 182         },
 183 #endif
 184 #ifdef CONFIG_PCI
 185         {
 186                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 187                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 188                 .length         = SZ_4K,
 189                 .type           = MT_DEVICE
 190         }, {
 191                 .virtual        =  VERSATILE_PCI_VIRT_BASE,
 192                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 193                 .length         = VERSATILE_PCI_BASE_SIZE,
 194                 .type           = MT_DEVICE
 195         }, {
 196                 .virtual        =  VERSATILE_PCI_CFG_VIRT_BASE,
 197                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 198                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 199                 .type           = MT_DEVICE
 200         },
 201 #if 0
 202         {
 203                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 204                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 205                 .length         = SZ_16M,
 206                 .type           = MT_DEVICE
 207         }, {
 208                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 209                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 210                 .length         = SZ_16M,
 211                 .type           = MT_DEVICE
 212         }, {
 213                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 214                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 215                 .length         = SZ_16M,
 216                 .type           = MT_DEVICE
 217         },
 218 #endif
 219 #endif
 220 };
 221
 222 void __init versatile_map_io(void)
 223 {
 224         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 225 }
 226
 227 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 228
 229 /*
 230  * This is the Versatile sched_clock implementation.  This has
 231  * a resolution of 41.7ns, and a maximum value of about 179s.
 232  */
 233 unsigned long long sched_clock(void)
 234 {
 235         unsigned long long v;
 236
 237         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
 238         do_div(v, 3);
 239
 240         return v;
 241 }
 242
 243
 244 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 245
 246 static int versatile_flash_init(void)
 247 {
 248         u32 val;
 249
 250         val = __raw_readl(VERSATILE_FLASHCTRL);
 251         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 252         __raw_writel(val, VERSATILE_FLASHCTRL);
 253
 254         return 0;
 255 }
 256
 257 static void versatile_flash_exit(void)
 258 {
 259         u32 val;
 260
 261         val = __raw_readl(VERSATILE_FLASHCTRL);
 262         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 263         __raw_writel(val, VERSATILE_FLASHCTRL);
 264 }
 265
 266 static void versatile_flash_set_vpp(int on)
 267 {
 268         u32 val;
 269
 270         val = __raw_readl(VERSATILE_FLASHCTRL);
 271         if (on)
 272                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 273         else
 274                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 275         __raw_writel(val, VERSATILE_FLASHCTRL);
 276 }
 277
 278 static struct flash_platform_data versatile_flash_data = {
 279         .map_name               = "cfi_probe",
 280         .width                  = 4,
 281         .init                   = versatile_flash_init,
 282         .exit                   = versatile_flash_exit,
 283         .set_vpp                = versatile_flash_set_vpp,
 284 };
 285
 286 static struct resource versatile_flash_resource = {
 287         .start                  = VERSATILE_FLASH_BASE,
 288         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
 289         .flags                  = IORESOURCE_MEM,
 290 };
 291
 292 static struct platform_device versatile_flash_device = {
 293         .name                   = "armflash",
 294         .id                     = 0,
 295         .dev                    = {
 296                 .platform_data  = &versatile_flash_data,
 297         },
 298         .num_resources          = 1,
 299         .resource               = &versatile_flash_resource,
 300 };
 301
 302 static struct resource smc91x_resources[] = {
 303         [0] = {
 304                 .start          = VERSATILE_ETH_BASE,
 305                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 306                 .flags          = IORESOURCE_MEM,
 307         },
 308         [1] = {
 309                 .start          = IRQ_ETH,
 310                 .end            = IRQ_ETH,
 311                 .flags          = IORESOURCE_IRQ,
 312         },
 313 };
 314
 315 static struct platform_device smc91x_device = {
 316         .name           = "smc91x",
 317         .id             = 0,
 318         .num_resources  = ARRAY_SIZE(smc91x_resources),
 319         .resource       = smc91x_resources,
 320 };
 321
 322 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 323
 324 unsigned int mmc_status(struct device *dev)
 325 {
 326         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 327         u32 mask;
 328
 329         if (adev->res.start == VERSATILE_MMCI0_BASE)
 330                 mask = 1;
 331         else
 332                 mask = 2;
 333
 334         return readl(VERSATILE_SYSMCI) & mask;
 335 }
 336
 337 static struct mmc_platform_data mmc0_plat_data = {
 338         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 339         .status         = mmc_status,
 340 };
 341
 342 /*
 343  * Clock handling
 344  */
 345 static const struct icst307_params versatile_oscvco_params = {
 346         .ref            = 24000,
 347         .vco_max        = 200000,
 348         .vd_min         = 4 + 8,
 349         .vd_max         = 511 + 8,
 350         .rd_min         = 1 + 2,
 351         .rd_max         = 127 + 2,
 352 };
 353
 354 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
 355 {
 356         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 357 #if defined(CONFIG_ARCH_VERSATILE_PB)
 358         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
 359 #elif defined(CONFIG_MACH_VERSATILE_AB)
 360         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
 361 #endif
 362         u32 val;
 363
 364         val = readl(sys_osc) & ~0x7ffff;
 365         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 366
 367         writel(0xa05f, sys_lock);
 368         writel(val, sys_osc);
 369         writel(0, sys_lock);
 370 }
 371
 372 static struct clk versatile_clcd_clk = {
 373         .name   = "CLCDCLK",
 374         .params = &versatile_oscvco_params,
 375         .setvco = versatile_oscvco_set,
 376 };
 377
 378 /*
 379  * CLCD support.
 380  */
 381 #define SYS_CLCD_MODE_MASK      (3 << 0)
 382 #define SYS_CLCD_MODE_888       (0 << 0)
 383 #define SYS_CLCD_MODE_5551      (1 << 0)
 384 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 385 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 386 #define SYS_CLCD_NLCDIOON       (1 << 2)
 387 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 388 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 389 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 390 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 391 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 392 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 393 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 394 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 395
 396 static struct clcd_panel vga = {
 397         .mode           = {
 398                 .name           = "VGA",
 399                 .refresh        = 60,
 400                 .xres           = 640,
 401                 .yres           = 480,
 402                 .pixclock       = 39721,
 403                 .left_margin    = 40,
 404                 .right_margin   = 24,
 405                 .upper_margin   = 32,
 406                 .lower_margin   = 11,
 407                 .hsync_len      = 96,
 408                 .vsync_len      = 2,
 409                 .sync           = 0,
 410                 .vmode          = FB_VMODE_NONINTERLACED,
 411         },
 412         .width          = -1,
 413         .height         = -1,
 414         .tim2           = TIM2_BCD | TIM2_IPC,
 415         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 416         .bpp            = 16,
 417 };
 418
 419 static struct clcd_panel sanyo_3_8_in = {
 420         .mode           = {
 421                 .name           = "Sanyo QVGA",
 422                 .refresh        = 116,
 423                 .xres           = 320,
 424                 .yres           = 240,
 425                 .pixclock       = 100000,
 426                 .left_margin    = 6,
 427                 .right_margin   = 6,
 428                 .upper_margin   = 5,
 429                 .lower_margin   = 5,
 430                 .hsync_len      = 6,
 431                 .vsync_len      = 6,
 432                 .sync           = 0,
 433                 .vmode          = FB_VMODE_NONINTERLACED,
 434         },
 435         .width          = -1,
 436         .height         = -1,
 437         .tim2           = TIM2_BCD,
 438         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 439         .bpp            = 16,
 440 };
 441
 442 static struct clcd_panel sanyo_2_5_in = {
 443         .mode           = {
 444                 .name           = "Sanyo QVGA Portrait",
 445                 .refresh        = 116,
 446                 .xres           = 240,
 447                 .yres           = 320,
 448                 .pixclock       = 100000,
 449                 .left_margin    = 20,
 450                 .right_margin   = 10,
 451                 .upper_margin   = 2,
 452                 .lower_margin   = 2,
 453                 .hsync_len      = 10,
 454                 .vsync_len      = 2,
 455                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 456                 .vmode          = FB_VMODE_NONINTERLACED,
 457         },
 458         .width          = -1,
 459         .height         = -1,
 460         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 461         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 462         .bpp            = 16,
 463 };
 464
 465 static struct clcd_panel epson_2_2_in = {
 466         .mode           = {
 467                 .name           = "Epson QCIF",
 468                 .refresh        = 390,
 469                 .xres           = 176,
 470                 .yres           = 220,
 471                 .pixclock       = 62500,
 472                 .left_margin    = 3,
 473                 .right_margin   = 2,
 474                 .upper_margin   = 1,
 475                 .lower_margin   = 0,
 476                 .hsync_len      = 3,
 477                 .vsync_len      = 2,
 478                 .sync           = 0,
 479                 .vmode          = FB_VMODE_NONINTERLACED,
 480         },
 481         .width          = -1,
 482         .height         = -1,
 483         .tim2           = TIM2_BCD | TIM2_IPC,
 484         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 485         .bpp            = 16,
 486 };
 487
 488 /*
 489  * Detect which LCD panel is connected, and return the appropriate
 490  * clcd_panel structure.  Note: we do not have any information on
 491  * the required timings for the 8.4in panel, so we presently assume
 492  * VGA timings.
 493  */
 494 static struct clcd_panel *versatile_clcd_panel(void)
 495 {
 496         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 497         struct clcd_panel *panel = &vga;
 498         u32 val;
 499
 500         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 501         if (val == SYS_CLCD_ID_SANYO_3_8)
 502                 panel = &sanyo_3_8_in;
 503         else if (val == SYS_CLCD_ID_SANYO_2_5)
 504                 panel = &sanyo_2_5_in;
 505         else if (val == SYS_CLCD_ID_EPSON_2_2)
 506                 panel = &epson_2_2_in;
 507         else if (val == SYS_CLCD_ID_VGA)
 508                 panel = &vga;
 509         else {
 510                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 511                         val);
 512                 panel = &vga;
 513         }
 514
 515         return panel;
 516 }
 517
 518 /*
 519  * Disable all display connectors on the interface module.
 520  */
 521 static void versatile_clcd_disable(struct clcd_fb *fb)
 522 {
 523         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 524         u32 val;
 525
 526         val = readl(sys_clcd);
 527         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 528         writel(val, sys_clcd);
 529
 530 #ifdef CONFIG_MACH_VERSATILE_AB
 531         /*
 532          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 533          */
 534         if (fb->panel == &sanyo_2_5_in) {
 535                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 536                 unsigned long ctrl;
 537
 538                 ctrl = readl(versatile_ib2_ctrl);
 539                 ctrl &= ~0x01;
 540                 writel(ctrl, versatile_ib2_ctrl);
 541         }
 542 #endif
 543 }
 544
 545 /*
 546  * Enable the relevant connector on the interface module.
 547  */
 548 static void versatile_clcd_enable(struct clcd_fb *fb)
 549 {
 550         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 551         u32 val;
 552
 553         val = readl(sys_clcd);
 554         val &= ~SYS_CLCD_MODE_MASK;
 555
 556         switch (fb->fb.var.green.length) {
 557         case 5:
 558                 val |= SYS_CLCD_MODE_5551;
 559                 break;
 560         case 6:
 561                 val |= SYS_CLCD_MODE_565_RLSB;
 562                 break;
 563         case 8:
 564                 val |= SYS_CLCD_MODE_888;
 565                 break;
 566         }
 567
 568         /*
 569          * Set the MUX
 570          */
 571         writel(val, sys_clcd);
 572
 573         /*
 574          * And now enable the PSUs
 575          */
 576         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 577         writel(val, sys_clcd);
 578
 579 #ifdef CONFIG_MACH_VERSATILE_AB
 580         /*
 581          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 582          */
 583         if (fb->panel == &sanyo_2_5_in) {
 584                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 585                 unsigned long ctrl;
 586
 587                 ctrl = readl(versatile_ib2_ctrl);
 588                 ctrl |= 0x01;
 589                 writel(ctrl, versatile_ib2_ctrl);
 590         }
 591 #endif
 592 }
 593
 594 static unsigned long framesize = SZ_1M;
 595
 596 static int versatile_clcd_setup(struct clcd_fb *fb)
 597 {
 598         dma_addr_t dma;
 599
 600         fb->panel               = versatile_clcd_panel();
 601
 602         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 603                                                     &dma, GFP_KERNEL);
 604         if (!fb->fb.screen_base) {
 605                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 606                 return -ENOMEM;
 607         }
 608
 609         fb->fb.fix.smem_start   = dma;
 610         fb->fb.fix.smem_len     = framesize;
 611
 612         return 0;
 613 }
 614
 615 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 616 {
 617         return dma_mmap_writecombine(&fb->dev->dev, vma,
 618                                      fb->fb.screen_base,
 619                                      fb->fb.fix.smem_start,
 620                                      fb->fb.fix.smem_len);
 621 }
 622
 623 static void versatile_clcd_remove(struct clcd_fb *fb)
 624 {
 625         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 626                               fb->fb.screen_base, fb->fb.fix.smem_start);
 627 }
 628
 629 static struct clcd_board clcd_plat_data = {
 630         .name           = "Versatile",
 631         .check          = clcdfb_check,
 632         .decode         = clcdfb_decode,
 633         .disable        = versatile_clcd_disable,
 634         .enable         = versatile_clcd_enable,
 635         .setup          = versatile_clcd_setup,
 636         .mmap           = versatile_clcd_mmap,
 637         .remove         = versatile_clcd_remove,
 638 };
 639
 640 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 641 #define AACI_DMA        { 0x80, 0x81 }
 642 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 643 #define MMCI0_DMA       { 0x84, 0 }
 644 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 645 #define KMI0_DMA        { 0, 0 }
 646 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 647 #define KMI1_DMA        { 0, 0 }
 648
 649 /*
 650  * These devices are connected directly to the multi-layer AHB switch
 651  */
 652 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 653 #define SMC_DMA         { 0, 0 }
 654 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 655 #define MPMC_DMA        { 0, 0 }
 656 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 657 #define CLCD_DMA        { 0, 0 }
 658 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 659 #define DMAC_DMA        { 0, 0 }
 660
 661 /*
 662  * These devices are connected via the core APB bridge
 663  */
 664 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 665 #define SCTL_DMA        { 0, 0 }
 666 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 667 #define WATCHDOG_DMA    { 0, 0 }
 668 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 669 #define GPIO0_DMA       { 0, 0 }
 670 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 671 #define GPIO1_DMA       { 0, 0 }
 672 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 673 #define RTC_DMA         { 0, 0 }
 674
 675 /*
 676  * These devices are connected via the DMA APB bridge
 677  */
 678 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 679 #define SCI_DMA         { 7, 6 }
 680 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 681 #define UART0_DMA       { 15, 14 }
 682 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 683 #define UART1_DMA       { 13, 12 }
 684 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 685 #define UART2_DMA       { 11, 10 }
 686 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 687 #define SSP_DMA         { 9, 8 }
 688
 689 /* FPGA Primecells */
 690 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 691 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 692 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 693 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 694
 695 /* DevChip Primecells */
 696 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 697 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 698 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 699 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 700 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 701 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 702 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
 703 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 704 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 705 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 706 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 707 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 708 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 709 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 710
 711 static struct amba_device *amba_devs[] __initdata = {
 712         &dmac_device,
 713         &uart0_device,
 714         &uart1_device,
 715         &uart2_device,
 716         &smc_device,
 717         &mpmc_device,
 718         &clcd_device,
 719         &sctl_device,
 720         &wdog_device,
 721         &gpio0_device,
 722         &gpio1_device,
 723         &rtc_device,
 724         &sci0_device,
 725         &ssp0_device,
 726         &aaci_device,
 727         &mmc0_device,
 728         &kmi0_device,
 729         &kmi1_device,
 730 };
 731
 732 #ifdef CONFIG_LEDS
 733 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 734
 735 static void versatile_leds_event(led_event_t ledevt)
 736 {
 737         unsigned long flags;
 738         u32 val;
 739
 740         local_irq_save(flags);
 741         val = readl(VA_LEDS_BASE);
 742
 743         switch (ledevt) {
 744         case led_idle_start:
 745                 val = val & ~VERSATILE_SYS_LED0;
 746                 break;
 747
 748         case led_idle_end:
 749                 val = val | VERSATILE_SYS_LED0;
 750                 break;
 751
 752         case led_timer:
 753                 val = val ^ VERSATILE_SYS_LED1;
 754                 break;
 755
 756         case led_halted:
 757                 val = 0;
 758                 break;
 759
 760         default:
 761                 break;
 762         }
 763
 764         writel(val, VA_LEDS_BASE);
 765         local_irq_restore(flags);
 766 }
 767 #endif  /* CONFIG_LEDS */
 768
 769 void __init versatile_init(void)
 770 {
 771         int i;
 772
 773         clk_register(&versatile_clcd_clk);
 774
 775         platform_device_register(&versatile_flash_device);
 776         platform_device_register(&smc91x_device);
 777
 778         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 779                 struct amba_device *d = amba_devs[i];
 780                 amba_device_register(d, &iomem_resource);
 781         }
 782
 783 #ifdef CONFIG_LEDS
 784         leds_event = versatile_leds_event;
 785 #endif
 786 }
 787
 788 /*
 789  * Where is the timer (VA)?
 790  */
 791 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 792 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 793 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 794 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 795 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE)
 796
 797 /*
 798  * How long is the timer interval?
 799  */
 800 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 801 #if TIMER_INTERVAL >= 0x100000
 802 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 803 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 804 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 805 #elif TIMER_INTERVAL >= 0x10000
 806 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 807 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 808 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 809 #else
 810 #define TIMER_RELOAD    (TIMER_INTERVAL)
 811 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 812 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 813 #endif
 814
 815 /*
 816  * Returns number of ms since last clock interrupt.  Note that interrupts
 817  * will have been disabled by do_gettimeoffset()
 818  */
 819 static unsigned long versatile_gettimeoffset(void)
 820 {
 821         unsigned long ticks1, ticks2, status;
 822
 823         /*
 824          * Get the current number of ticks.  Note that there is a race
 825          * condition between us reading the timer and checking for
 826          * an interrupt.  We get around this by ensuring that the
 827          * counter has not reloaded between our two reads.
 828          */
 829         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 830         do {
 831                 ticks1 = ticks2;
 832                 status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
 833                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
 834         } while (ticks2 > ticks1);
 835
 836         /*
 837          * Number of ticks since last interrupt.
 838          */
 839         ticks1 = TIMER_RELOAD - ticks2;
 840
 841         /*
 842          * Interrupt pending?  If so, we've reloaded once already.
 843          *
 844          * FIXME: Need to check this is effectively timer 0 that expires
 845          */
 846         if (status & IRQMASK_TIMERINT0_1)
 847                 ticks1 += TIMER_RELOAD;
 848
 849         /*
 850          * Convert the ticks to usecs
 851          */
 852         return TICKS2USECS(ticks1);
 853 }
 854
 855 /*
 856  * IRQ handler for the timer
 857  */
 858 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 859 {
 860         write_seqlock(&xtime_lock);
 861
 862         // ...clear the interrupt
 863         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 864
 865         timer_tick(regs);
 866
 867         write_sequnlock(&xtime_lock);
 868
 869         return IRQ_HANDLED;
 870 }
 871
 872 static struct irqaction versatile_timer_irq = {
 873         .name           = "Versatile Timer Tick",
 874         .flags          = SA_INTERRUPT | SA_TIMER,
 875         .handler        = versatile_timer_interrupt,
 876 };
 877
 878 /*
 879  * Set up timer interrupt, and return the current time in seconds.
 880  */
 881 static void __init versatile_timer_init(void)
 882 {
 883         u32 val;
 884
 885         /*
 886          * set clock frequency:
 887          *      VERSATILE_REFCLK is 32KHz
 888          *      VERSATILE_TIMCLK is 1MHz
 889          */
 890         val = readl(__io_address(VERSATILE_SCTL_BASE));
 891         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 892                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 893                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 894                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 895                __io_address(VERSATILE_SCTL_BASE));
 896
 897         /*
 898          * Initialise to a known state (all timers off)
 899          */
 900         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 901         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 902         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 903         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 904
 905         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 906         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
 907         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
 908                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
 909
 910         /*
 911          * Make irqs happen for the system timer
 912          */
 913         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
 914 }
 915
 916 struct sys_timer versatile_timer = {
 917         .init           = versatile_timer_init,
 918         .offset         = versatile_gettimeoffset,
 919 };