arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/amba/pl022.h>
  32 #include <linux/io.h>
  33 #include <linux/gfp.h>
  34 #include <linux/clkdev.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <mach/hardware.h>
  50 #include <mach/platform.h>
  51 #include <asm/hardware/timer-sp.h>
  52
  53 #include <plat/clcd.h>
  54 #include <plat/fpga-irq.h>
  55 #include <plat/sched_clock.h>
  56
  57 #include "core.h"
  58
  59 /*
  60  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  61  * is the (PA >> 12).
  62  *
  63  * Setup a VA for the Versatile Vectored Interrupt Controller.
  64  */
  65 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  66 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  67
  68 static struct fpga_irq_data sic_irq = {
  69         .base           = VA_SIC_BASE,
  70         .irq_start      = IRQ_SIC_START,
  71         .chip.name      = "SIC",
  72 };
  73
  74 #if 1
  75 #define IRQ_MMCI0A      IRQ_VICSOURCE22
  76 #define IRQ_AACI        IRQ_VICSOURCE24
  77 #define IRQ_ETH         IRQ_VICSOURCE25
  78 #define PIC_MASK        0xFFD00000
  79 #else
  80 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
  81 #define IRQ_AACI        IRQ_SIC_AACI
  82 #define IRQ_ETH         IRQ_SIC_ETH
  83 #define PIC_MASK        0
  84 #endif
  85
  86 void __init versatile_init_irq(void)
  87 {
  88         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
  89
  90         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  91
  92         fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
  93
  94         /*
  95          * Interrupts on secondary controller from 0 to 8 are routed to
  96          * source 31 on PIC.
  97          * Interrupts from 21 to 31 are routed directly to the VIC on
  98          * the corresponding number on primary controller. This is controlled
  99          * by setting PIC_ENABLEx.
 100          */
 101         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 102 }
 103
 104 static struct map_desc versatile_io_desc[] __initdata = {
 105         {
 106                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 107                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 108                 .length         = SZ_4K,
 109                 .type           = MT_DEVICE
 110         }, {
 111                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 112                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 113                 .length         = SZ_4K,
 114                 .type           = MT_DEVICE
 115         }, {
 116                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 117                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE
 120         }, {
 121                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 122                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 123                 .length         = SZ_4K * 9,
 124                 .type           = MT_DEVICE
 125         },
 126 #ifdef CONFIG_MACH_VERSATILE_AB
 127         {
 128                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 129                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 130                 .length         = SZ_4K,
 131                 .type           = MT_DEVICE
 132         }, {
 133                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 134                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 135                 .length         = SZ_64M,
 136                 .type           = MT_DEVICE
 137         },
 138 #endif
 139 #ifdef CONFIG_DEBUG_LL
 140         {
 141                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 142                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 143                 .length         = SZ_4K,
 144                 .type           = MT_DEVICE
 145         },
 146 #endif
 147 #ifdef CONFIG_PCI
 148         {
 149                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 150                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 151                 .length         = SZ_4K,
 152                 .type           = MT_DEVICE
 153         }, {
 154                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 155                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 156                 .length         = VERSATILE_PCI_BASE_SIZE,
 157                 .type           = MT_DEVICE
 158         }, {
 159                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 160                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 161                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 162                 .type           = MT_DEVICE
 163         },
 164 #if 0
 165         {
 166                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 167                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 168                 .length         = SZ_16M,
 169                 .type           = MT_DEVICE
 170         }, {
 171                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 172                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 173                 .length         = SZ_16M,
 174                 .type           = MT_DEVICE
 175         }, {
 176                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 177                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 178                 .length         = SZ_16M,
 179                 .type           = MT_DEVICE
 180         },
 181 #endif
 182 #endif
 183 };
 184
 185 void __init versatile_map_io(void)
 186 {
 187         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 188 }
 189
 190
 191 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 192
 193 static int versatile_flash_init(void)
 194 {
 195         u32 val;
 196
 197         val = __raw_readl(VERSATILE_FLASHCTRL);
 198         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 199         __raw_writel(val, VERSATILE_FLASHCTRL);
 200
 201         return 0;
 202 }
 203
 204 static void versatile_flash_exit(void)
 205 {
 206         u32 val;
 207
 208         val = __raw_readl(VERSATILE_FLASHCTRL);
 209         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 210         __raw_writel(val, VERSATILE_FLASHCTRL);
 211 }
 212
 213 static void versatile_flash_set_vpp(int on)
 214 {
 215         u32 val;
 216
 217         val = __raw_readl(VERSATILE_FLASHCTRL);
 218         if (on)
 219                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 220         else
 221                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 222         __raw_writel(val, VERSATILE_FLASHCTRL);
 223 }
 224
 225 static struct flash_platform_data versatile_flash_data = {
 226         .map_name               = "cfi_probe",
 227         .width                  = 4,
 228         .init                   = versatile_flash_init,
 229         .exit                   = versatile_flash_exit,
 230         .set_vpp                = versatile_flash_set_vpp,
 231 };
 232
 233 static struct resource versatile_flash_resource = {
 234         .start                  = VERSATILE_FLASH_BASE,
 235         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 236         .flags                  = IORESOURCE_MEM,
 237 };
 238
 239 static struct platform_device versatile_flash_device = {
 240         .name                   = "armflash",
 241         .id                     = 0,
 242         .dev                    = {
 243                 .platform_data  = &versatile_flash_data,
 244         },
 245         .num_resources          = 1,
 246         .resource               = &versatile_flash_resource,
 247 };
 248
 249 static struct resource smc91x_resources[] = {
 250         [0] = {
 251                 .start          = VERSATILE_ETH_BASE,
 252                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 253                 .flags          = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start          = IRQ_ETH,
 257                 .end            = IRQ_ETH,
 258                 .flags          = IORESOURCE_IRQ,
 259         },
 260 };
 261
 262 static struct platform_device smc91x_device = {
 263         .name           = "smc91x",
 264         .id             = 0,
 265         .num_resources  = ARRAY_SIZE(smc91x_resources),
 266         .resource       = smc91x_resources,
 267 };
 268
 269 static struct resource versatile_i2c_resource = {
 270         .start                  = VERSATILE_I2C_BASE,
 271         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 272         .flags                  = IORESOURCE_MEM,
 273 };
 274
 275 static struct platform_device versatile_i2c_device = {
 276         .name                   = "versatile-i2c",
 277         .id                     = 0,
 278         .num_resources          = 1,
 279         .resource               = &versatile_i2c_resource,
 280 };
 281
 282 static struct i2c_board_info versatile_i2c_board_info[] = {
 283         {
 284                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 285         },
 286 };
 287
 288 static int __init versatile_i2c_init(void)
 289 {
 290         return i2c_register_board_info(0, versatile_i2c_board_info,
 291                                        ARRAY_SIZE(versatile_i2c_board_info));
 292 }
 293 arch_initcall(versatile_i2c_init);
 294
 295 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 296
 297 unsigned int mmc_status(struct device *dev)
 298 {
 299         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 300         u32 mask;
 301
 302         if (adev->res.start == VERSATILE_MMCI0_BASE)
 303                 mask = 1;
 304         else
 305                 mask = 2;
 306
 307         return readl(VERSATILE_SYSMCI) & mask;
 308 }
 309
 310 static struct mmci_platform_data mmc0_plat_data = {
 311         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 312         .status         = mmc_status,
 313         .gpio_wp        = -1,
 314         .gpio_cd        = -1,
 315 };
 316
 317 static struct resource chalcd_resources[] = {
 318         {
 319                 .start = VERSATILE_CHAR_LCD_BASE,
 320                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 321                 .flags = IORESOURCE_MEM,
 322         },
 323 };
 324
 325 static struct platform_device char_lcd_device = {
 326         .name           =       "arm-charlcd",
 327         .id             =       -1,
 328         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 329         .resource       =       char_lcd_resources,
 330 };
 331
 332 /*
 333  * Clock handling
 334  */
 335 static const struct icst_params versatile_oscvco_params = {
 336         .ref            = 24000000,
 337         .vco_max        = ICST307_VCO_MAX,
 338         .vco_min        = ICST307_VCO_MIN,
 339         .vd_min         = 4 + 8,
 340         .vd_max         = 511 + 8,
 341         .rd_min         = 1 + 2,
 342         .rd_max         = 127 + 2,
 343         .s2div          = icst307_s2div,
 344         .idx2s          = icst307_idx2s,
 345 };
 346
 347 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 348 {
 349         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 350         u32 val;
 351
 352         val = readl(clk->vcoreg) & ~0x7ffff;
 353         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 354
 355         writel(0xa05f, sys_lock);
 356         writel(val, clk->vcoreg);
 357         writel(0, sys_lock);
 358 }
 359
 360 static const struct clk_ops osc4_clk_ops = {
 361         .round  = icst_clk_round,
 362         .set    = icst_clk_set,
 363         .setvco = versatile_oscvco_set,
 364 };
 365
 366 static struct clk osc4_clk = {
 367         .ops    = &osc4_clk_ops,
 368         .params = &versatile_oscvco_params,
 369 };
 370
 371 /*
 372  * These are fixed clocks.
 373  */
 374 static struct clk ref24_clk = {
 375         .rate   = 24000000,
 376 };
 377
 378 static struct clk dummy_apb_pclk;
 379
 380 static struct clk_lookup lookups[] = {
 381         {       /* AMBA bus clock */
 382                 .con_id         = "apb_pclk",
 383                 .clk            = &dummy_apb_pclk,
 384         }, {    /* UART0 */
 385                 .dev_id         = "dev:f1",
 386                 .clk            = &ref24_clk,
 387         }, {    /* UART1 */
 388                 .dev_id         = "dev:f2",
 389                 .clk            = &ref24_clk,
 390         }, {    /* UART2 */
 391                 .dev_id         = "dev:f3",
 392                 .clk            = &ref24_clk,
 393         }, {    /* UART3 */
 394                 .dev_id         = "fpga:09",
 395                 .clk            = &ref24_clk,
 396         }, {    /* KMI0 */
 397                 .dev_id         = "fpga:06",
 398                 .clk            = &ref24_clk,
 399         }, {    /* KMI1 */
 400                 .dev_id         = "fpga:07",
 401                 .clk            = &ref24_clk,
 402         }, {    /* MMC0 */
 403                 .dev_id         = "fpga:05",
 404                 .clk            = &ref24_clk,
 405         }, {    /* MMC1 */
 406                 .dev_id         = "fpga:0b",
 407                 .clk            = &ref24_clk,
 408         }, {    /* SSP */
 409                 .dev_id         = "dev:f4",
 410                 .clk            = &ref24_clk,
 411         }, {    /* CLCD */
 412                 .dev_id         = "dev:20",
 413                 .clk            = &osc4_clk,
 414         }
 415 };
 416
 417 /*
 418  * CLCD support.
 419  */
 420 #define SYS_CLCD_MODE_MASK      (3 << 0)
 421 #define SYS_CLCD_MODE_888       (0 << 0)
 422 #define SYS_CLCD_MODE_5551      (1 << 0)
 423 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 424 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 425 #define SYS_CLCD_NLCDIOON       (1 << 2)
 426 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 427 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 428 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 429 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 430 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 431 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 432 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 433 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 434
 435 static bool is_sanyo_2_5_lcd;
 436
 437 /*
 438  * Disable all display connectors on the interface module.
 439  */
 440 static void versatile_clcd_disable(struct clcd_fb *fb)
 441 {
 442         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 443         u32 val;
 444
 445         val = readl(sys_clcd);
 446         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 447         writel(val, sys_clcd);
 448
 449 #ifdef CONFIG_MACH_VERSATILE_AB
 450         /*
 451          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 452          */
 453         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 454                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 455                 unsigned long ctrl;
 456
 457                 ctrl = readl(versatile_ib2_ctrl);
 458                 ctrl &= ~0x01;
 459                 writel(ctrl, versatile_ib2_ctrl);
 460         }
 461 #endif
 462 }
 463
 464 /*
 465  * Enable the relevant connector on the interface module.
 466  */
 467 static void versatile_clcd_enable(struct clcd_fb *fb)
 468 {
 469         struct fb_var_screeninfo *var = &fb->fb.var;
 470         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 471         u32 val;
 472
 473         val = readl(sys_clcd);
 474         val &= ~SYS_CLCD_MODE_MASK;
 475
 476         switch (var->green.length) {
 477         case 5:
 478                 val |= SYS_CLCD_MODE_5551;
 479                 break;
 480         case 6:
 481                 if (var->red.offset == 0)
 482                         val |= SYS_CLCD_MODE_565_RLSB;
 483                 else
 484                         val |= SYS_CLCD_MODE_565_BLSB;
 485                 break;
 486         case 8:
 487                 val |= SYS_CLCD_MODE_888;
 488                 break;
 489         }
 490
 491         /*
 492          * Set the MUX
 493          */
 494         writel(val, sys_clcd);
 495
 496         /*
 497          * And now enable the PSUs
 498          */
 499         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 500         writel(val, sys_clcd);
 501
 502 #ifdef CONFIG_MACH_VERSATILE_AB
 503         /*
 504          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 505          */
 506         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 507                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 508                 unsigned long ctrl;
 509
 510                 ctrl = readl(versatile_ib2_ctrl);
 511                 ctrl |= 0x01;
 512                 writel(ctrl, versatile_ib2_ctrl);
 513         }
 514 #endif
 515 }
 516
 517 /*
 518  * Detect which LCD panel is connected, and return the appropriate
 519  * clcd_panel structure.  Note: we do not have any information on
 520  * the required timings for the 8.4in panel, so we presently assume
 521  * VGA timings.
 522  */
 523 static int versatile_clcd_setup(struct clcd_fb *fb)
 524 {
 525         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 526         const char *panel_name;
 527         u32 val;
 528
 529         is_sanyo_2_5_lcd = false;
 530
 531         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 532         if (val == SYS_CLCD_ID_SANYO_3_8)
 533                 panel_name = "Sanyo TM38QV67A02A";
 534         else if (val == SYS_CLCD_ID_SANYO_2_5) {
 535                 panel_name = "Sanyo QVGA Portrait";
 536                 is_sanyo_2_5_lcd = true;
 537         } else if (val == SYS_CLCD_ID_EPSON_2_2)
 538                 panel_name = "Epson L2F50113T00";
 539         else if (val == SYS_CLCD_ID_VGA)
 540                 panel_name = "VGA";
 541         else {
 542                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 543                         val);
 544                 panel_name = "VGA";
 545         }
 546
 547         fb->panel = versatile_clcd_get_panel(panel_name);
 548         if (!fb->panel)
 549                 return -EINVAL;
 550
 551         return versatile_clcd_setup_dma(fb, SZ_1M);
 552 }
 553
 554 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 555 {
 556         clcdfb_decode(fb, regs);
 557
 558         /* Always clear BGR for RGB565: we do the routing externally */
 559         if (fb->fb.var.green.length == 6)
 560                 regs->cntl &= ~CNTL_BGR;
 561 }
 562
 563 static struct clcd_board clcd_plat_data = {
 564         .name           = "Versatile",
 565         .caps           = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
 566         .check          = clcdfb_check,
 567         .decode         = versatile_clcd_decode,
 568         .disable        = versatile_clcd_disable,
 569         .enable         = versatile_clcd_enable,
 570         .setup          = versatile_clcd_setup,
 571         .mmap           = versatile_clcd_mmap_dma,
 572         .remove         = versatile_clcd_remove_dma,
 573 };
 574
 575 static struct pl061_platform_data gpio0_plat_data = {
 576         .gpio_base      = 0,
 577         .irq_base       = IRQ_GPIO0_START,
 578 };
 579
 580 static struct pl061_platform_data gpio1_plat_data = {
 581         .gpio_base      = 8,
 582         .irq_base       = IRQ_GPIO1_START,
 583 };
 584
 585 static struct pl022_ssp_controller ssp0_plat_data = {
 586         .bus_id = 0,
 587         .enable_dma = 0,
 588         .num_chipselect = 1,
 589 };
 590
 591 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 592 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 593 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 594 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 595
 596 /*
 597  * These devices are connected directly to the multi-layer AHB switch
 598  */
 599 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 600 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 601 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 602 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 603
 604 /*
 605  * These devices are connected via the core APB bridge
 606  */
 607 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 608 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 609 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 610 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 611 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 612
 613 /*
 614  * These devices are connected via the DMA APB bridge
 615  */
 616 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 617 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 618 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 619 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 620 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 621
 622 /* FPGA Primecells */
 623 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 624 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 625 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 626 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 627
 628 /* DevChip Primecells */
 629 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 630 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 631 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 632 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 633 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 634 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 635 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 636 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 637 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 638 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 639 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 640 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 641 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 642 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 643
 644 static struct amba_device *amba_devs[] __initdata = {
 645         &dmac_device,
 646         &uart0_device,
 647         &uart1_device,
 648         &uart2_device,
 649         &smc_device,
 650         &mpmc_device,
 651         &clcd_device,
 652         &sctl_device,
 653         &wdog_device,
 654         &gpio0_device,
 655         &gpio1_device,
 656         &rtc_device,
 657         &sci0_device,
 658         &ssp0_device,
 659         &aaci_device,
 660         &mmc0_device,
 661         &kmi0_device,
 662         &kmi1_device,
 663 };
 664
 665 #ifdef CONFIG_LEDS
 666 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 667
 668 static void versatile_leds_event(led_event_t ledevt)
 669 {
 670         unsigned long flags;
 671         u32 val;
 672
 673         local_irq_save(flags);
 674         val = readl(VA_LEDS_BASE);
 675
 676         switch (ledevt) {
 677         case led_idle_start:
 678                 val = val & ~VERSATILE_SYS_LED0;
 679                 break;
 680
 681         case led_idle_end:
 682                 val = val | VERSATILE_SYS_LED0;
 683                 break;
 684
 685         case led_timer:
 686                 val = val ^ VERSATILE_SYS_LED1;
 687                 break;
 688
 689         case led_halted:
 690                 val = 0;
 691                 break;
 692
 693         default:
 694                 break;
 695         }
 696
 697         writel(val, VA_LEDS_BASE);
 698         local_irq_restore(flags);
 699 }
 700 #endif  /* CONFIG_LEDS */
 701
 702 /* Early initializations */
 703 void __init versatile_init_early(void)
 704 {
 705         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 706
 707         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
 708         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 709
 710         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
 711 }
 712
 713 void __init versatile_init(void)
 714 {
 715         int i;
 716
 717         platform_device_register(&versatile_flash_device);
 718         platform_device_register(&versatile_i2c_device);
 719         platform_device_register(&smc91x_device);
 720         platform_device_register(&char_lcd_device);
 721
 722         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 723                 struct amba_device *d = amba_devs[i];
 724                 amba_device_register(d, &iomem_resource);
 725         }
 726
 727 #ifdef CONFIG_LEDS
 728         leds_event = versatile_leds_event;
 729 #endif
 730 }
 731
 732 /*
 733  * Where is the timer (VA)?
 734  */
 735 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 736 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 737 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 738 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 739
 740 /*
 741  * Set up timer interrupt, and return the current time in seconds.
 742  */
 743 static void __init versatile_timer_init(void)
 744 {
 745         u32 val;
 746
 747         /*
 748          * set clock frequency:
 749          *      VERSATILE_REFCLK is 32KHz
 750          *      VERSATILE_TIMCLK is 1MHz
 751          */
 752         val = readl(__io_address(VERSATILE_SCTL_BASE));
 753         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 754                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 755                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 756                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 757                __io_address(VERSATILE_SCTL_BASE));
 758
 759         /*
 760          * Initialise to a known state (all timers off)
 761          */
 762         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 763         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 764         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 765         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 766
 767         sp804_clocksource_init(TIMER3_VA_BASE);
 768         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 769 }
 770
 771 struct sys_timer versatile_timer = {
 772         .init           = versatile_timer_init,
 773 };
 774