ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
[sfrench/cifs-2.6.git] / arch / arm / mach-tegra / sleep-tegra30.S
1 /*
2  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16
17 #include <linux/linkage.h>
18
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/cache.h>
22
23 #include "irammap.h"
24 #include "fuse.h"
25 #include "sleep.h"
26 #include "flowctrl.h"
27
28 #define EMC_CFG                         0xc
29 #define EMC_ADR_CFG                     0x10
30 #define EMC_TIMING_CONTROL              0x28
31 #define EMC_REFRESH                     0x70
32 #define EMC_NOP                         0xdc
33 #define EMC_SELF_REF                    0xe0
34 #define EMC_MRW                         0xe8
35 #define EMC_FBIO_CFG5                   0x104
36 #define EMC_AUTO_CAL_CONFIG             0x2a4
37 #define EMC_AUTO_CAL_INTERVAL           0x2a8
38 #define EMC_AUTO_CAL_STATUS             0x2ac
39 #define EMC_REQ_CTRL                    0x2b0
40 #define EMC_CFG_DIG_DLL                 0x2bc
41 #define EMC_EMC_STATUS                  0x2b4
42 #define EMC_ZCAL_INTERVAL               0x2e0
43 #define EMC_ZQ_CAL                      0x2ec
44 #define EMC_XM2VTTGENPADCTRL            0x310
45 #define EMC_XM2VTTGENPADCTRL2           0x314
46
47 #define PMC_CTRL                        0x0
48 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
49
50 #define PMC_PLLP_WB0_OVERRIDE           0xf8
51 #define PMC_IO_DPD_REQ                  0x1b8
52 #define PMC_IO_DPD_STATUS               0x1bc
53
54 #define CLK_RESET_CCLK_BURST            0x20
55 #define CLK_RESET_CCLK_DIVIDER          0x24
56 #define CLK_RESET_SCLK_BURST            0x28
57 #define CLK_RESET_SCLK_DIVIDER          0x2c
58
59 #define CLK_RESET_PLLC_BASE             0x80
60 #define CLK_RESET_PLLC_MISC             0x8c
61 #define CLK_RESET_PLLM_BASE             0x90
62 #define CLK_RESET_PLLM_MISC             0x9c
63 #define CLK_RESET_PLLP_BASE             0xa0
64 #define CLK_RESET_PLLP_MISC             0xac
65 #define CLK_RESET_PLLA_BASE             0xb0
66 #define CLK_RESET_PLLA_MISC             0xbc
67 #define CLK_RESET_PLLX_BASE             0xe0
68 #define CLK_RESET_PLLX_MISC             0xe4
69 #define CLK_RESET_PLLX_MISC3            0x518
70 #define CLK_RESET_PLLX_MISC3_IDDQ       3
71 #define CLK_RESET_PLLM_MISC_IDDQ        5
72 #define CLK_RESET_PLLC_MISC_IDDQ        26
73
74 #define CLK_RESET_CLK_SOURCE_MSELECT    0x3b4
75
76 #define MSELECT_CLKM                    (0x3 << 30)
77
78 #define LOCK_DELAY 50 /* safety delay after lock is detected */
79
80 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
81
82 .macro emc_device_mask, rd, base
83         ldr     \rd, [\base, #EMC_ADR_CFG]
84         tst     \rd, #0x1
85         moveq   \rd, #(0x1 << 8)                @ just 1 device
86         movne   \rd, #(0x3 << 8)                @ 2 devices
87 .endm
88
89 .macro emc_timing_update, rd, base
90         mov     \rd, #1
91         str     \rd, [\base, #EMC_TIMING_CONTROL]
92 1001:
93         ldr     \rd, [\base, #EMC_EMC_STATUS]
94         tst     \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
95         bne     1001b
96 .endm
97
98 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
99         ldr     \rd, [\r_car_base, #\pll_base]
100         tst     \rd, #(1 << 30)
101         orreq   \rd, \rd, #(1 << 30)
102         streq   \rd, [\r_car_base, #\pll_base]
103         /* Enable lock detector */
104         .if     \pll_misc
105         ldr     \rd, [\r_car_base, #\pll_misc]
106         bic     \rd, \rd, #(1 << 18)
107         str     \rd, [\r_car_base, #\pll_misc]
108         ldr     \rd, [\r_car_base, #\pll_misc]
109         ldr     \rd, [\r_car_base, #\pll_misc]
110         orr     \rd, \rd, #(1 << 18)
111         str     \rd, [\r_car_base, #\pll_misc]
112         .endif
113 .endm
114
115 .macro pll_locked, rd, r_car_base, pll_base
116 1:
117         ldr     \rd, [\r_car_base, #\pll_base]
118         tst     \rd, #(1 << 27)
119         beq     1b
120 .endm
121
122 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
123         ldr     \rd, [\car, #\iddq]
124         bic     \rd, \rd, #(1<<\iddq_bit)
125         str     \rd, [\car, #\iddq]
126 .endm
127
128 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
129         ldr     \rd, [\car, #\iddq]
130         orr     \rd, \rd, #(1<<\iddq_bit)
131         str     \rd, [\car, #\iddq]
132 .endm
133
134 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
135 /*
136  * tegra30_hotplug_shutdown(void)
137  *
138  * Powergates the current CPU.
139  * Should never return.
140  */
141 ENTRY(tegra30_hotplug_shutdown)
142         /* Powergate this CPU */
143         mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
144         bl      tegra30_cpu_shutdown
145         ret     lr                      @ should never get here
146 ENDPROC(tegra30_hotplug_shutdown)
147
148 /*
149  * tegra30_cpu_shutdown(unsigned long flags)
150  *
151  * Puts the current CPU in wait-for-event mode on the flow controller
152  * and powergates it -- flags (in R0) indicate the request type.
153  *
154  * r10 = SoC ID
155  * corrupts r0-r4, r10-r12
156  */
157 ENTRY(tegra30_cpu_shutdown)
158         cpu_id  r3
159         tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
160         cmp     r10, #TEGRA30
161         bne     _no_cpu0_chk    @ It's not Tegra30
162
163         cmp     r3, #0
164         reteq   lr              @ Must never be called for CPU 0
165 _no_cpu0_chk:
166
167         ldr     r12, =TEGRA_FLOW_CTRL_VIRT
168         cpu_to_csr_reg r1, r3
169         add     r1, r1, r12     @ virtual CSR address for this CPU
170         cpu_to_halt_reg r2, r3
171         add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
172
173         /*
174          * Clear this CPU's "event" and "interrupt" flags and power gate
175          * it when halting but not before it is in the "WFE" state.
176          */
177         movw    r12, \
178                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
179                 FLOW_CTRL_CSR_ENABLE
180         cmp     r10, #TEGRA30
181         moveq   r4, #(1 << 4)                   @ wfe bitmap
182         movne   r4, #(1 << 8)                   @ wfi bitmap
183  ARM(   orr     r12, r12, r4, lsl r3    )
184  THUMB( lsl     r4, r4, r3              )
185  THUMB( orr     r12, r12, r4            )
186         str     r12, [r1]
187
188         /* Halt this CPU. */
189         mov     r3, #0x400
190 delay_1:
191         subs    r3, r3, #1                      @ delay as a part of wfe war.
192         bge     delay_1;
193         cpsid   a                               @ disable imprecise aborts.
194         ldr     r3, [r1]                        @ read CSR
195         str     r3, [r1]                        @ clear CSR
196
197         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
198         beq     flow_ctrl_setting_for_lp2
199
200         /* flow controller set up for hotplug */
201         mov     r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
202         b       flow_ctrl_done
203 flow_ctrl_setting_for_lp2:
204         /* flow controller set up for LP2 */
205         cmp     r10, #TEGRA30
206         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
207         movne   r3, #FLOW_CTRL_WAITEVENT
208         orrne   r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
209         orrne   r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
210 flow_ctrl_done:
211         cmp     r10, #TEGRA30
212         str     r3, [r2]
213         ldr     r0, [r2]
214         b       wfe_war
215
216 __cpu_reset_again:
217         dsb
218         .align 5
219         wfeeq                                   @ CPU should be power gated here
220         wfine
221 wfe_war:
222         b       __cpu_reset_again
223
224         /*
225          * 38 nop's, which fills reset of wfe cache line and
226          * 4 more cachelines with nop
227          */
228         .rept 38
229         nop
230         .endr
231         b       .                               @ should never get here
232
233 ENDPROC(tegra30_cpu_shutdown)
234 #endif
235
236 #ifdef CONFIG_PM_SLEEP
237 /*
238  * tegra30_sleep_core_finish(unsigned long v2p)
239  *
240  * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
241  * tegra30_tear_down_core in IRAM
242  */
243 ENTRY(tegra30_sleep_core_finish)
244         /* Flush, disable the L1 data cache and exit SMP */
245         bl      tegra_disable_clean_inv_dcache
246
247         /*
248          * Preload all the address literals that are needed for the
249          * CPU power-gating process, to avoid loading from SDRAM which
250          * are not supported once SDRAM is put into self-refresh.
251          * LP0 / LP1 use physical address, since the MMU needs to be
252          * disabled before putting SDRAM into self-refresh to avoid
253          * memory access due to page table walks.
254          */
255         mov32   r4, TEGRA_PMC_BASE
256         mov32   r5, TEGRA_CLK_RESET_BASE
257         mov32   r6, TEGRA_FLOW_CTRL_BASE
258         mov32   r7, TEGRA_TMRUS_BASE
259
260         mov32   r3, tegra_shut_off_mmu
261         add     r3, r3, r0
262
263         mov32   r0, tegra30_tear_down_core
264         mov32   r1, tegra30_iram_start
265         sub     r0, r0, r1
266         mov32   r1, TEGRA_IRAM_LPx_RESUME_AREA
267         add     r0, r0, r1
268
269         ret     r3
270 ENDPROC(tegra30_sleep_core_finish)
271
272 /*
273  * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
274  *
275  * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
276  */
277 ENTRY(tegra30_sleep_cpu_secondary_finish)
278         mov     r7, lr
279
280         /* Flush and disable the L1 data cache */
281         mov     r0, #TEGRA_FLUSH_CACHE_LOUIS
282         bl      tegra_disable_clean_inv_dcache
283
284         /* Powergate this CPU. */
285         mov     r0, #0                          @ power mode flags (!hotplug)
286         bl      tegra30_cpu_shutdown
287         mov     r0, #1                          @ never return here
288         ret     r7
289 ENDPROC(tegra30_sleep_cpu_secondary_finish)
290
291 /*
292  * tegra30_tear_down_cpu
293  *
294  * Switches the CPU to enter sleep.
295  */
296 ENTRY(tegra30_tear_down_cpu)
297         mov32   r6, TEGRA_FLOW_CTRL_BASE
298
299         b       tegra30_enter_sleep
300 ENDPROC(tegra30_tear_down_cpu)
301
302 /* START OF ROUTINES COPIED TO IRAM */
303         .align L1_CACHE_SHIFT
304         .globl tegra30_iram_start
305 tegra30_iram_start:
306
307 /*
308  * tegra30_lp1_reset
309  *
310  * reset vector for LP1 restore; copied into IRAM during suspend.
311  * Brings the system back up to a safe staring point (SDRAM out of
312  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
313  * system clock running on the same PLL that it suspended at), and
314  * jumps to tegra_resume to restore virtual addressing.
315  * The physical address of tegra_resume expected to be stored in
316  * PMC_SCRATCH41.
317  *
318  * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
319  */
320 ENTRY(tegra30_lp1_reset)
321         /*
322          * The CPU and system bus are running at 32KHz and executing from
323          * IRAM when this code is executed; immediately switch to CLKM and
324          * enable PLLP, PLLM, PLLC, PLLA and PLLX.
325          */
326         mov32   r0, TEGRA_CLK_RESET_BASE
327
328         mov     r1, #(1 << 28)
329         str     r1, [r0, #CLK_RESET_SCLK_BURST]
330         str     r1, [r0, #CLK_RESET_CCLK_BURST]
331         mov     r1, #0
332         str     r1, [r0, #CLK_RESET_CCLK_DIVIDER]
333         str     r1, [r0, #CLK_RESET_SCLK_DIVIDER]
334
335         tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
336         cmp     r10, #TEGRA30
337         beq     _no_pll_iddq_exit
338
339         pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
340         pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
341         pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
342
343         mov32   r7, TEGRA_TMRUS_BASE
344         ldr     r1, [r7]
345         add     r1, r1, #2
346         wait_until r1, r7, r3
347
348         /* enable PLLM via PMC */
349         mov32   r2, TEGRA_PMC_BASE
350         ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
351         orr     r1, r1, #(1 << 12)
352         str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
353
354         pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
355         pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
356         pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
357
358         b       _pll_m_c_x_done
359
360 _no_pll_iddq_exit:
361         /* enable PLLM via PMC */
362         mov32   r2, TEGRA_PMC_BASE
363         ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
364         orr     r1, r1, #(1 << 12)
365         str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
366
367         pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
368         pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
369         pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
370
371 _pll_m_c_x_done:
372         pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
373         pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
374
375         pll_locked r1, r0, CLK_RESET_PLLM_BASE
376         pll_locked r1, r0, CLK_RESET_PLLP_BASE
377         pll_locked r1, r0, CLK_RESET_PLLA_BASE
378         pll_locked r1, r0, CLK_RESET_PLLC_BASE
379         pll_locked r1, r0, CLK_RESET_PLLX_BASE
380
381         mov32   r7, TEGRA_TMRUS_BASE
382         ldr     r1, [r7]
383         add     r1, r1, #LOCK_DELAY
384         wait_until r1, r7, r3
385
386         adr     r5, tegra_sdram_pad_save
387
388         ldr     r4, [r5, #0x18]         @ restore CLK_SOURCE_MSELECT
389         str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
390
391         ldr     r4, [r5, #0x1C]         @ restore SCLK_BURST
392         str     r4, [r0, #CLK_RESET_SCLK_BURST]
393
394         cmp     r10, #TEGRA30
395         movweq  r4, #:lower16:((1 << 28) | (0x8))       @ burst policy is PLLX
396         movteq  r4, #:upper16:((1 << 28) | (0x8))
397         movwne  r4, #:lower16:((1 << 28) | (0xe))
398         movtne  r4, #:upper16:((1 << 28) | (0xe))
399         str     r4, [r0, #CLK_RESET_CCLK_BURST]
400
401         /* Restore pad power state to normal */
402         ldr     r1, [r5, #0x14]         @ PMC_IO_DPD_STATUS
403         mvn     r1, r1
404         bic     r1, r1, #(1 << 31)
405         orr     r1, r1, #(1 << 30)
406         str     r1, [r2, #PMC_IO_DPD_REQ]       @ DPD_OFF
407
408         cmp     r10, #TEGRA30
409         movweq  r0, #:lower16:TEGRA_EMC_BASE    @ r0 reserved for emc base
410         movteq  r0, #:upper16:TEGRA_EMC_BASE
411         cmp     r10, #TEGRA114
412         movweq  r0, #:lower16:TEGRA_EMC0_BASE
413         movteq  r0, #:upper16:TEGRA_EMC0_BASE
414         cmp     r10, #TEGRA124
415         movweq  r0, #:lower16:TEGRA124_EMC_BASE
416         movteq  r0, #:upper16:TEGRA124_EMC_BASE
417
418 exit_self_refresh:
419         ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
420         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
421         ldr     r1, [r5, #0x10]         @ restore EMC_XM2VTTGENPADCTRL2
422         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
423         ldr     r1, [r5, #0x8]          @ restore EMC_AUTO_CAL_INTERVAL
424         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
425
426         /* Relock DLL */
427         ldr     r1, [r0, #EMC_CFG_DIG_DLL]
428         orr     r1, r1, #(1 << 30)      @ set DLL_RESET
429         str     r1, [r0, #EMC_CFG_DIG_DLL]
430
431         emc_timing_update r1, r0
432
433         cmp     r10, #TEGRA114
434         movweq  r1, #:lower16:TEGRA_EMC1_BASE
435         movteq  r1, #:upper16:TEGRA_EMC1_BASE
436         cmpeq   r0, r1
437
438         ldr     r1, [r0, #EMC_AUTO_CAL_CONFIG]
439         orr     r1, r1, #(1 << 31)      @ set AUTO_CAL_ACTIVE
440         orreq   r1, r1, #(1 << 27)      @ set slave mode for channel 1
441         str     r1, [r0, #EMC_AUTO_CAL_CONFIG]
442
443 emc_wait_auto_cal_onetime:
444         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
445         tst     r1, #(1 << 31)          @ wait until AUTO_CAL_ACTIVE is cleared
446         bne     emc_wait_auto_cal_onetime
447
448         ldr     r1, [r0, #EMC_CFG]
449         bic     r1, r1, #(1 << 31)      @ disable DRAM_CLK_STOP_PD
450         str     r1, [r0, #EMC_CFG]
451
452         mov     r1, #0
453         str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
454         mov     r1, #1
455         cmp     r10, #TEGRA30
456         streq   r1, [r0, #EMC_NOP]
457         streq   r1, [r0, #EMC_NOP]
458         streq   r1, [r0, #EMC_REFRESH]
459
460         emc_device_mask r1, r0
461
462 exit_selfrefresh_loop:
463         ldr     r2, [r0, #EMC_EMC_STATUS]
464         ands    r2, r2, r1
465         bne     exit_selfrefresh_loop
466
467         lsr     r1, r1, #8              @ devSel, bit0:dev0, bit1:dev1
468
469         mov32   r7, TEGRA_TMRUS_BASE
470         ldr     r2, [r0, #EMC_FBIO_CFG5]
471
472         and     r2, r2, #3              @ check DRAM_TYPE
473         cmp     r2, #2
474         beq     emc_lpddr2
475
476         /* Issue a ZQ_CAL for dev0 - DDR3 */
477         mov32   r2, 0x80000011          @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
478         str     r2, [r0, #EMC_ZQ_CAL]
479         ldr     r2, [r7]
480         add     r2, r2, #10
481         wait_until r2, r7, r3
482
483         tst     r1, #2
484         beq     zcal_done
485
486         /* Issue a ZQ_CAL for dev1 - DDR3 */
487         mov32   r2, 0x40000011          @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
488         str     r2, [r0, #EMC_ZQ_CAL]
489         ldr     r2, [r7]
490         add     r2, r2, #10
491         wait_until r2, r7, r3
492         b       zcal_done
493
494 emc_lpddr2:
495         /* Issue a ZQ_CAL for dev0 - LPDDR2 */
496         mov32   r2, 0x800A00AB          @ DEV_SELECTION=2, MA=10, OP=0xAB
497         str     r2, [r0, #EMC_MRW]
498         ldr     r2, [r7]
499         add     r2, r2, #1
500         wait_until r2, r7, r3
501
502         tst     r1, #2
503         beq     zcal_done
504
505         /* Issue a ZQ_CAL for dev0 - LPDDR2 */
506         mov32   r2, 0x400A00AB          @ DEV_SELECTION=1, MA=10, OP=0xAB
507         str     r2, [r0, #EMC_MRW]
508         ldr     r2, [r7]
509         add     r2, r2, #1
510         wait_until r2, r7, r3
511
512 zcal_done:
513         mov     r1, #0                  @ unstall all transactions
514         str     r1, [r0, #EMC_REQ_CTRL]
515         ldr     r1, [r5, #0x4]          @ restore EMC_ZCAL_INTERVAL
516         str     r1, [r0, #EMC_ZCAL_INTERVAL]
517         ldr     r1, [r5, #0x0]          @ restore EMC_CFG
518         str     r1, [r0, #EMC_CFG]
519
520         /* Tegra114 had dual EMC channel, now config the other one */
521         cmp     r10, #TEGRA114
522         bne     __no_dual_emc_chanl
523         mov32   r1, TEGRA_EMC1_BASE
524         cmp     r0, r1
525         movne   r0, r1
526         addne   r5, r5, #0x20
527         bne     exit_self_refresh
528 __no_dual_emc_chanl:
529
530         mov32   r0, TEGRA_PMC_BASE
531         ldr     r0, [r0, #PMC_SCRATCH41]
532         ret     r0                      @ jump to tegra_resume
533 ENDPROC(tegra30_lp1_reset)
534
535         .align  L1_CACHE_SHIFT
536 tegra30_sdram_pad_address:
537         .word   TEGRA_EMC_BASE + EMC_CFG                                @0x0
538         .word   TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL                      @0x4
539         .word   TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL                  @0x8
540         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL                   @0xc
541         .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2                  @0x10
542         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
543         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
544         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
545 tegra30_sdram_pad_address_end:
546
547 tegra114_sdram_pad_address:
548         .word   TEGRA_EMC0_BASE + EMC_CFG                               @0x0
549         .word   TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL                     @0x4
550         .word   TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL                 @0x8
551         .word   TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL                  @0xc
552         .word   TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2                 @0x10
553         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
554         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
555         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
556         .word   TEGRA_EMC1_BASE + EMC_CFG                               @0x20
557         .word   TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL                     @0x24
558         .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
559         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
560         .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
561 tegra114_sdram_pad_adress_end:
562
563 tegra124_sdram_pad_address:
564         .word   TEGRA124_EMC_BASE + EMC_CFG                             @0x0
565         .word   TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL                   @0x4
566         .word   TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL               @0x8
567         .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL                @0xc
568         .word   TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2               @0x10
569         .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
570         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
571         .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
572 tegra124_sdram_pad_address_end:
573
574 tegra30_sdram_pad_size:
575         .word   tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
576
577 tegra114_sdram_pad_size:
578         .word   tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
579
580         .type   tegra_sdram_pad_save, %object
581 tegra_sdram_pad_save:
582         .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
583         .long   0
584         .endr
585
586 /*
587  * tegra30_tear_down_core
588  *
589  * copied into and executed from IRAM
590  * puts memory in self-refresh for LP0 and LP1
591  */
592 tegra30_tear_down_core:
593         bl      tegra30_sdram_self_refresh
594         bl      tegra30_switch_cpu_to_clk32k
595         b       tegra30_enter_sleep
596
597 /*
598  * tegra30_switch_cpu_to_clk32k
599  *
600  * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
601  * to the 32KHz clock.
602  * r4 = TEGRA_PMC_BASE
603  * r5 = TEGRA_CLK_RESET_BASE
604  * r6 = TEGRA_FLOW_CTRL_BASE
605  * r7 = TEGRA_TMRUS_BASE
606  * r10= SoC ID
607  */
608 tegra30_switch_cpu_to_clk32k:
609         /*
610          * start by jumping to CLKM to safely disable PLLs, then jump to
611          * CLKS.
612          */
613         mov     r0, #(1 << 28)
614         str     r0, [r5, #CLK_RESET_SCLK_BURST]
615         /* 2uS delay delay between changing SCLK and CCLK */
616         ldr     r1, [r7]
617         add     r1, r1, #2
618         wait_until r1, r7, r9
619         str     r0, [r5, #CLK_RESET_CCLK_BURST]
620         mov     r0, #0
621         str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
622         str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
623
624         /* switch the clock source of mselect to be CLK_M */
625         ldr     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
626         orr     r0, r0, #MSELECT_CLKM
627         str     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
628
629         /* 2uS delay delay between changing SCLK and disabling PLLs */
630         ldr     r1, [r7]
631         add     r1, r1, #2
632         wait_until r1, r7, r9
633
634         /* disable PLLM via PMC in LP1 */
635         ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
636         bic     r0, r0, #(1 << 12)
637         str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
638
639         /* disable PLLP, PLLA, PLLC and PLLX */
640         ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
641         bic     r0, r0, #(1 << 30)
642         str     r0, [r5, #CLK_RESET_PLLP_BASE]
643         ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
644         bic     r0, r0, #(1 << 30)
645         str     r0, [r5, #CLK_RESET_PLLA_BASE]
646         ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
647         bic     r0, r0, #(1 << 30)
648         str     r0, [r5, #CLK_RESET_PLLC_BASE]
649         ldr     r0, [r5, #CLK_RESET_PLLX_BASE]
650         bic     r0, r0, #(1 << 30)
651         str     r0, [r5, #CLK_RESET_PLLX_BASE]
652
653         cmp     r10, #TEGRA30
654         beq     _no_pll_in_iddq
655         pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
656 _no_pll_in_iddq:
657
658         /* switch to CLKS */
659         mov     r0, #0  /* brust policy = 32KHz */
660         str     r0, [r5, #CLK_RESET_SCLK_BURST]
661
662         ret     lr
663
664 /*
665  * tegra30_enter_sleep
666  *
667  * uses flow controller to enter sleep state
668  * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
669  * executes from SDRAM with target state is LP2
670  * r6 = TEGRA_FLOW_CTRL_BASE
671  */
672 tegra30_enter_sleep:
673         cpu_id  r1
674
675         cpu_to_csr_reg  r2, r1
676         ldr     r0, [r6, r2]
677         orr     r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
678         orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
679         str     r0, [r6, r2]
680
681         tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
682         cmp     r10, #TEGRA30
683         mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
684         orreq   r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
685         orrne   r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
686
687         cpu_to_halt_reg r2, r1
688         str     r0, [r6, r2]
689         dsb
690         ldr     r0, [r6, r2] /* memory barrier */
691
692 halted:
693         isb
694         dsb
695         wfi     /* CPU should be power gated here */
696
697         /* !!!FIXME!!! Implement halt failure handler */
698         b       halted
699
700 /*
701  * tegra30_sdram_self_refresh
702  *
703  * called with MMU off and caches disabled
704  * must be executed from IRAM
705  * r4 = TEGRA_PMC_BASE
706  * r5 = TEGRA_CLK_RESET_BASE
707  * r6 = TEGRA_FLOW_CTRL_BASE
708  * r7 = TEGRA_TMRUS_BASE
709  * r10= SoC ID
710  */
711 tegra30_sdram_self_refresh:
712
713         adr     r8, tegra_sdram_pad_save
714         tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
715         cmp     r10, #TEGRA30
716         adreq   r2, tegra30_sdram_pad_address
717         ldreq   r3, tegra30_sdram_pad_size
718         cmp     r10, #TEGRA114
719         adreq   r2, tegra114_sdram_pad_address
720         ldreq   r3, tegra114_sdram_pad_size
721         cmp     r10, #TEGRA124
722         adreq   r2, tegra124_sdram_pad_address
723         ldreq   r3, tegra30_sdram_pad_size
724
725         mov     r9, #0
726
727 padsave:
728         ldr     r0, [r2, r9]            @ r0 is the addr in the pad_address
729
730         ldr     r1, [r0]
731         str     r1, [r8, r9]            @ save the content of the addr
732
733         add     r9, r9, #4
734         cmp     r3, r9
735         bne     padsave
736 padsave_done:
737
738         dsb
739
740         cmp     r10, #TEGRA30
741         ldreq   r0, =TEGRA_EMC_BASE     @ r0 reserved for emc base addr
742         cmp     r10, #TEGRA114
743         ldreq   r0, =TEGRA_EMC0_BASE
744         cmp     r10, #TEGRA124
745         ldreq   r0, =TEGRA124_EMC_BASE
746
747 enter_self_refresh:
748         cmp     r10, #TEGRA30
749         mov     r1, #0
750         str     r1, [r0, #EMC_ZCAL_INTERVAL]
751         str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
752         ldr     r1, [r0, #EMC_CFG]
753         bic     r1, r1, #(1 << 28)
754         bicne   r1, r1, #(1 << 29)
755         str     r1, [r0, #EMC_CFG]      @ disable DYN_SELF_REF
756
757         emc_timing_update r1, r0
758
759         ldr     r1, [r7]
760         add     r1, r1, #5
761         wait_until r1, r7, r2
762
763 emc_wait_auto_cal:
764         ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
765         tst     r1, #(1 << 31)          @ wait until AUTO_CAL_ACTIVE is cleared
766         bne     emc_wait_auto_cal
767
768         mov     r1, #3
769         str     r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
770
771 emcidle:
772         ldr     r1, [r0, #EMC_EMC_STATUS]
773         tst     r1, #4
774         beq     emcidle
775
776         mov     r1, #1
777         str     r1, [r0, #EMC_SELF_REF]
778
779         emc_device_mask r1, r0
780
781 emcself:
782         ldr     r2, [r0, #EMC_EMC_STATUS]
783         and     r2, r2, r1
784         cmp     r2, r1
785         bne     emcself                 @ loop until DDR in self-refresh
786
787         /* Put VTTGEN in the lowest power mode */
788         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL]
789         mov32   r2, 0xF8F8FFFF  @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
790         and     r1, r1, r2
791         str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
792         ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
793         cmp     r10, #TEGRA30
794         orreq   r1, r1, #7              @ set E_NO_VTTGEN
795         orrne   r1, r1, #0x3f
796         str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
797
798         emc_timing_update r1, r0
799
800         /* Tegra114 had dual EMC channel, now config the other one */
801         cmp     r10, #TEGRA114
802         bne     no_dual_emc_chanl
803         mov32   r1, TEGRA_EMC1_BASE
804         cmp     r0, r1
805         movne   r0, r1
806         bne     enter_self_refresh
807 no_dual_emc_chanl:
808
809         ldr     r1, [r4, #PMC_CTRL]
810         tst     r1, #PMC_CTRL_SIDE_EFFECT_LP0
811         bne     pmc_io_dpd_skip
812         /*
813          * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
814          * and COMP in the lowest power mode when LP1.
815          */
816         mov32   r1, 0x8EC00000
817         str     r1, [r4, #PMC_IO_DPD_REQ]
818 pmc_io_dpd_skip:
819
820         dsb
821
822         ret     lr
823
824         .ltorg
825 /* dummy symbol for end of IRAM */
826         .align L1_CACHE_SHIFT
827         .global tegra30_iram_end
828 tegra30_iram_end:
829         b       .
830 #endif