arch/arm/mach-tegra/include/mach/pinmux.h

   1 /*
   2  * linux/arch/arm/mach-tegra/include/mach/pinmux.h
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #ifndef __MACH_TEGRA_PINMUX_H
  18 #define __MACH_TEGRA_PINMUX_H
  19
  20 enum tegra_pingroup {
  21         TEGRA_PINGROUP_ATA = 0,
  22         TEGRA_PINGROUP_ATB,
  23         TEGRA_PINGROUP_ATC,
  24         TEGRA_PINGROUP_ATD,
  25         TEGRA_PINGROUP_ATE,
  26         TEGRA_PINGROUP_CDEV1,
  27         TEGRA_PINGROUP_CDEV2,
  28         TEGRA_PINGROUP_CRTP,
  29         TEGRA_PINGROUP_CSUS,
  30         TEGRA_PINGROUP_DAP1,
  31         TEGRA_PINGROUP_DAP2,
  32         TEGRA_PINGROUP_DAP3,
  33         TEGRA_PINGROUP_DAP4,
  34         TEGRA_PINGROUP_DDC,
  35         TEGRA_PINGROUP_DTA,
  36         TEGRA_PINGROUP_DTB,
  37         TEGRA_PINGROUP_DTC,
  38         TEGRA_PINGROUP_DTD,
  39         TEGRA_PINGROUP_DTE,
  40         TEGRA_PINGROUP_DTF,
  41         TEGRA_PINGROUP_GMA,
  42         TEGRA_PINGROUP_GMB,
  43         TEGRA_PINGROUP_GMC,
  44         TEGRA_PINGROUP_GMD,
  45         TEGRA_PINGROUP_GME,
  46         TEGRA_PINGROUP_GPU,
  47         TEGRA_PINGROUP_GPU7,
  48         TEGRA_PINGROUP_GPV,
  49         TEGRA_PINGROUP_HDINT,
  50         TEGRA_PINGROUP_I2CP,
  51         TEGRA_PINGROUP_IRRX,
  52         TEGRA_PINGROUP_IRTX,
  53         TEGRA_PINGROUP_KBCA,
  54         TEGRA_PINGROUP_KBCB,
  55         TEGRA_PINGROUP_KBCC,
  56         TEGRA_PINGROUP_KBCD,
  57         TEGRA_PINGROUP_KBCE,
  58         TEGRA_PINGROUP_KBCF,
  59         TEGRA_PINGROUP_LCSN,
  60         TEGRA_PINGROUP_LD0,
  61         TEGRA_PINGROUP_LD1,
  62         TEGRA_PINGROUP_LD10,
  63         TEGRA_PINGROUP_LD11,
  64         TEGRA_PINGROUP_LD12,
  65         TEGRA_PINGROUP_LD13,
  66         TEGRA_PINGROUP_LD14,
  67         TEGRA_PINGROUP_LD15,
  68         TEGRA_PINGROUP_LD16,
  69         TEGRA_PINGROUP_LD17,
  70         TEGRA_PINGROUP_LD2,
  71         TEGRA_PINGROUP_LD3,
  72         TEGRA_PINGROUP_LD4,
  73         TEGRA_PINGROUP_LD5,
  74         TEGRA_PINGROUP_LD6,
  75         TEGRA_PINGROUP_LD7,
  76         TEGRA_PINGROUP_LD8,
  77         TEGRA_PINGROUP_LD9,
  78         TEGRA_PINGROUP_LDC,
  79         TEGRA_PINGROUP_LDI,
  80         TEGRA_PINGROUP_LHP0,
  81         TEGRA_PINGROUP_LHP1,
  82         TEGRA_PINGROUP_LHP2,
  83         TEGRA_PINGROUP_LHS,
  84         TEGRA_PINGROUP_LM0,
  85         TEGRA_PINGROUP_LM1,
  86         TEGRA_PINGROUP_LPP,
  87         TEGRA_PINGROUP_LPW0,
  88         TEGRA_PINGROUP_LPW1,
  89         TEGRA_PINGROUP_LPW2,
  90         TEGRA_PINGROUP_LSC0,
  91         TEGRA_PINGROUP_LSC1,
  92         TEGRA_PINGROUP_LSCK,
  93         TEGRA_PINGROUP_LSDA,
  94         TEGRA_PINGROUP_LSDI,
  95         TEGRA_PINGROUP_LSPI,
  96         TEGRA_PINGROUP_LVP0,
  97         TEGRA_PINGROUP_LVP1,
  98         TEGRA_PINGROUP_LVS,
  99         TEGRA_PINGROUP_OWC,
 100         TEGRA_PINGROUP_PMC,
 101         TEGRA_PINGROUP_PTA,
 102         TEGRA_PINGROUP_RM,
 103         TEGRA_PINGROUP_SDB,
 104         TEGRA_PINGROUP_SDC,
 105         TEGRA_PINGROUP_SDD,
 106         TEGRA_PINGROUP_SDIO1,
 107         TEGRA_PINGROUP_SLXA,
 108         TEGRA_PINGROUP_SLXC,
 109         TEGRA_PINGROUP_SLXD,
 110         TEGRA_PINGROUP_SLXK,
 111         TEGRA_PINGROUP_SPDI,
 112         TEGRA_PINGROUP_SPDO,
 113         TEGRA_PINGROUP_SPIA,
 114         TEGRA_PINGROUP_SPIB,
 115         TEGRA_PINGROUP_SPIC,
 116         TEGRA_PINGROUP_SPID,
 117         TEGRA_PINGROUP_SPIE,
 118         TEGRA_PINGROUP_SPIF,
 119         TEGRA_PINGROUP_SPIG,
 120         TEGRA_PINGROUP_SPIH,
 121         TEGRA_PINGROUP_UAA,
 122         TEGRA_PINGROUP_UAB,
 123         TEGRA_PINGROUP_UAC,
 124         TEGRA_PINGROUP_UAD,
 125         TEGRA_PINGROUP_UCA,
 126         TEGRA_PINGROUP_UCB,
 127         TEGRA_PINGROUP_UDA,
 128         /* these pin groups only have pullup and pull down control */
 129         TEGRA_PINGROUP_CK32,
 130         TEGRA_PINGROUP_DDRC,
 131         TEGRA_PINGROUP_PMCA,
 132         TEGRA_PINGROUP_PMCB,
 133         TEGRA_PINGROUP_PMCC,
 134         TEGRA_PINGROUP_PMCD,
 135         TEGRA_PINGROUP_PMCE,
 136         TEGRA_PINGROUP_XM2C,
 137         TEGRA_PINGROUP_XM2D,
 138         TEGRA_MAX_PINGROUP,
 139 };
 140
 141 enum tegra_mux_func {
 142         TEGRA_MUX_RSVD = 0x8000,
 143         TEGRA_MUX_RSVD1 = 0x8000,
 144         TEGRA_MUX_RSVD2 = 0x8001,
 145         TEGRA_MUX_RSVD3 = 0x8002,
 146         TEGRA_MUX_RSVD4 = 0x8003,
 147         TEGRA_MUX_NONE = -1,
 148         TEGRA_MUX_AHB_CLK,
 149         TEGRA_MUX_APB_CLK,
 150         TEGRA_MUX_AUDIO_SYNC,
 151         TEGRA_MUX_CRT,
 152         TEGRA_MUX_DAP1,
 153         TEGRA_MUX_DAP2,
 154         TEGRA_MUX_DAP3,
 155         TEGRA_MUX_DAP4,
 156         TEGRA_MUX_DAP5,
 157         TEGRA_MUX_DISPLAYA,
 158         TEGRA_MUX_DISPLAYB,
 159         TEGRA_MUX_EMC_TEST0_DLL,
 160         TEGRA_MUX_EMC_TEST1_DLL,
 161         TEGRA_MUX_GMI,
 162         TEGRA_MUX_GMI_INT,
 163         TEGRA_MUX_HDMI,
 164         TEGRA_MUX_I2C,
 165         TEGRA_MUX_I2C2,
 166         TEGRA_MUX_I2C3,
 167         TEGRA_MUX_IDE,
 168         TEGRA_MUX_IRDA,
 169         TEGRA_MUX_KBC,
 170         TEGRA_MUX_MIO,
 171         TEGRA_MUX_MIPI_HS,
 172         TEGRA_MUX_NAND,
 173         TEGRA_MUX_OSC,
 174         TEGRA_MUX_OWR,
 175         TEGRA_MUX_PCIE,
 176         TEGRA_MUX_PLLA_OUT,
 177         TEGRA_MUX_PLLC_OUT1,
 178         TEGRA_MUX_PLLM_OUT1,
 179         TEGRA_MUX_PLLP_OUT2,
 180         TEGRA_MUX_PLLP_OUT3,
 181         TEGRA_MUX_PLLP_OUT4,
 182         TEGRA_MUX_PWM,
 183         TEGRA_MUX_PWR_INTR,
 184         TEGRA_MUX_PWR_ON,
 185         TEGRA_MUX_RTCK,
 186         TEGRA_MUX_SDIO1,
 187         TEGRA_MUX_SDIO2,
 188         TEGRA_MUX_SDIO3,
 189         TEGRA_MUX_SDIO4,
 190         TEGRA_MUX_SFLASH,
 191         TEGRA_MUX_SPDIF,
 192         TEGRA_MUX_SPI1,
 193         TEGRA_MUX_SPI2,
 194         TEGRA_MUX_SPI2_ALT,
 195         TEGRA_MUX_SPI3,
 196         TEGRA_MUX_SPI4,
 197         TEGRA_MUX_TRACE,
 198         TEGRA_MUX_TWC,
 199         TEGRA_MUX_UARTA,
 200         TEGRA_MUX_UARTB,
 201         TEGRA_MUX_UARTC,
 202         TEGRA_MUX_UARTD,
 203         TEGRA_MUX_UARTE,
 204         TEGRA_MUX_ULPI,
 205         TEGRA_MUX_VI,
 206         TEGRA_MUX_VI_SENSOR_CLK,
 207         TEGRA_MUX_XIO,
 208         TEGRA_MAX_MUX,
 209 };
 210
 211 enum tegra_pullupdown {
 212         TEGRA_PUPD_NORMAL = 0,
 213         TEGRA_PUPD_PULL_DOWN,
 214         TEGRA_PUPD_PULL_UP,
 215 };
 216
 217 enum tegra_tristate {
 218         TEGRA_TRI_NORMAL = 0,
 219         TEGRA_TRI_TRISTATE = 1,
 220 };
 221
 222 struct tegra_pingroup_config {
 223         enum tegra_pingroup     pingroup;
 224         enum tegra_mux_func     func;
 225         enum tegra_pullupdown   pupd;
 226         enum tegra_tristate     tristate;
 227 };
 228
 229 enum tegra_slew {
 230         TEGRA_SLEW_FASTEST = 0,
 231         TEGRA_SLEW_FAST,
 232         TEGRA_SLEW_SLOW,
 233         TEGRA_SLEW_SLOWEST,
 234         TEGRA_MAX_SLEW,
 235 };
 236
 237 enum tegra_pull_strength {
 238         TEGRA_PULL_0 = 0,
 239         TEGRA_PULL_1,
 240         TEGRA_PULL_2,
 241         TEGRA_PULL_3,
 242         TEGRA_PULL_4,
 243         TEGRA_PULL_5,
 244         TEGRA_PULL_6,
 245         TEGRA_PULL_7,
 246         TEGRA_PULL_8,
 247         TEGRA_PULL_9,
 248         TEGRA_PULL_10,
 249         TEGRA_PULL_11,
 250         TEGRA_PULL_12,
 251         TEGRA_PULL_13,
 252         TEGRA_PULL_14,
 253         TEGRA_PULL_15,
 254         TEGRA_PULL_16,
 255         TEGRA_PULL_17,
 256         TEGRA_PULL_18,
 257         TEGRA_PULL_19,
 258         TEGRA_PULL_20,
 259         TEGRA_PULL_21,
 260         TEGRA_PULL_22,
 261         TEGRA_PULL_23,
 262         TEGRA_PULL_24,
 263         TEGRA_PULL_25,
 264         TEGRA_PULL_26,
 265         TEGRA_PULL_27,
 266         TEGRA_PULL_28,
 267         TEGRA_PULL_29,
 268         TEGRA_PULL_30,
 269         TEGRA_PULL_31,
 270         TEGRA_MAX_PULL,
 271 };
 272
 273 enum tegra_drive_pingroup {
 274         TEGRA_DRIVE_PINGROUP_AO1 = 0,
 275         TEGRA_DRIVE_PINGROUP_AO2,
 276         TEGRA_DRIVE_PINGROUP_AT1,
 277         TEGRA_DRIVE_PINGROUP_AT2,
 278         TEGRA_DRIVE_PINGROUP_CDEV1,
 279         TEGRA_DRIVE_PINGROUP_CDEV2,
 280         TEGRA_DRIVE_PINGROUP_CSUS,
 281         TEGRA_DRIVE_PINGROUP_DAP1,
 282         TEGRA_DRIVE_PINGROUP_DAP2,
 283         TEGRA_DRIVE_PINGROUP_DAP3,
 284         TEGRA_DRIVE_PINGROUP_DAP4,
 285         TEGRA_DRIVE_PINGROUP_DBG,
 286         TEGRA_DRIVE_PINGROUP_LCD1,
 287         TEGRA_DRIVE_PINGROUP_LCD2,
 288         TEGRA_DRIVE_PINGROUP_SDMMC2,
 289         TEGRA_DRIVE_PINGROUP_SDMMC3,
 290         TEGRA_DRIVE_PINGROUP_SPI,
 291         TEGRA_DRIVE_PINGROUP_UAA,
 292         TEGRA_DRIVE_PINGROUP_UAB,
 293         TEGRA_DRIVE_PINGROUP_UART2,
 294         TEGRA_DRIVE_PINGROUP_UART3,
 295         TEGRA_DRIVE_PINGROUP_VI1,
 296         TEGRA_DRIVE_PINGROUP_VI2,
 297         TEGRA_DRIVE_PINGROUP_XM2A,
 298         TEGRA_DRIVE_PINGROUP_XM2C,
 299         TEGRA_DRIVE_PINGROUP_XM2D,
 300         TEGRA_DRIVE_PINGROUP_XM2CLK,
 301         TEGRA_DRIVE_PINGROUP_MEMCOMP,
 302         TEGRA_MAX_DRIVE_PINGROUP,
 303 };
 304
 305 enum tegra_drive {
 306         TEGRA_DRIVE_DIV_8 = 0,
 307         TEGRA_DRIVE_DIV_4,
 308         TEGRA_DRIVE_DIV_2,
 309         TEGRA_DRIVE_DIV_1,
 310         TEGRA_MAX_DRIVE,
 311 };
 312
 313 enum tegra_hsm {
 314         TEGRA_HSM_DISABLE = 0,
 315         TEGRA_HSM_ENABLE,
 316 };
 317
 318 enum tegra_schmitt {
 319         TEGRA_SCHMITT_DISABLE = 0,
 320         TEGRA_SCHMITT_ENABLE,
 321 };
 322
 323 struct tegra_drive_pingroup_config {
 324         enum tegra_drive_pingroup pingroup;
 325         enum tegra_hsm hsm;
 326         enum tegra_schmitt schmitt;
 327         enum tegra_drive drive;
 328         enum tegra_pull_strength pull_down;
 329         enum tegra_pull_strength pull_up;
 330         enum tegra_slew slew_rising;
 331         enum tegra_slew slew_falling;
 332 };
 333
 334 int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func);
 335 int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate);
 336 int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd);
 337
 338 void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
 339         enum tegra_mux_func func, enum tegra_pullupdown pupd,
 340         enum tegra_tristate tristate);
 341
 342 void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len);
 343
 344 void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
 345         int len);
 346
 347 #endif
 348