arch/arm/mach-spear3xx/spear3xx.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear3xx.c
   3  *
   4  * SPEAr3XX machines common source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr3xx: " fmt
  15
  16 #include <linux/amba/pl022.h>
  17 #include <linux/amba/pl08x.h>
  18 #include <linux/irqchip/spear-shirq.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/io.h>
  21 #include <asm/hardware/pl080.h>
  22 #include <asm/hardware/vic.h>
  23 #include <plat/pl080.h>
  24 #include <mach/generic.h>
  25 #include <mach/spear.h>
  26
  27 /* ssp device registration */
  28 struct pl022_ssp_controller pl022_plat_data = {
  29         .bus_id = 0,
  30         .enable_dma = 1,
  31         .dma_filter = pl08x_filter_id,
  32         .dma_tx_param = "ssp0_tx",
  33         .dma_rx_param = "ssp0_rx",
  34         /*
  35          * This is number of spi devices that can be connected to spi. There are
  36          * two type of chipselects on which slave devices can work. One is chip
  37          * select provided by spi masters other is controlled through external
  38          * gpio's. We can't use chipselect provided from spi master (because as
  39          * soon as FIFO becomes empty, CS is disabled and transfer ends). So
  40          * this number now depends on number of gpios available for spi. each
  41          * slave on each master requires a separate gpio pin.
  42          */
  43         .num_chipselect = 2,
  44 };
  45
  46 /* dmac device registration */
  47 struct pl08x_platform_data pl080_plat_data = {
  48         .memcpy_channel = {
  49                 .bus_id = "memcpy",
  50                 .cctl_memcpy =
  51                         (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
  52                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
  53                         PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
  54                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
  55                         PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
  56                         PL080_CONTROL_PROT_SYS),
  57         },
  58         .lli_buses = PL08X_AHB1,
  59         .mem_buses = PL08X_AHB1,
  60         .get_signal = pl080_get_signal,
  61         .put_signal = pl080_put_signal,
  62 };
  63
  64 /*
  65  * Following will create 16MB static virtual/physical mappings
  66  * PHYSICAL             VIRTUAL
  67  * 0xD0000000           0xFD000000
  68  * 0xFC000000           0xFC000000
  69  */
  70 struct map_desc spear3xx_io_desc[] __initdata = {
  71         {
  72                 .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
  73                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
  74                 .length         = SZ_16M,
  75                 .type           = MT_DEVICE
  76         }, {
  77                 .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
  78                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
  79                 .length         = SZ_16M,
  80                 .type           = MT_DEVICE
  81         },
  82 };
  83
  84 /* This will create static memory mapping for selected devices */
  85 void __init spear3xx_map_io(void)
  86 {
  87         iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
  88 }
  89
  90 void __init spear3xx_timer_init(void)
  91 {
  92         char pclk_name[] = "pll3_clk";
  93         struct clk *gpt_clk, *pclk;
  94
  95         spear3xx_clk_init();
  96
  97         /* get the system timer clock */
  98         gpt_clk = clk_get_sys("gpt0", NULL);
  99         if (IS_ERR(gpt_clk)) {
 100                 pr_err("%s:couldn't get clk for gpt\n", __func__);
 101                 BUG();
 102         }
 103
 104         /* get the suitable parent clock for timer*/
 105         pclk = clk_get(NULL, pclk_name);
 106         if (IS_ERR(pclk)) {
 107                 pr_err("%s:couldn't get %s as parent for gpt\n",
 108                                 __func__, pclk_name);
 109                 BUG();
 110         }
 111
 112         clk_set_parent(gpt_clk, pclk);
 113         clk_put(gpt_clk);
 114         clk_put(pclk);
 115
 116         spear_setup_of_timer();
 117 }
 118
 119 static const struct of_device_id vic_of_match[] __initconst = {
 120         { .compatible = "arm,pl190-vic", .data = vic_of_init, },
 121         { .compatible = "st,spear300-shirq", .data = spear300_shirq_of_init, },
 122         { .compatible = "st,spear310-shirq", .data = spear310_shirq_of_init, },
 123         { .compatible = "st,spear320-shirq", .data = spear320_shirq_of_init, },
 124         { /* Sentinel */ }
 125 };
 126
 127 void __init spear3xx_dt_init_irq(void)
 128 {
 129         of_irq_init(vic_of_match);
 130 }