arch/arm/mach-spear3xx/spear310.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear310.c
   3  *
   4  * SPEAr310 machine source file
   5  *
   6  * Copyright (C) 2009-2012 ST Microelectronics
   7  * Viresh Kumar <viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) "SPEAr310: " fmt
  15
  16 #include <linux/amba/pl08x.h>
  17 #include <linux/amba/serial.h>
  18 #include <linux/of_platform.h>
  19 #include <asm/hardware/vic.h>
  20 #include <asm/mach/arch.h>
  21 #include <plat/shirq.h>
  22 #include <mach/generic.h>
  23 #include <mach/spear.h>
  24
  25 #define SPEAR310_UART1_BASE             UL(0xB2000000)
  26 #define SPEAR310_UART2_BASE             UL(0xB2080000)
  27 #define SPEAR310_UART3_BASE             UL(0xB2100000)
  28 #define SPEAR310_UART4_BASE             UL(0xB2180000)
  29 #define SPEAR310_UART5_BASE             UL(0xB2200000)
  30 #define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
  31
  32 /* Interrupt registers offsets and masks */
  33 #define SPEAR310_INT_STS_MASK_REG       0x04
  34 #define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
  35 #define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
  36 #define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
  37 #define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
  38 #define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
  39 #define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
  40 #define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
  41 #define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
  42 #define SPEAR310_UART1_IRQ_MASK         (1 << 8)
  43 #define SPEAR310_UART2_IRQ_MASK         (1 << 9)
  44 #define SPEAR310_UART3_IRQ_MASK         (1 << 10)
  45 #define SPEAR310_UART4_IRQ_MASK         (1 << 11)
  46 #define SPEAR310_UART5_IRQ_MASK         (1 << 12)
  47 #define SPEAR310_EMI_IRQ_MASK           (1 << 13)
  48 #define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
  49 #define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
  50 #define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
  51
  52 #define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
  53 #define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
  54 #define SPEAR310_SHIRQ_RAS3_MASK        0x02000
  55 #define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
  56
  57 /* SPEAr310 Virtual irq definitions */
  58 /* IRQs sharing IRQ_GEN_RAS_1 */
  59 #define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
  60 #define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
  61 #define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
  62 #define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
  63 #define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
  64 #define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
  65 #define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
  66 #define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
  67
  68 /* IRQs sharing IRQ_GEN_RAS_2 */
  69 #define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
  70 #define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
  71 #define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
  72 #define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
  73 #define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
  74
  75 /* IRQs sharing IRQ_GEN_RAS_3 */
  76 #define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
  77 #define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
  78
  79 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
  80 #define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
  81 #define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
  82 #define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
  83
  84
  85 /* spear3xx shared irq */
  86 static struct shirq_dev_config shirq_ras1_config[] = {
  87         {
  88                 .virq = SPEAR310_VIRQ_SMII0,
  89                 .status_mask = SPEAR310_SMII0_IRQ_MASK,
  90         }, {
  91                 .virq = SPEAR310_VIRQ_SMII1,
  92                 .status_mask = SPEAR310_SMII1_IRQ_MASK,
  93         }, {
  94                 .virq = SPEAR310_VIRQ_SMII2,
  95                 .status_mask = SPEAR310_SMII2_IRQ_MASK,
  96         }, {
  97                 .virq = SPEAR310_VIRQ_SMII3,
  98                 .status_mask = SPEAR310_SMII3_IRQ_MASK,
  99         }, {
 100                 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
 101                 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
 102         }, {
 103                 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
 104                 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
 105         }, {
 106                 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
 107                 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
 108         }, {
 109                 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
 110                 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
 111         },
 112 };
 113
 114 static struct spear_shirq shirq_ras1 = {
 115         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
 116         .dev_config = shirq_ras1_config,
 117         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 118         .regs = {
 119                 .enb_reg = -1,
 120                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 121                 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
 122                 .clear_reg = -1,
 123         },
 124 };
 125
 126 static struct shirq_dev_config shirq_ras2_config[] = {
 127         {
 128                 .virq = SPEAR310_VIRQ_UART1,
 129                 .status_mask = SPEAR310_UART1_IRQ_MASK,
 130         }, {
 131                 .virq = SPEAR310_VIRQ_UART2,
 132                 .status_mask = SPEAR310_UART2_IRQ_MASK,
 133         }, {
 134                 .virq = SPEAR310_VIRQ_UART3,
 135                 .status_mask = SPEAR310_UART3_IRQ_MASK,
 136         }, {
 137                 .virq = SPEAR310_VIRQ_UART4,
 138                 .status_mask = SPEAR310_UART4_IRQ_MASK,
 139         }, {
 140                 .virq = SPEAR310_VIRQ_UART5,
 141                 .status_mask = SPEAR310_UART5_IRQ_MASK,
 142         },
 143 };
 144
 145 static struct spear_shirq shirq_ras2 = {
 146         .irq = SPEAR3XX_IRQ_GEN_RAS_2,
 147         .dev_config = shirq_ras2_config,
 148         .dev_count = ARRAY_SIZE(shirq_ras2_config),
 149         .regs = {
 150                 .enb_reg = -1,
 151                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 152                 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
 153                 .clear_reg = -1,
 154         },
 155 };
 156
 157 static struct shirq_dev_config shirq_ras3_config[] = {
 158         {
 159                 .virq = SPEAR310_VIRQ_EMI,
 160                 .status_mask = SPEAR310_EMI_IRQ_MASK,
 161         },
 162 };
 163
 164 static struct spear_shirq shirq_ras3 = {
 165         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
 166         .dev_config = shirq_ras3_config,
 167         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 168         .regs = {
 169                 .enb_reg = -1,
 170                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 171                 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
 172                 .clear_reg = -1,
 173         },
 174 };
 175
 176 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 177         {
 178                 .virq = SPEAR310_VIRQ_TDM_HDLC,
 179                 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
 180         }, {
 181                 .virq = SPEAR310_VIRQ_RS485_0,
 182                 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
 183         }, {
 184                 .virq = SPEAR310_VIRQ_RS485_1,
 185                 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
 186         },
 187 };
 188
 189 static struct spear_shirq shirq_intrcomm_ras = {
 190         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 191         .dev_config = shirq_intrcomm_ras_config,
 192         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 193         .regs = {
 194                 .enb_reg = -1,
 195                 .status_reg = SPEAR310_INT_STS_MASK_REG,
 196                 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
 197                 .clear_reg = -1,
 198         },
 199 };
 200
 201 /* DMAC platform data's slave info */
 202 struct pl08x_channel_data spear310_dma_info[] = {
 203         {
 204                 .bus_id = "uart0_rx",
 205                 .min_signal = 2,
 206                 .max_signal = 2,
 207                 .muxval = 0,
 208                 .cctl = 0,
 209                 .periph_buses = PL08X_AHB1,
 210         }, {
 211                 .bus_id = "uart0_tx",
 212                 .min_signal = 3,
 213                 .max_signal = 3,
 214                 .muxval = 0,
 215                 .cctl = 0,
 216                 .periph_buses = PL08X_AHB1,
 217         }, {
 218                 .bus_id = "ssp0_rx",
 219                 .min_signal = 8,
 220                 .max_signal = 8,
 221                 .muxval = 0,
 222                 .cctl = 0,
 223                 .periph_buses = PL08X_AHB1,
 224         }, {
 225                 .bus_id = "ssp0_tx",
 226                 .min_signal = 9,
 227                 .max_signal = 9,
 228                 .muxval = 0,
 229                 .cctl = 0,
 230                 .periph_buses = PL08X_AHB1,
 231         }, {
 232                 .bus_id = "i2c_rx",
 233                 .min_signal = 10,
 234                 .max_signal = 10,
 235                 .muxval = 0,
 236                 .cctl = 0,
 237                 .periph_buses = PL08X_AHB1,
 238         }, {
 239                 .bus_id = "i2c_tx",
 240                 .min_signal = 11,
 241                 .max_signal = 11,
 242                 .muxval = 0,
 243                 .cctl = 0,
 244                 .periph_buses = PL08X_AHB1,
 245         }, {
 246                 .bus_id = "irda",
 247                 .min_signal = 12,
 248                 .max_signal = 12,
 249                 .muxval = 0,
 250                 .cctl = 0,
 251                 .periph_buses = PL08X_AHB1,
 252         }, {
 253                 .bus_id = "adc",
 254                 .min_signal = 13,
 255                 .max_signal = 13,
 256                 .muxval = 0,
 257                 .cctl = 0,
 258                 .periph_buses = PL08X_AHB1,
 259         }, {
 260                 .bus_id = "to_jpeg",
 261                 .min_signal = 14,
 262                 .max_signal = 14,
 263                 .muxval = 0,
 264                 .cctl = 0,
 265                 .periph_buses = PL08X_AHB1,
 266         }, {
 267                 .bus_id = "from_jpeg",
 268                 .min_signal = 15,
 269                 .max_signal = 15,
 270                 .muxval = 0,
 271                 .cctl = 0,
 272                 .periph_buses = PL08X_AHB1,
 273         }, {
 274                 .bus_id = "uart1_rx",
 275                 .min_signal = 0,
 276                 .max_signal = 0,
 277                 .muxval = 1,
 278                 .cctl = 0,
 279                 .periph_buses = PL08X_AHB1,
 280         }, {
 281                 .bus_id = "uart1_tx",
 282                 .min_signal = 1,
 283                 .max_signal = 1,
 284                 .muxval = 1,
 285                 .cctl = 0,
 286                 .periph_buses = PL08X_AHB1,
 287         }, {
 288                 .bus_id = "uart2_rx",
 289                 .min_signal = 2,
 290                 .max_signal = 2,
 291                 .muxval = 1,
 292                 .cctl = 0,
 293                 .periph_buses = PL08X_AHB1,
 294         }, {
 295                 .bus_id = "uart2_tx",
 296                 .min_signal = 3,
 297                 .max_signal = 3,
 298                 .muxval = 1,
 299                 .cctl = 0,
 300                 .periph_buses = PL08X_AHB1,
 301         }, {
 302                 .bus_id = "uart3_rx",
 303                 .min_signal = 4,
 304                 .max_signal = 4,
 305                 .muxval = 1,
 306                 .cctl = 0,
 307                 .periph_buses = PL08X_AHB1,
 308         }, {
 309                 .bus_id = "uart3_tx",
 310                 .min_signal = 5,
 311                 .max_signal = 5,
 312                 .muxval = 1,
 313                 .cctl = 0,
 314                 .periph_buses = PL08X_AHB1,
 315         }, {
 316                 .bus_id = "uart4_rx",
 317                 .min_signal = 6,
 318                 .max_signal = 6,
 319                 .muxval = 1,
 320                 .cctl = 0,
 321                 .periph_buses = PL08X_AHB1,
 322         }, {
 323                 .bus_id = "uart4_tx",
 324                 .min_signal = 7,
 325                 .max_signal = 7,
 326                 .muxval = 1,
 327                 .cctl = 0,
 328                 .periph_buses = PL08X_AHB1,
 329         }, {
 330                 .bus_id = "uart5_rx",
 331                 .min_signal = 8,
 332                 .max_signal = 8,
 333                 .muxval = 1,
 334                 .cctl = 0,
 335                 .periph_buses = PL08X_AHB1,
 336         }, {
 337                 .bus_id = "uart5_tx",
 338                 .min_signal = 9,
 339                 .max_signal = 9,
 340                 .muxval = 1,
 341                 .cctl = 0,
 342                 .periph_buses = PL08X_AHB1,
 343         }, {
 344                 .bus_id = "ras5_rx",
 345                 .min_signal = 10,
 346                 .max_signal = 10,
 347                 .muxval = 1,
 348                 .cctl = 0,
 349                 .periph_buses = PL08X_AHB1,
 350         }, {
 351                 .bus_id = "ras5_tx",
 352                 .min_signal = 11,
 353                 .max_signal = 11,
 354                 .muxval = 1,
 355                 .cctl = 0,
 356                 .periph_buses = PL08X_AHB1,
 357         }, {
 358                 .bus_id = "ras6_rx",
 359                 .min_signal = 12,
 360                 .max_signal = 12,
 361                 .muxval = 1,
 362                 .cctl = 0,
 363                 .periph_buses = PL08X_AHB1,
 364         }, {
 365                 .bus_id = "ras6_tx",
 366                 .min_signal = 13,
 367                 .max_signal = 13,
 368                 .muxval = 1,
 369                 .cctl = 0,
 370                 .periph_buses = PL08X_AHB1,
 371         }, {
 372                 .bus_id = "ras7_rx",
 373                 .min_signal = 14,
 374                 .max_signal = 14,
 375                 .muxval = 1,
 376                 .cctl = 0,
 377                 .periph_buses = PL08X_AHB1,
 378         }, {
 379                 .bus_id = "ras7_tx",
 380                 .min_signal = 15,
 381                 .max_signal = 15,
 382                 .muxval = 1,
 383                 .cctl = 0,
 384                 .periph_buses = PL08X_AHB1,
 385         },
 386 };
 387
 388 /* uart devices plat data */
 389 static struct amba_pl011_data spear310_uart_data[] = {
 390         {
 391                 .dma_filter = pl08x_filter_id,
 392                 .dma_tx_param = "uart1_tx",
 393                 .dma_rx_param = "uart1_rx",
 394         }, {
 395                 .dma_filter = pl08x_filter_id,
 396                 .dma_tx_param = "uart2_tx",
 397                 .dma_rx_param = "uart2_rx",
 398         }, {
 399                 .dma_filter = pl08x_filter_id,
 400                 .dma_tx_param = "uart3_tx",
 401                 .dma_rx_param = "uart3_rx",
 402         }, {
 403                 .dma_filter = pl08x_filter_id,
 404                 .dma_tx_param = "uart4_tx",
 405                 .dma_rx_param = "uart4_rx",
 406         }, {
 407                 .dma_filter = pl08x_filter_id,
 408                 .dma_tx_param = "uart5_tx",
 409                 .dma_rx_param = "uart5_rx",
 410         },
 411 };
 412
 413 /* Add SPEAr310 auxdata to pass platform data */
 414 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
 415         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
 416                         &pl022_plat_data),
 417         OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
 418                         &pl080_plat_data),
 419         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
 420                         &spear310_uart_data[0]),
 421         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
 422                         &spear310_uart_data[1]),
 423         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
 424                         &spear310_uart_data[2]),
 425         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
 426                         &spear310_uart_data[3]),
 427         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
 428                         &spear310_uart_data[4]),
 429         {}
 430 };
 431
 432 static void __init spear310_dt_init(void)
 433 {
 434         void __iomem *base;
 435         int ret;
 436
 437         pl080_plat_data.slave_channels = spear310_dma_info;
 438         pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
 439
 440         of_platform_populate(NULL, of_default_bus_match_table,
 441                         spear310_auxdata_lookup, NULL);
 442
 443         /* shared irq registration */
 444         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
 445         if (base) {
 446                 /* shirq 1 */
 447                 shirq_ras1.regs.base = base;
 448                 ret = spear_shirq_register(&shirq_ras1);
 449                 if (ret)
 450                         pr_err("Error registering Shared IRQ 1\n");
 451
 452                 /* shirq 2 */
 453                 shirq_ras2.regs.base = base;
 454                 ret = spear_shirq_register(&shirq_ras2);
 455                 if (ret)
 456                         pr_err("Error registering Shared IRQ 2\n");
 457
 458                 /* shirq 3 */
 459                 shirq_ras3.regs.base = base;
 460                 ret = spear_shirq_register(&shirq_ras3);
 461                 if (ret)
 462                         pr_err("Error registering Shared IRQ 3\n");
 463
 464                 /* shirq 4 */
 465                 shirq_intrcomm_ras.regs.base = base;
 466                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 467                 if (ret)
 468                         pr_err("Error registering Shared IRQ 4\n");
 469         }
 470 }
 471
 472 static const char * const spear310_dt_board_compat[] = {
 473         "st,spear310",
 474         "st,spear310-evb",
 475         NULL,
 476 };
 477
 478 static void __init spear310_map_io(void)
 479 {
 480         spear3xx_map_io();
 481 }
 482
 483 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
 484         .map_io         =       spear310_map_io,
 485         .init_irq       =       spear3xx_dt_init_irq,
 486         .handle_irq     =       vic_handle_irq,
 487         .timer          =       &spear3xx_timer,
 488         .init_machine   =       spear310_dt_init,
 489         .restart        =       spear_restart,
 490         .dt_compat      =       spear310_dt_board_compat,
 491 MACHINE_END