arch/arm/mach-spear3xx/include/mach/spear320.h

   1 /*
   2  * arch/arm/mach-spear3xx/include/mach/spear320.h
   3  *
   4  * SPEAr320 Machine specific definition
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #ifdef  CONFIG_MACH_SPEAR320
  15
  16 #ifndef __MACH_SPEAR320_H
  17 #define __MACH_SPEAR320_H
  18
  19 #define SPEAR320_EMI_CTRL_BASE          0x40000000
  20 #define SPEAR320_EMI_CTRL_SIZE          0x08000000
  21
  22 #define SPEAR320_FSMC_BASE              0x4C000000
  23 #define SPEAR320_FSMC_SIZE              0x01000000
  24
  25 #define SPEAR320_I2S_BASE               0x60000000
  26 #define SPEAR320_I2S_SIZE               0x10000000
  27
  28 #define SPEAR320_SDIO_BASE              0x70000000
  29 #define SPEAR320_SDIO_SIZE              0x10000000
  30
  31 #define SPEAR320_CLCD_BASE              0x90000000
  32 #define SPEAR320_CLCD_SIZE              0x10000000
  33
  34 #define SPEAR320_PAR_PORT_BASE          0xA0000000
  35 #define SPEAR320_PAR_PORT_SIZE          0x01000000
  36
  37 #define SPEAR320_CAN0_BASE              0xA1000000
  38 #define SPEAR320_CAN0_SIZE              0x01000000
  39
  40 #define SPEAR320_CAN1_BASE              0xA2000000
  41 #define SPEAR320_CAN1_SIZE              0x01000000
  42
  43 #define SPEAR320_UART1_BASE             0xA3000000
  44 #define SPEAR320_UART2_BASE             0xA4000000
  45 #define SPEAR320_UART_SIZE              0x01000000
  46
  47 #define SPEAR320_SSP0_BASE              0xA5000000
  48 #define SPEAR320_SSP0_SIZE              0x01000000
  49
  50 #define SPEAR320_SSP1_BASE              0xA6000000
  51 #define SPEAR320_SSP1_SIZE              0x01000000
  52
  53 #define SPEAR320_I2C_BASE               0xA7000000
  54 #define SPEAR320_I2C_SIZE               0x01000000
  55
  56 #define SPEAR320_PWM_BASE               0xA8000000
  57 #define SPEAR320_PWM_SIZE               0x01000000
  58
  59 #define SPEAR320_SMII0_BASE             0xAA000000
  60 #define SPEAR320_SMII0_SIZE             0x01000000
  61
  62 #define SPEAR320_SMII1_BASE             0xAB000000
  63 #define SPEAR320_SMII1_SIZE             0x01000000
  64
  65 #define SPEAR320_SOC_CONFIG_BASE        0xB4000000
  66 #define SPEAR320_SOC_CONFIG_SIZE        0x00000070
  67 /* Interrupt registers offsets and masks */
  68 #define INT_STS_MASK_REG                0x04
  69 #define INT_CLR_MASK_REG                0x04
  70 #define INT_ENB_MASK_REG                0x08
  71 #define GPIO_IRQ_MASK                   (1 << 0)
  72 #define I2S_PLAY_IRQ_MASK               (1 << 1)
  73 #define I2S_REC_IRQ_MASK                (1 << 2)
  74 #define EMI_IRQ_MASK                    (1 << 7)
  75 #define CLCD_IRQ_MASK                   (1 << 8)
  76 #define SPP_IRQ_MASK                    (1 << 9)
  77 #define SDIO_IRQ_MASK                   (1 << 10)
  78 #define CAN_U_IRQ_MASK                  (1 << 11)
  79 #define CAN_L_IRQ_MASK                  (1 << 12)
  80 #define UART1_IRQ_MASK                  (1 << 13)
  81 #define UART2_IRQ_MASK                  (1 << 14)
  82 #define SSP1_IRQ_MASK                   (1 << 15)
  83 #define SSP2_IRQ_MASK                   (1 << 16)
  84 #define SMII0_IRQ_MASK                  (1 << 17)
  85 #define MII1_SMII1_IRQ_MASK             (1 << 18)
  86 #define WAKEUP_SMII0_IRQ_MASK           (1 << 19)
  87 #define WAKEUP_MII1_SMII1_IRQ_MASK      (1 << 20)
  88 #define I2C1_IRQ_MASK                   (1 << 21)
  89
  90 #define SHIRQ_RAS1_MASK                 0x000380
  91 #define SHIRQ_RAS3_MASK                 0x000007
  92 #define SHIRQ_INTRCOMM_RAS_MASK         0x3FF800
  93
  94 #endif /* __MACH_SPEAR320_H */
  95
  96 #endif /* CONFIG_MACH_SPEAR320 */