arch/arm/mach-socfpga/socfpga.c

   1 /*
   2  *  Copyright (C) 2012-2015 Altera Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <linux/irqchip.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/reboot.h>
  22 #include <linux/reset/socfpga.h>
  23
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/cacheflush.h>
  28
  29 #include "core.h"
  30
  31 void __iomem *sys_manager_base_addr;
  32 void __iomem *rst_manager_base_addr;
  33 void __iomem *sdr_ctl_base_addr;
  34 unsigned long socfpga_cpu1start_addr;
  35
  36 static void __init socfpga_sysmgr_init(void)
  37 {
  38         struct device_node *np;
  39
  40         np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
  41
  42         if (of_property_read_u32(np, "cpu1-start-addr",
  43                         (u32 *) &socfpga_cpu1start_addr))
  44                 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
  45
  46         /* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
  47         smp_wmb();
  48         sync_cache_w(&socfpga_cpu1start_addr);
  49
  50         sys_manager_base_addr = of_iomap(np, 0);
  51
  52         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
  53         rst_manager_base_addr = of_iomap(np, 0);
  54
  55         np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
  56         sdr_ctl_base_addr = of_iomap(np, 0);
  57 }
  58
  59 static void __init socfpga_init_irq(void)
  60 {
  61         irqchip_init();
  62         socfpga_sysmgr_init();
  63         if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
  64                 socfpga_init_l2_ecc();
  65
  66         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
  67                 socfpga_init_ocram_ecc();
  68         socfpga_reset_init();
  69 }
  70
  71 static void __init socfpga_arria10_init_irq(void)
  72 {
  73         irqchip_init();
  74         socfpga_sysmgr_init();
  75         if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
  76                 socfpga_init_arria10_l2_ecc();
  77         if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
  78                 socfpga_init_arria10_ocram_ecc();
  79         socfpga_reset_init();
  80 }
  81
  82 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
  83 {
  84         u32 temp;
  85
  86         temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  87
  88         if (mode == REBOOT_HARD)
  89                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
  90         else
  91                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
  92         writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
  93 }
  94
  95 static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
  96 {
  97         u32 temp;
  98
  99         temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 100
 101         if (mode == REBOOT_HARD)
 102                 temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
 103         else
 104                 temp |= RSTMGR_CTRL_SWWARMRSTREQ;
 105         writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
 106 }
 107
 108 static const char *altera_dt_match[] = {
 109         "altr,socfpga",
 110         NULL
 111 };
 112
 113 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 114         .l2c_aux_val    = 0,
 115         .l2c_aux_mask   = ~0,
 116         .init_irq       = socfpga_init_irq,
 117         .restart        = socfpga_cyclone5_restart,
 118         .dt_compat      = altera_dt_match,
 119 MACHINE_END
 120
 121 static const char *altera_a10_dt_match[] = {
 122         "altr,socfpga-arria10",
 123         NULL
 124 };
 125
 126 DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
 127         .l2c_aux_val    = 0,
 128         .l2c_aux_mask   = ~0,
 129         .init_irq       = socfpga_arria10_init_irq,
 130         .restart        = socfpga_arria10_restart,
 131         .dt_compat      = altera_a10_dt_match,
 132 MACHINE_END