arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/pm_domain.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/platform_data/sh_ipmmu.h>
  36
  37 #include <asm/mach/map.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/time.h>
  41
  42 #include "common.h"
  43 #include "dma-register.h"
  44 #include "intc.h"
  45 #include "irqs.h"
  46 #include "pm-rmobile.h"
  47 #include "sh7372.h"
  48
  49 static struct map_desc sh7372_io_desc[] __initdata = {
  50         /* create a 1:1 entity map for 0xe6xxxxxx
  51          * used by CPGA, INTC and PFC.
  52          */
  53         {
  54                 .virtual        = 0xe6000000,
  55                 .pfn            = __phys_to_pfn(0xe6000000),
  56                 .length         = 256 << 20,
  57                 .type           = MT_DEVICE_NONSHARED
  58         },
  59 };
  60
  61 void __init sh7372_map_io(void)
  62 {
  63         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  64 }
  65
  66 /* PFC */
  67 static struct resource sh7372_pfc_resources[] = {
  68         [0] = {
  69                 .start  = 0xe6050000,
  70                 .end    = 0xe6057fff,
  71                 .flags  = IORESOURCE_MEM,
  72         },
  73         [1] = {
  74                 .start  = 0xe605800c,
  75                 .end    = 0xe6058027,
  76                 .flags  = IORESOURCE_MEM,
  77         }
  78 };
  79
  80 static struct platform_device sh7372_pfc_device = {
  81         .name           = "pfc-sh7372",
  82         .id             = -1,
  83         .resource       = sh7372_pfc_resources,
  84         .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
  85 };
  86
  87 void __init sh7372_pinmux_init(void)
  88 {
  89         platform_device_register(&sh7372_pfc_device);
  90 }
  91
  92 /* SCIF */
  93 #define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
  94 static struct plat_sci_port scif##index##_platform_data = {     \
  95         .type           = scif_type,                            \
  96         .flags          = UPF_BOOT_AUTOCONF,                    \
  97         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  98 };                                                              \
  99                                                                 \
 100 static struct resource scif##index##_resources[] = {            \
 101         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 102         DEFINE_RES_IRQ(irq),                                    \
 103 };                                                              \
 104                                                                 \
 105 static struct platform_device scif##index##_device = {          \
 106         .name           = "sh-sci",                             \
 107         .id             = index,                                \
 108         .resource       = scif##index##_resources,              \
 109         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 110         .dev            = {                                     \
 111                 .platform_data  = &scif##index##_platform_data, \
 112         },                                                      \
 113 }
 114
 115 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
 116 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
 117 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
 118 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
 119 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
 120 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
 121 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 122
 123 /* CMT */
 124 static struct sh_timer_config cmt2_platform_data = {
 125         .channels_mask = 0x20,
 126 };
 127
 128 static struct resource cmt2_resources[] = {
 129         DEFINE_RES_MEM(0xe6130000, 0x50),
 130         DEFINE_RES_IRQ(evt2irq(0x0b80)),
 131 };
 132
 133 static struct platform_device cmt2_device = {
 134         .name           = "sh-cmt-32-fast",
 135         .id             = 2,
 136         .dev = {
 137                 .platform_data  = &cmt2_platform_data,
 138         },
 139         .resource       = cmt2_resources,
 140         .num_resources  = ARRAY_SIZE(cmt2_resources),
 141 };
 142
 143 /* TMU */
 144 static struct sh_timer_config tmu0_platform_data = {
 145         .channels_mask = 7,
 146 };
 147
 148 static struct resource tmu0_resources[] = {
 149         DEFINE_RES_MEM(0xfff60000, 0x2c),
 150         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 151         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 152         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 153 };
 154
 155 static struct platform_device tmu0_device = {
 156         .name           = "sh-tmu",
 157         .id             = 0,
 158         .dev = {
 159                 .platform_data  = &tmu0_platform_data,
 160         },
 161         .resource       = tmu0_resources,
 162         .num_resources  = ARRAY_SIZE(tmu0_resources),
 163 };
 164
 165 /* I2C */
 166 static struct resource iic0_resources[] = {
 167         [0] = {
 168                 .name   = "IIC0",
 169                 .start  = 0xFFF20000,
 170                 .end    = 0xFFF20425 - 1,
 171                 .flags  = IORESOURCE_MEM,
 172         },
 173         [1] = {
 174                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 175                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 176                 .flags  = IORESOURCE_IRQ,
 177         },
 178 };
 179
 180 static struct platform_device iic0_device = {
 181         .name           = "i2c-sh_mobile",
 182         .id             = 0, /* "i2c0" clock */
 183         .num_resources  = ARRAY_SIZE(iic0_resources),
 184         .resource       = iic0_resources,
 185 };
 186
 187 static struct resource iic1_resources[] = {
 188         [0] = {
 189                 .name   = "IIC1",
 190                 .start  = 0xE6C20000,
 191                 .end    = 0xE6C20425 - 1,
 192                 .flags  = IORESOURCE_MEM,
 193         },
 194         [1] = {
 195                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 196                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 197                 .flags  = IORESOURCE_IRQ,
 198         },
 199 };
 200
 201 static struct platform_device iic1_device = {
 202         .name           = "i2c-sh_mobile",
 203         .id             = 1, /* "i2c1" clock */
 204         .num_resources  = ARRAY_SIZE(iic1_resources),
 205         .resource       = iic1_resources,
 206 };
 207
 208 /* DMA */
 209 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 210         {
 211                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 212                 .addr           = 0xe6c40020,
 213                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 214                 .mid_rid        = 0x21,
 215         }, {
 216                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 217                 .addr           = 0xe6c40024,
 218                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 219                 .mid_rid        = 0x22,
 220         }, {
 221                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 222                 .addr           = 0xe6c50020,
 223                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 224                 .mid_rid        = 0x25,
 225         }, {
 226                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 227                 .addr           = 0xe6c50024,
 228                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 229                 .mid_rid        = 0x26,
 230         }, {
 231                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 232                 .addr           = 0xe6c60020,
 233                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 234                 .mid_rid        = 0x29,
 235         }, {
 236                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 237                 .addr           = 0xe6c60024,
 238                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 239                 .mid_rid        = 0x2a,
 240         }, {
 241                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 242                 .addr           = 0xe6c70020,
 243                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 244                 .mid_rid        = 0x2d,
 245         }, {
 246                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 247                 .addr           = 0xe6c70024,
 248                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 249                 .mid_rid        = 0x2e,
 250         }, {
 251                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 252                 .addr           = 0xe6c80020,
 253                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 254                 .mid_rid        = 0x39,
 255         }, {
 256                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 257                 .addr           = 0xe6c80024,
 258                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 259                 .mid_rid        = 0x3a,
 260         }, {
 261                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 262                 .addr           = 0xe6cb0020,
 263                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 264                 .mid_rid        = 0x35,
 265         }, {
 266                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 267                 .addr           = 0xe6cb0024,
 268                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 269                 .mid_rid        = 0x36,
 270         }, {
 271                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 272                 .addr           = 0xe6c30040,
 273                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 274                 .mid_rid        = 0x3d,
 275         }, {
 276                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 277                 .addr           = 0xe6c30060,
 278                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 279                 .mid_rid        = 0x3e,
 280         }, {
 281                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 282                 .addr           = 0xe6a30050,
 283                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 284                 .mid_rid        = 0x83,
 285         }, {
 286                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 287                 .addr           = 0xe6a30050,
 288                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 289                 .mid_rid        = 0x83,
 290         }, {
 291                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 292                 .addr           = 0xe6a30060,
 293                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 294                 .mid_rid        = 0x87,
 295         }, {
 296                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 297                 .addr           = 0xe6a30060,
 298                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 299                 .mid_rid        = 0x87,
 300         }, {
 301                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 302                 .addr           = 0xe6850030,
 303                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 304                 .mid_rid        = 0xc1,
 305         }, {
 306                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 307                 .addr           = 0xe6850030,
 308                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 309                 .mid_rid        = 0xc2,
 310         }, {
 311                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 312                 .addr           = 0xe6860030,
 313                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 314                 .mid_rid        = 0xc9,
 315         }, {
 316                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 317                 .addr           = 0xe6860030,
 318                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 319                 .mid_rid        = 0xca,
 320         }, {
 321                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 322                 .addr           = 0xe6870030,
 323                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 324                 .mid_rid        = 0xcd,
 325         }, {
 326                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 327                 .addr           = 0xe6870030,
 328                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 329                 .mid_rid        = 0xce,
 330         }, {
 331                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 332                 .addr           = 0xfe1f0024,
 333                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 334                 .mid_rid        = 0xb1,
 335         }, {
 336                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 337                 .addr           = 0xfe1f0020,
 338                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 339                 .mid_rid        = 0xb2,
 340         }, {
 341                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 342                 .addr           = 0xe6bd0034,
 343                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 344                 .mid_rid        = 0xd1,
 345         }, {
 346                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 347                 .addr           = 0xe6bd0034,
 348                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 349                 .mid_rid        = 0xd2,
 350         },
 351 };
 352
 353 #define SH7372_CHCLR (0x220 - 0x20)
 354
 355 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 356         {
 357                 .offset = 0,
 358                 .dmars = 0,
 359                 .dmars_bit = 0,
 360                 .chclr_offset = SH7372_CHCLR + 0,
 361         }, {
 362                 .offset = 0x10,
 363                 .dmars = 0,
 364                 .dmars_bit = 8,
 365                 .chclr_offset = SH7372_CHCLR + 0x10,
 366         }, {
 367                 .offset = 0x20,
 368                 .dmars = 4,
 369                 .dmars_bit = 0,
 370                 .chclr_offset = SH7372_CHCLR + 0x20,
 371         }, {
 372                 .offset = 0x30,
 373                 .dmars = 4,
 374                 .dmars_bit = 8,
 375                 .chclr_offset = SH7372_CHCLR + 0x30,
 376         }, {
 377                 .offset = 0x50,
 378                 .dmars = 8,
 379                 .dmars_bit = 0,
 380                 .chclr_offset = SH7372_CHCLR + 0x50,
 381         }, {
 382                 .offset = 0x60,
 383                 .dmars = 8,
 384                 .dmars_bit = 8,
 385                 .chclr_offset = SH7372_CHCLR + 0x60,
 386         }
 387 };
 388
 389 static struct sh_dmae_pdata dma_platform_data = {
 390         .slave          = sh7372_dmae_slaves,
 391         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 392         .channel        = sh7372_dmae_channels,
 393         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 394         .ts_low_shift   = TS_LOW_SHIFT,
 395         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 396         .ts_high_shift  = TS_HI_SHIFT,
 397         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 398         .ts_shift       = dma_ts_shift,
 399         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 400         .dmaor_init     = DMAOR_DME,
 401         .chclr_present  = 1,
 402 };
 403
 404 /* Resource order important! */
 405 static struct resource sh7372_dmae0_resources[] = {
 406         {
 407                 /* Channel registers and DMAOR */
 408                 .start  = 0xfe008020,
 409                 .end    = 0xfe00828f,
 410                 .flags  = IORESOURCE_MEM,
 411         },
 412         {
 413                 /* DMARSx */
 414                 .start  = 0xfe009000,
 415                 .end    = 0xfe00900b,
 416                 .flags  = IORESOURCE_MEM,
 417         },
 418         {
 419                 .name   = "error_irq",
 420                 .start  = evt2irq(0x20c0),
 421                 .end    = evt2irq(0x20c0),
 422                 .flags  = IORESOURCE_IRQ,
 423         },
 424         {
 425                 /* IRQ for channels 0-5 */
 426                 .start  = evt2irq(0x2000),
 427                 .end    = evt2irq(0x20a0),
 428                 .flags  = IORESOURCE_IRQ,
 429         },
 430 };
 431
 432 /* Resource order important! */
 433 static struct resource sh7372_dmae1_resources[] = {
 434         {
 435                 /* Channel registers and DMAOR */
 436                 .start  = 0xfe018020,
 437                 .end    = 0xfe01828f,
 438                 .flags  = IORESOURCE_MEM,
 439         },
 440         {
 441                 /* DMARSx */
 442                 .start  = 0xfe019000,
 443                 .end    = 0xfe01900b,
 444                 .flags  = IORESOURCE_MEM,
 445         },
 446         {
 447                 .name   = "error_irq",
 448                 .start  = evt2irq(0x21c0),
 449                 .end    = evt2irq(0x21c0),
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452         {
 453                 /* IRQ for channels 0-5 */
 454                 .start  = evt2irq(0x2100),
 455                 .end    = evt2irq(0x21a0),
 456                 .flags  = IORESOURCE_IRQ,
 457         },
 458 };
 459
 460 /* Resource order important! */
 461 static struct resource sh7372_dmae2_resources[] = {
 462         {
 463                 /* Channel registers and DMAOR */
 464                 .start  = 0xfe028020,
 465                 .end    = 0xfe02828f,
 466                 .flags  = IORESOURCE_MEM,
 467         },
 468         {
 469                 /* DMARSx */
 470                 .start  = 0xfe029000,
 471                 .end    = 0xfe02900b,
 472                 .flags  = IORESOURCE_MEM,
 473         },
 474         {
 475                 .name   = "error_irq",
 476                 .start  = evt2irq(0x22c0),
 477                 .end    = evt2irq(0x22c0),
 478                 .flags  = IORESOURCE_IRQ,
 479         },
 480         {
 481                 /* IRQ for channels 0-5 */
 482                 .start  = evt2irq(0x2200),
 483                 .end    = evt2irq(0x22a0),
 484                 .flags  = IORESOURCE_IRQ,
 485         },
 486 };
 487
 488 static struct platform_device dma0_device = {
 489         .name           = "sh-dma-engine",
 490         .id             = 0,
 491         .resource       = sh7372_dmae0_resources,
 492         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 493         .dev            = {
 494                 .platform_data  = &dma_platform_data,
 495         },
 496 };
 497
 498 static struct platform_device dma1_device = {
 499         .name           = "sh-dma-engine",
 500         .id             = 1,
 501         .resource       = sh7372_dmae1_resources,
 502         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 503         .dev            = {
 504                 .platform_data  = &dma_platform_data,
 505         },
 506 };
 507
 508 static struct platform_device dma2_device = {
 509         .name           = "sh-dma-engine",
 510         .id             = 2,
 511         .resource       = sh7372_dmae2_resources,
 512         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 513         .dev            = {
 514                 .platform_data  = &dma_platform_data,
 515         },
 516 };
 517
 518 /*
 519  * USB-DMAC
 520  */
 521 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 522         {
 523                 .offset = 0,
 524         }, {
 525                 .offset = 0x20,
 526         },
 527 };
 528
 529 /* USB DMAC0 */
 530 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 531         {
 532                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 533                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 534         }, {
 535                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 536                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 537         },
 538 };
 539
 540 static struct sh_dmae_pdata usb_dma0_platform_data = {
 541         .slave          = sh7372_usb_dmae0_slaves,
 542         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 543         .channel        = sh7372_usb_dmae_channels,
 544         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 545         .ts_low_shift   = USBTS_LOW_SHIFT,
 546         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 547         .ts_high_shift  = USBTS_HI_SHIFT,
 548         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 549         .ts_shift       = dma_usbts_shift,
 550         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 551         .dmaor_init     = DMAOR_DME,
 552         .chcr_offset    = 0x14,
 553         .chcr_ie_bit    = 1 << 5,
 554         .dmaor_is_32bit = 1,
 555         .needs_tend_set = 1,
 556         .no_dmars       = 1,
 557         .slave_only     = 1,
 558 };
 559
 560 static struct resource sh7372_usb_dmae0_resources[] = {
 561         {
 562                 /* Channel registers and DMAOR */
 563                 .start  = 0xe68a0020,
 564                 .end    = 0xe68a0064 - 1,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         {
 568                 /* VCR/SWR/DMICR */
 569                 .start  = 0xe68a0000,
 570                 .end    = 0xe68a0014 - 1,
 571                 .flags  = IORESOURCE_MEM,
 572         },
 573         {
 574                 /* IRQ for channels */
 575                 .start  = evt2irq(0x0a00),
 576                 .end    = evt2irq(0x0a00),
 577                 .flags  = IORESOURCE_IRQ,
 578         },
 579 };
 580
 581 static struct platform_device usb_dma0_device = {
 582         .name           = "sh-dma-engine",
 583         .id             = 3,
 584         .resource       = sh7372_usb_dmae0_resources,
 585         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 586         .dev            = {
 587                 .platform_data  = &usb_dma0_platform_data,
 588         },
 589 };
 590
 591 /* USB DMAC1 */
 592 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 593         {
 594                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 595                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 596         }, {
 597                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 598                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 599         },
 600 };
 601
 602 static struct sh_dmae_pdata usb_dma1_platform_data = {
 603         .slave          = sh7372_usb_dmae1_slaves,
 604         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 605         .channel        = sh7372_usb_dmae_channels,
 606         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 607         .ts_low_shift   = USBTS_LOW_SHIFT,
 608         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 609         .ts_high_shift  = USBTS_HI_SHIFT,
 610         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 611         .ts_shift       = dma_usbts_shift,
 612         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 613         .dmaor_init     = DMAOR_DME,
 614         .chcr_offset    = 0x14,
 615         .chcr_ie_bit    = 1 << 5,
 616         .dmaor_is_32bit = 1,
 617         .needs_tend_set = 1,
 618         .no_dmars       = 1,
 619         .slave_only     = 1,
 620 };
 621
 622 static struct resource sh7372_usb_dmae1_resources[] = {
 623         {
 624                 /* Channel registers and DMAOR */
 625                 .start  = 0xe68c0020,
 626                 .end    = 0xe68c0064 - 1,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         {
 630                 /* VCR/SWR/DMICR */
 631                 .start  = 0xe68c0000,
 632                 .end    = 0xe68c0014 - 1,
 633                 .flags  = IORESOURCE_MEM,
 634         },
 635         {
 636                 /* IRQ for channels */
 637                 .start  = evt2irq(0x1d00),
 638                 .end    = evt2irq(0x1d00),
 639                 .flags  = IORESOURCE_IRQ,
 640         },
 641 };
 642
 643 static struct platform_device usb_dma1_device = {
 644         .name           = "sh-dma-engine",
 645         .id             = 4,
 646         .resource       = sh7372_usb_dmae1_resources,
 647         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 648         .dev            = {
 649                 .platform_data  = &usb_dma1_platform_data,
 650         },
 651 };
 652
 653 /* VPU */
 654 static struct uio_info vpu_platform_data = {
 655         .name = "VPU5HG",
 656         .version = "0",
 657         .irq = intcs_evt2irq(0x980),
 658 };
 659
 660 static struct resource vpu_resources[] = {
 661         [0] = {
 662                 .name   = "VPU",
 663                 .start  = 0xfe900000,
 664                 .end    = 0xfe900157,
 665                 .flags  = IORESOURCE_MEM,
 666         },
 667 };
 668
 669 static struct platform_device vpu_device = {
 670         .name           = "uio_pdrv_genirq",
 671         .id             = 0,
 672         .dev = {
 673                 .platform_data  = &vpu_platform_data,
 674         },
 675         .resource       = vpu_resources,
 676         .num_resources  = ARRAY_SIZE(vpu_resources),
 677 };
 678
 679 /* VEU0 */
 680 static struct uio_info veu0_platform_data = {
 681         .name = "VEU0",
 682         .version = "0",
 683         .irq = intcs_evt2irq(0x700),
 684 };
 685
 686 static struct resource veu0_resources[] = {
 687         [0] = {
 688                 .name   = "VEU0",
 689                 .start  = 0xfe920000,
 690                 .end    = 0xfe9200cb,
 691                 .flags  = IORESOURCE_MEM,
 692         },
 693 };
 694
 695 static struct platform_device veu0_device = {
 696         .name           = "uio_pdrv_genirq",
 697         .id             = 1,
 698         .dev = {
 699                 .platform_data  = &veu0_platform_data,
 700         },
 701         .resource       = veu0_resources,
 702         .num_resources  = ARRAY_SIZE(veu0_resources),
 703 };
 704
 705 /* VEU1 */
 706 static struct uio_info veu1_platform_data = {
 707         .name = "VEU1",
 708         .version = "0",
 709         .irq = intcs_evt2irq(0x720),
 710 };
 711
 712 static struct resource veu1_resources[] = {
 713         [0] = {
 714                 .name   = "VEU1",
 715                 .start  = 0xfe924000,
 716                 .end    = 0xfe9240cb,
 717                 .flags  = IORESOURCE_MEM,
 718         },
 719 };
 720
 721 static struct platform_device veu1_device = {
 722         .name           = "uio_pdrv_genirq",
 723         .id             = 2,
 724         .dev = {
 725                 .platform_data  = &veu1_platform_data,
 726         },
 727         .resource       = veu1_resources,
 728         .num_resources  = ARRAY_SIZE(veu1_resources),
 729 };
 730
 731 /* VEU2 */
 732 static struct uio_info veu2_platform_data = {
 733         .name = "VEU2",
 734         .version = "0",
 735         .irq = intcs_evt2irq(0x740),
 736 };
 737
 738 static struct resource veu2_resources[] = {
 739         [0] = {
 740                 .name   = "VEU2",
 741                 .start  = 0xfe928000,
 742                 .end    = 0xfe928307,
 743                 .flags  = IORESOURCE_MEM,
 744         },
 745 };
 746
 747 static struct platform_device veu2_device = {
 748         .name           = "uio_pdrv_genirq",
 749         .id             = 3,
 750         .dev = {
 751                 .platform_data  = &veu2_platform_data,
 752         },
 753         .resource       = veu2_resources,
 754         .num_resources  = ARRAY_SIZE(veu2_resources),
 755 };
 756
 757 /* VEU3 */
 758 static struct uio_info veu3_platform_data = {
 759         .name = "VEU3",
 760         .version = "0",
 761         .irq = intcs_evt2irq(0x760),
 762 };
 763
 764 static struct resource veu3_resources[] = {
 765         [0] = {
 766                 .name   = "VEU3",
 767                 .start  = 0xfe92c000,
 768                 .end    = 0xfe92c307,
 769                 .flags  = IORESOURCE_MEM,
 770         },
 771 };
 772
 773 static struct platform_device veu3_device = {
 774         .name           = "uio_pdrv_genirq",
 775         .id             = 4,
 776         .dev = {
 777                 .platform_data  = &veu3_platform_data,
 778         },
 779         .resource       = veu3_resources,
 780         .num_resources  = ARRAY_SIZE(veu3_resources),
 781 };
 782
 783 /* JPU */
 784 static struct uio_info jpu_platform_data = {
 785         .name = "JPU",
 786         .version = "0",
 787         .irq = intcs_evt2irq(0x560),
 788 };
 789
 790 static struct resource jpu_resources[] = {
 791         [0] = {
 792                 .name   = "JPU",
 793                 .start  = 0xfe980000,
 794                 .end    = 0xfe9902d3,
 795                 .flags  = IORESOURCE_MEM,
 796         },
 797 };
 798
 799 static struct platform_device jpu_device = {
 800         .name           = "uio_pdrv_genirq",
 801         .id             = 5,
 802         .dev = {
 803                 .platform_data  = &jpu_platform_data,
 804         },
 805         .resource       = jpu_resources,
 806         .num_resources  = ARRAY_SIZE(jpu_resources),
 807 };
 808
 809 /* SPU2DSP0 */
 810 static struct uio_info spu0_platform_data = {
 811         .name = "SPU2DSP0",
 812         .version = "0",
 813         .irq = evt2irq(0x1800),
 814 };
 815
 816 static struct resource spu0_resources[] = {
 817         [0] = {
 818                 .name   = "SPU2DSP0",
 819                 .start  = 0xfe200000,
 820                 .end    = 0xfe2fffff,
 821                 .flags  = IORESOURCE_MEM,
 822         },
 823 };
 824
 825 static struct platform_device spu0_device = {
 826         .name           = "uio_pdrv_genirq",
 827         .id             = 6,
 828         .dev = {
 829                 .platform_data  = &spu0_platform_data,
 830         },
 831         .resource       = spu0_resources,
 832         .num_resources  = ARRAY_SIZE(spu0_resources),
 833 };
 834
 835 /* SPU2DSP1 */
 836 static struct uio_info spu1_platform_data = {
 837         .name = "SPU2DSP1",
 838         .version = "0",
 839         .irq = evt2irq(0x1820),
 840 };
 841
 842 static struct resource spu1_resources[] = {
 843         [0] = {
 844                 .name   = "SPU2DSP1",
 845                 .start  = 0xfe300000,
 846                 .end    = 0xfe3fffff,
 847                 .flags  = IORESOURCE_MEM,
 848         },
 849 };
 850
 851 static struct platform_device spu1_device = {
 852         .name           = "uio_pdrv_genirq",
 853         .id             = 7,
 854         .dev = {
 855                 .platform_data  = &spu1_platform_data,
 856         },
 857         .resource       = spu1_resources,
 858         .num_resources  = ARRAY_SIZE(spu1_resources),
 859 };
 860
 861 /* IPMMUI (an IPMMU module for ICB/LMB) */
 862 static struct resource ipmmu_resources[] = {
 863         [0] = {
 864                 .name   = "IPMMUI",
 865                 .start  = 0xfe951000,
 866                 .end    = 0xfe9510ff,
 867                 .flags  = IORESOURCE_MEM,
 868         },
 869 };
 870
 871 static const char * const ipmmu_dev_names[] = {
 872         "sh_mobile_lcdc_fb.0",
 873         "sh_mobile_lcdc_fb.1",
 874         "sh_mobile_ceu.0",
 875         "uio_pdrv_genirq.0",
 876         "uio_pdrv_genirq.1",
 877         "uio_pdrv_genirq.2",
 878         "uio_pdrv_genirq.3",
 879         "uio_pdrv_genirq.4",
 880         "uio_pdrv_genirq.5",
 881 };
 882
 883 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 884         .dev_names = ipmmu_dev_names,
 885         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 886 };
 887
 888 static struct platform_device ipmmu_device = {
 889         .name           = "ipmmu",
 890         .id             = -1,
 891         .dev = {
 892                 .platform_data = &ipmmu_platform_data,
 893         },
 894         .resource       = ipmmu_resources,
 895         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 896 };
 897
 898 static struct platform_device *sh7372_early_devices[] __initdata = {
 899         &scif0_device,
 900         &scif1_device,
 901         &scif2_device,
 902         &scif3_device,
 903         &scif4_device,
 904         &scif5_device,
 905         &scif6_device,
 906         &cmt2_device,
 907         &tmu0_device,
 908         &ipmmu_device,
 909 };
 910
 911 static struct platform_device *sh7372_late_devices[] __initdata = {
 912         &iic0_device,
 913         &iic1_device,
 914         &dma0_device,
 915         &dma1_device,
 916         &dma2_device,
 917         &usb_dma0_device,
 918         &usb_dma1_device,
 919         &vpu_device,
 920         &veu0_device,
 921         &veu1_device,
 922         &veu2_device,
 923         &veu3_device,
 924         &jpu_device,
 925         &spu0_device,
 926         &spu1_device,
 927 };
 928
 929 void __init sh7372_add_standard_devices(void)
 930 {
 931         static struct pm_domain_device domain_devices[] __initdata = {
 932                 { "A3RV", &vpu_device, },
 933                 { "A4MP", &spu0_device, },
 934                 { "A4MP", &spu1_device, },
 935                 { "A3SP", &scif0_device, },
 936                 { "A3SP", &scif1_device, },
 937                 { "A3SP", &scif2_device, },
 938                 { "A3SP", &scif3_device, },
 939                 { "A3SP", &scif4_device, },
 940                 { "A3SP", &scif5_device, },
 941                 { "A3SP", &scif6_device, },
 942                 { "A3SP", &iic1_device, },
 943                 { "A3SP", &dma0_device, },
 944                 { "A3SP", &dma1_device, },
 945                 { "A3SP", &dma2_device, },
 946                 { "A3SP", &usb_dma0_device, },
 947                 { "A3SP", &usb_dma1_device, },
 948                 { "A4R", &iic0_device, },
 949                 { "A4R", &veu0_device, },
 950                 { "A4R", &veu1_device, },
 951                 { "A4R", &veu2_device, },
 952                 { "A4R", &veu3_device, },
 953                 { "A4R", &jpu_device, },
 954                 { "A4R", &tmu0_device, },
 955         };
 956
 957         sh7372_init_pm_domains();
 958
 959         platform_add_devices(sh7372_early_devices,
 960                             ARRAY_SIZE(sh7372_early_devices));
 961
 962         platform_add_devices(sh7372_late_devices,
 963                             ARRAY_SIZE(sh7372_late_devices));
 964
 965         rmobile_add_devices_to_domains(domain_devices,
 966                                        ARRAY_SIZE(domain_devices));
 967 }
 968
 969 void __init sh7372_earlytimer_init(void)
 970 {
 971         sh7372_clock_init();
 972         shmobile_earlytimer_init();
 973 }
 974
 975 void __init sh7372_add_early_devices(void)
 976 {
 977         early_platform_add_devices(sh7372_early_devices,
 978                                    ARRAY_SIZE(sh7372_early_devices));
 979
 980         /* setup early console here as well */
 981         shmobile_setup_console();
 982 }
 983
 984 #ifdef CONFIG_USE_OF
 985
 986 void __init sh7372_add_early_devices_dt(void)
 987 {
 988         shmobile_init_delay();
 989
 990         sh7372_add_early_devices();
 991 }
 992
 993 void __init sh7372_add_standard_devices_dt(void)
 994 {
 995         /* clocks are setup late during boot in the case of DT */
 996         sh7372_clock_init();
 997
 998         platform_add_devices(sh7372_early_devices,
 999                             ARRAY_SIZE(sh7372_early_devices));
1000
1001         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1002 }
1003
1004 static const char *sh7372_boards_compat_dt[] __initdata = {
1005         "renesas,sh7372",
1006         NULL,
1007 };
1008
1009 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1010         .map_io         = sh7372_map_io,
1011         .init_early     = sh7372_add_early_devices_dt,
1012         .init_irq       = sh7372_init_irq,
1013         .handle_irq     = shmobile_handle_irq_intc,
1014         .init_machine   = sh7372_add_standard_devices_dt,
1015         .dt_compat      = sh7372_boards_compat_dt,
1016 MACHINE_END
1017
1018 #endif /* CONFIG_USE_OF */