arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/arch.h>
  38 #include <asm/mach/time.h>
  39 #include <asm/hardware/cache-l2x0.h>
  40
  41 #include "common.h"
  42 #include "dma-register.h"
  43 #include "irqs.h"
  44 #include "pm-rmobile.h"
  45 #include "r8a7740.h"
  46
  47 static struct map_desc r8a7740_io_desc[] __initdata = {
  48          /*
  49           * for CPGA/INTC/PFC
  50           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  51           */
  52         {
  53                 .virtual        = 0xe6000000,
  54                 .pfn            = __phys_to_pfn(0xe6000000),
  55                 .length         = 160 << 20,
  56                 .type           = MT_DEVICE_NONSHARED
  57         },
  58 #ifdef CONFIG_CACHE_L2X0
  59         /*
  60          * for l2x0_init()
  61          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  62          */
  63         {
  64                 .virtual        = 0xf0002000,
  65                 .pfn            = __phys_to_pfn(0xf0100000),
  66                 .length         = PAGE_SIZE,
  67                 .type           = MT_DEVICE_NONSHARED
  68         },
  69 #endif
  70 };
  71
  72 void __init r8a7740_map_io(void)
  73 {
  74         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  75 }
  76
  77 /* PFC */
  78 static const struct resource pfc_resources[] = {
  79         DEFINE_RES_MEM(0xe6050000, 0x8000),
  80         DEFINE_RES_MEM(0xe605800c, 0x0020),
  81 };
  82
  83 void __init r8a7740_pinmux_init(void)
  84 {
  85         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  86                                         ARRAY_SIZE(pfc_resources));
  87 }
  88
  89 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  90         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  91 };
  92
  93 static struct resource irqpin0_resources[] = {
  94         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  95         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  96         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  97         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  98         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
 103         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 104         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 105         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 106         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 107 };
 108
 109 static struct platform_device irqpin0_device = {
 110         .name           = "renesas_intc_irqpin",
 111         .id             = 0,
 112         .resource       = irqpin0_resources,
 113         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 114         .dev            = {
 115                 .platform_data  = &irqpin0_platform_data,
 116         },
 117 };
 118
 119 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 120         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 121 };
 122
 123 static struct resource irqpin1_resources[] = {
 124         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 125         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 126         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 127         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 128         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 133         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 134         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 135         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 136         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 137 };
 138
 139 static struct platform_device irqpin1_device = {
 140         .name           = "renesas_intc_irqpin",
 141         .id             = 1,
 142         .resource       = irqpin1_resources,
 143         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 144         .dev            = {
 145                 .platform_data  = &irqpin1_platform_data,
 146         },
 147 };
 148
 149 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 150         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 151 };
 152
 153 static struct resource irqpin2_resources[] = {
 154         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 155         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 156         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 157         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 158         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 163         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 164         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 165         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 166         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 167 };
 168
 169 static struct platform_device irqpin2_device = {
 170         .name           = "renesas_intc_irqpin",
 171         .id             = 2,
 172         .resource       = irqpin2_resources,
 173         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 174         .dev            = {
 175                 .platform_data  = &irqpin2_platform_data,
 176         },
 177 };
 178
 179 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 180         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 181 };
 182
 183 static struct resource irqpin3_resources[] = {
 184         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 185         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 186         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 187         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 188         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 193         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 194         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 195         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 196         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 197 };
 198
 199 static struct platform_device irqpin3_device = {
 200         .name           = "renesas_intc_irqpin",
 201         .id             = 3,
 202         .resource       = irqpin3_resources,
 203         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 204         .dev            = {
 205                 .platform_data  = &irqpin3_platform_data,
 206         },
 207 };
 208
 209 /* SCIF */
 210 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 211 static struct plat_sci_port scif##index##_platform_data = {     \
 212         .type           = scif_type,                            \
 213         .flags          = UPF_BOOT_AUTOCONF,                    \
 214         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 215 };                                                              \
 216                                                                 \
 217 static struct resource scif##index##_resources[] = {            \
 218         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 219         DEFINE_RES_IRQ(irq),                                    \
 220 };                                                              \
 221                                                                 \
 222 static struct platform_device scif##index##_device = {          \
 223         .name           = "sh-sci",                             \
 224         .id             = index,                                \
 225         .resource       = scif##index##_resources,              \
 226         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 227         .dev            = {                                     \
 228                 .platform_data  = &scif##index##_platform_data, \
 229         },                                                      \
 230 }
 231
 232 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 233 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 234 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 235 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 236 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 237 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 238 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 239 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 240 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 241
 242 /* CMT */
 243 static struct sh_timer_config cmt1_platform_data = {
 244         .channels_mask = 0x3f,
 245 };
 246
 247 static struct resource cmt1_resources[] = {
 248         DEFINE_RES_MEM(0xe6138000, 0x170),
 249         DEFINE_RES_IRQ(gic_spi(58)),
 250 };
 251
 252 static struct platform_device cmt1_device = {
 253         .name           = "sh-cmt-48",
 254         .id             = 1,
 255         .dev = {
 256                 .platform_data  = &cmt1_platform_data,
 257         },
 258         .resource       = cmt1_resources,
 259         .num_resources  = ARRAY_SIZE(cmt1_resources),
 260 };
 261
 262 /* TMU */
 263 static struct sh_timer_config tmu0_platform_data = {
 264         .channels_mask = 7,
 265 };
 266
 267 static struct resource tmu0_resources[] = {
 268         DEFINE_RES_MEM(0xfff80000, 0x2c),
 269         DEFINE_RES_IRQ(gic_spi(198)),
 270         DEFINE_RES_IRQ(gic_spi(199)),
 271         DEFINE_RES_IRQ(gic_spi(200)),
 272 };
 273
 274 static struct platform_device tmu0_device = {
 275         .name           = "sh-tmu",
 276         .id             = 0,
 277         .dev = {
 278                 .platform_data  = &tmu0_platform_data,
 279         },
 280         .resource       = tmu0_resources,
 281         .num_resources  = ARRAY_SIZE(tmu0_resources),
 282 };
 283
 284 /* IPMMUI (an IPMMU module for ICB/LMB) */
 285 static struct resource ipmmu_resources[] = {
 286         [0] = {
 287                 .name   = "IPMMUI",
 288                 .start  = 0xfe951000,
 289                 .end    = 0xfe9510ff,
 290                 .flags  = IORESOURCE_MEM,
 291         },
 292 };
 293
 294 static const char * const ipmmu_dev_names[] = {
 295         "sh_mobile_lcdc_fb.0",
 296         "sh_mobile_lcdc_fb.1",
 297         "sh_mobile_ceu.0",
 298 };
 299
 300 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 301         .dev_names = ipmmu_dev_names,
 302         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 303 };
 304
 305 static struct platform_device ipmmu_device = {
 306         .name           = "ipmmu",
 307         .id             = -1,
 308         .dev = {
 309                 .platform_data = &ipmmu_platform_data,
 310         },
 311         .resource       = ipmmu_resources,
 312         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 313 };
 314
 315 static struct platform_device *r8a7740_early_devices[] __initdata = {
 316         &scif0_device,
 317         &scif1_device,
 318         &scif2_device,
 319         &scif3_device,
 320         &scif4_device,
 321         &scif5_device,
 322         &scif6_device,
 323         &scif7_device,
 324         &scif8_device,
 325         &irqpin0_device,
 326         &irqpin1_device,
 327         &irqpin2_device,
 328         &irqpin3_device,
 329         &tmu0_device,
 330         &ipmmu_device,
 331         &cmt1_device,
 332 };
 333
 334 /* DMA */
 335 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 336         {
 337                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 338                 .addr           = 0xe6850030,
 339                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 340                 .mid_rid        = 0xc1,
 341         }, {
 342                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 343                 .addr           = 0xe6850030,
 344                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 345                 .mid_rid        = 0xc2,
 346         }, {
 347                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 348                 .addr           = 0xe6860030,
 349                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 350                 .mid_rid        = 0xc9,
 351         }, {
 352                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 353                 .addr           = 0xe6860030,
 354                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 355                 .mid_rid        = 0xca,
 356         }, {
 357                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 358                 .addr           = 0xe6870030,
 359                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 360                 .mid_rid        = 0xcd,
 361         }, {
 362                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 363                 .addr           = 0xe6870030,
 364                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 365                 .mid_rid        = 0xce,
 366         }, {
 367                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 368                 .addr           = 0xfe1f0024,
 369                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 370                 .mid_rid        = 0xb1,
 371         }, {
 372                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 373                 .addr           = 0xfe1f0020,
 374                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 375                 .mid_rid        = 0xb2,
 376         }, {
 377                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 378                 .addr           = 0xfe1f0064,
 379                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 380                 .mid_rid        = 0xb5,
 381         }, {
 382                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 383                 .addr           = 0xe6bd0034,
 384                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 385                 .mid_rid        = 0xd1,
 386         }, {
 387                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 388                 .addr           = 0xe6bd0034,
 389                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 390                 .mid_rid        = 0xd2,
 391         },
 392 };
 393
 394 #define DMA_CHANNEL(a, b, c)                    \
 395 {                                               \
 396         .offset         = a,                    \
 397         .dmars          = b,                    \
 398         .dmars_bit      = c,                    \
 399         .chclr_offset   = (0x220 - 0x20) + a    \
 400 }
 401
 402 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 403         DMA_CHANNEL(0x00, 0, 0),
 404         DMA_CHANNEL(0x10, 0, 8),
 405         DMA_CHANNEL(0x20, 4, 0),
 406         DMA_CHANNEL(0x30, 4, 8),
 407         DMA_CHANNEL(0x50, 8, 0),
 408         DMA_CHANNEL(0x60, 8, 8),
 409 };
 410
 411 static struct sh_dmae_pdata dma_platform_data = {
 412         .slave          = r8a7740_dmae_slaves,
 413         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 414         .channel        = r8a7740_dmae_channels,
 415         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 416         .ts_low_shift   = TS_LOW_SHIFT,
 417         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 418         .ts_high_shift  = TS_HI_SHIFT,
 419         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 420         .ts_shift       = dma_ts_shift,
 421         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 422         .dmaor_init     = DMAOR_DME,
 423         .chclr_present  = 1,
 424 };
 425
 426 /* Resource order important! */
 427 static struct resource r8a7740_dmae0_resources[] = {
 428         {
 429                 /* Channel registers and DMAOR */
 430                 .start  = 0xfe008020,
 431                 .end    = 0xfe00828f,
 432                 .flags  = IORESOURCE_MEM,
 433         },
 434         {
 435                 /* DMARSx */
 436                 .start  = 0xfe009000,
 437                 .end    = 0xfe00900b,
 438                 .flags  = IORESOURCE_MEM,
 439         },
 440         {
 441                 .name   = "error_irq",
 442                 .start  = gic_spi(34),
 443                 .end    = gic_spi(34),
 444                 .flags  = IORESOURCE_IRQ,
 445         },
 446         {
 447                 /* IRQ for channels 0-5 */
 448                 .start  = gic_spi(28),
 449                 .end    = gic_spi(33),
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452 };
 453
 454 /* Resource order important! */
 455 static struct resource r8a7740_dmae1_resources[] = {
 456         {
 457                 /* Channel registers and DMAOR */
 458                 .start  = 0xfe018020,
 459                 .end    = 0xfe01828f,
 460                 .flags  = IORESOURCE_MEM,
 461         },
 462         {
 463                 /* DMARSx */
 464                 .start  = 0xfe019000,
 465                 .end    = 0xfe01900b,
 466                 .flags  = IORESOURCE_MEM,
 467         },
 468         {
 469                 .name   = "error_irq",
 470                 .start  = gic_spi(41),
 471                 .end    = gic_spi(41),
 472                 .flags  = IORESOURCE_IRQ,
 473         },
 474         {
 475                 /* IRQ for channels 0-5 */
 476                 .start  = gic_spi(35),
 477                 .end    = gic_spi(40),
 478                 .flags  = IORESOURCE_IRQ,
 479         },
 480 };
 481
 482 /* Resource order important! */
 483 static struct resource r8a7740_dmae2_resources[] = {
 484         {
 485                 /* Channel registers and DMAOR */
 486                 .start  = 0xfe028020,
 487                 .end    = 0xfe02828f,
 488                 .flags  = IORESOURCE_MEM,
 489         },
 490         {
 491                 /* DMARSx */
 492                 .start  = 0xfe029000,
 493                 .end    = 0xfe02900b,
 494                 .flags  = IORESOURCE_MEM,
 495         },
 496         {
 497                 .name   = "error_irq",
 498                 .start  = gic_spi(48),
 499                 .end    = gic_spi(48),
 500                 .flags  = IORESOURCE_IRQ,
 501         },
 502         {
 503                 /* IRQ for channels 0-5 */
 504                 .start  = gic_spi(42),
 505                 .end    = gic_spi(47),
 506                 .flags  = IORESOURCE_IRQ,
 507         },
 508 };
 509
 510 static struct platform_device dma0_device = {
 511         .name           = "sh-dma-engine",
 512         .id             = 0,
 513         .resource       = r8a7740_dmae0_resources,
 514         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 515         .dev            = {
 516                 .platform_data  = &dma_platform_data,
 517         },
 518 };
 519
 520 static struct platform_device dma1_device = {
 521         .name           = "sh-dma-engine",
 522         .id             = 1,
 523         .resource       = r8a7740_dmae1_resources,
 524         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 525         .dev            = {
 526                 .platform_data  = &dma_platform_data,
 527         },
 528 };
 529
 530 static struct platform_device dma2_device = {
 531         .name           = "sh-dma-engine",
 532         .id             = 2,
 533         .resource       = r8a7740_dmae2_resources,
 534         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 535         .dev            = {
 536                 .platform_data  = &dma_platform_data,
 537         },
 538 };
 539
 540 /* USB-DMAC */
 541 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 542         {
 543                 .offset = 0,
 544         }, {
 545                 .offset = 0x20,
 546         },
 547 };
 548
 549 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 550         {
 551                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 552                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 553         }, {
 554                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 555                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 556         },
 557 };
 558
 559 static struct sh_dmae_pdata usb_dma_platform_data = {
 560         .slave          = r8a7740_usb_dma_slaves,
 561         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 562         .channel        = r8a7740_usb_dma_channels,
 563         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 564         .ts_low_shift   = USBTS_LOW_SHIFT,
 565         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 566         .ts_high_shift  = USBTS_HI_SHIFT,
 567         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 568         .ts_shift       = dma_usbts_shift,
 569         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 570         .dmaor_init     = DMAOR_DME,
 571         .chcr_offset    = 0x14,
 572         .chcr_ie_bit    = 1 << 5,
 573         .dmaor_is_32bit = 1,
 574         .needs_tend_set = 1,
 575         .no_dmars       = 1,
 576         .slave_only     = 1,
 577 };
 578
 579 static struct resource r8a7740_usb_dma_resources[] = {
 580         {
 581                 /* Channel registers and DMAOR */
 582                 .start  = 0xe68a0020,
 583                 .end    = 0xe68a0064 - 1,
 584                 .flags  = IORESOURCE_MEM,
 585         },
 586         {
 587                 /* VCR/SWR/DMICR */
 588                 .start  = 0xe68a0000,
 589                 .end    = 0xe68a0014 - 1,
 590                 .flags  = IORESOURCE_MEM,
 591         },
 592         {
 593                 /* IRQ for channels */
 594                 .start  = gic_spi(49),
 595                 .end    = gic_spi(49),
 596                 .flags  = IORESOURCE_IRQ,
 597         },
 598 };
 599
 600 static struct platform_device usb_dma_device = {
 601         .name           = "sh-dma-engine",
 602         .id             = 3,
 603         .resource       = r8a7740_usb_dma_resources,
 604         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 605         .dev            = {
 606                 .platform_data  = &usb_dma_platform_data,
 607         },
 608 };
 609
 610 /* I2C */
 611 static struct resource i2c0_resources[] = {
 612         [0] = {
 613                 .name   = "IIC0",
 614                 .start  = 0xfff20000,
 615                 .end    = 0xfff20425 - 1,
 616                 .flags  = IORESOURCE_MEM,
 617         },
 618         [1] = {
 619                 .start  = gic_spi(201),
 620                 .end    = gic_spi(204),
 621                 .flags  = IORESOURCE_IRQ,
 622         },
 623 };
 624
 625 static struct resource i2c1_resources[] = {
 626         [0] = {
 627                 .name   = "IIC1",
 628                 .start  = 0xe6c20000,
 629                 .end    = 0xe6c20425 - 1,
 630                 .flags  = IORESOURCE_MEM,
 631         },
 632         [1] = {
 633                 .start  = gic_spi(70), /* IIC1_ALI1 */
 634                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 635                 .flags  = IORESOURCE_IRQ,
 636         },
 637 };
 638
 639 static struct platform_device i2c0_device = {
 640         .name           = "i2c-sh_mobile",
 641         .id             = 0,
 642         .resource       = i2c0_resources,
 643         .num_resources  = ARRAY_SIZE(i2c0_resources),
 644 };
 645
 646 static struct platform_device i2c1_device = {
 647         .name           = "i2c-sh_mobile",
 648         .id             = 1,
 649         .resource       = i2c1_resources,
 650         .num_resources  = ARRAY_SIZE(i2c1_resources),
 651 };
 652
 653 static struct resource pmu_resources[] = {
 654         [0] = {
 655                 .start  = gic_spi(83),
 656                 .end    = gic_spi(83),
 657                 .flags  = IORESOURCE_IRQ,
 658         },
 659 };
 660
 661 static struct platform_device pmu_device = {
 662         .name   = "arm-pmu",
 663         .id     = -1,
 664         .num_resources = ARRAY_SIZE(pmu_resources),
 665         .resource = pmu_resources,
 666 };
 667
 668 static struct platform_device *r8a7740_late_devices[] __initdata = {
 669         &i2c0_device,
 670         &i2c1_device,
 671         &dma0_device,
 672         &dma1_device,
 673         &dma2_device,
 674         &usb_dma_device,
 675         &pmu_device,
 676 };
 677
 678 /*
 679  * r8a7740 chip has lasting errata on MERAM buffer.
 680  * this is work-around for it.
 681  * see
 682  *      "Media RAM (MERAM)" on r8a7740 documentation
 683  */
 684 #define MEBUFCNTR       0xFE950098
 685 void __init r8a7740_meram_workaround(void)
 686 {
 687         void __iomem *reg;
 688
 689         reg = ioremap_nocache(MEBUFCNTR, 4);
 690         if (reg) {
 691                 iowrite32(0x01600164, reg);
 692                 iounmap(reg);
 693         }
 694 }
 695
 696 #define ICCR    0x0004
 697 #define ICSTART 0x0070
 698
 699 #define i2c_read(reg, offset)           ioread8(reg + offset)
 700 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 701
 702 /*
 703  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 704  * this is work-around for it.
 705  */
 706 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 707 {
 708         struct resource *res;
 709         void __iomem *reg;
 710
 711         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 712         if (unlikely(!res)) {
 713                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 714                 return;
 715         }
 716
 717         reg = ioremap(res->start, resource_size(res));
 718         if (unlikely(!reg)) {
 719                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 720                 return;
 721         }
 722
 723         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 724         i2c_read(reg, ICCR); /* dummy read */
 725
 726         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 727         i2c_read(reg, ICSTART); /* dummy read */
 728
 729         udelay(10);
 730
 731         i2c_write(reg, ICCR, 0x01);
 732         i2c_write(reg, ICSTART, 0x00);
 733
 734         udelay(10);
 735
 736         i2c_write(reg, ICCR, 0x10);
 737         udelay(10);
 738         i2c_write(reg, ICCR, 0x00);
 739         udelay(10);
 740         i2c_write(reg, ICCR, 0x10);
 741         udelay(10);
 742
 743         iounmap(reg);
 744 }
 745
 746 void __init r8a7740_add_standard_devices(void)
 747 {
 748         static struct pm_domain_device domain_devices[] __initdata = {
 749                 { "A3SP", &scif0_device },
 750                 { "A3SP", &scif1_device },
 751                 { "A3SP", &scif2_device },
 752                 { "A3SP", &scif3_device },
 753                 { "A3SP", &scif4_device },
 754                 { "A3SP", &scif5_device },
 755                 { "A3SP", &scif6_device },
 756                 { "A3SP", &scif7_device },
 757                 { "A3SP", &scif8_device },
 758                 { "A3SP", &i2c1_device },
 759         };
 760
 761         /* I2C work-around */
 762         r8a7740_i2c_workaround(&i2c0_device);
 763         r8a7740_i2c_workaround(&i2c1_device);
 764
 765         r8a7740_init_pm_domains();
 766
 767         /* add devices */
 768         platform_add_devices(r8a7740_early_devices,
 769                             ARRAY_SIZE(r8a7740_early_devices));
 770         platform_add_devices(r8a7740_late_devices,
 771                              ARRAY_SIZE(r8a7740_late_devices));
 772
 773         /* add devices to PM domain  */
 774         rmobile_add_devices_to_domains(domain_devices,
 775                                        ARRAY_SIZE(domain_devices));
 776 }
 777
 778 void __init r8a7740_add_early_devices(void)
 779 {
 780         early_platform_add_devices(r8a7740_early_devices,
 781                                    ARRAY_SIZE(r8a7740_early_devices));
 782
 783         /* setup early console here as well */
 784         shmobile_setup_console();
 785 }
 786
 787 #ifdef CONFIG_USE_OF
 788
 789 void __init r8a7740_init_irq_of(void)
 790 {
 791         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 792         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 793         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 794
 795         irqchip_init();
 796
 797         /* route signals to GIC */
 798         iowrite32(0x0, pfc_inta_ctrl);
 799
 800         /*
 801          * To mask the shared interrupt to SPI 149 we must ensure to set
 802          * PRIO *and* MASK. Else we run into IRQ floods when registering
 803          * the intc_irqpin devices
 804          */
 805         iowrite32(0x0, intc_prio_base + 0x0);
 806         iowrite32(0x0, intc_prio_base + 0x4);
 807         iowrite32(0x0, intc_prio_base + 0x8);
 808         iowrite32(0x0, intc_prio_base + 0xc);
 809         iowrite8(0xff, intc_msk_base + 0x0);
 810         iowrite8(0xff, intc_msk_base + 0x4);
 811         iowrite8(0xff, intc_msk_base + 0x8);
 812         iowrite8(0xff, intc_msk_base + 0xc);
 813
 814         iounmap(intc_prio_base);
 815         iounmap(intc_msk_base);
 816         iounmap(pfc_inta_ctrl);
 817 }
 818
 819 static void __init r8a7740_generic_init(void)
 820 {
 821         r8a7740_meram_workaround();
 822
 823 #ifdef CONFIG_CACHE_L2X0
 824         /* Shared attribute override enable, 32K*8way */
 825         l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
 826 #endif
 827         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 828 }
 829
 830 #define RESCNT2 IOMEM(0xe6188020)
 831 static void r8a7740_restart(enum reboot_mode mode, const char *cmd)
 832 {
 833         /* Do soft power on reset */
 834         writel(1 << 31, RESCNT2);
 835 }
 836
 837 static const char *r8a7740_boards_compat_dt[] __initdata = {
 838         "renesas,r8a7740",
 839         NULL,
 840 };
 841
 842 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 843         .map_io         = r8a7740_map_io,
 844         .init_early     = shmobile_init_delay,
 845         .init_irq       = r8a7740_init_irq_of,
 846         .init_machine   = r8a7740_generic_init,
 847         .init_late      = shmobile_init_late,
 848         .dt_compat      = r8a7740_boards_compat_dt,
 849         .restart        = r8a7740_restart,
 850 MACHINE_END
 851
 852 #endif /* CONFIG_USE_OF */