Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
[sfrench/cifs-2.6.git] / arch / arm / mach-s5pv210 / clock.c
1 /* linux/arch/arm/mach-s5pv210/clock.c
2  *
3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com/
5  *
6  * S5PV210 - Clock support
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
21 #include <linux/io.h>
22
23 #include <mach/map.h>
24
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
28 #include <plat/cpu.h>
29 #include <plat/pll.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
33
34 static struct clksrc_clk clk_mout_apll = {
35         .clk    = {
36                 .name           = "mout_apll",
37                 .id             = -1,
38         },
39         .sources        = &clk_src_apll,
40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
41 };
42
43 static struct clksrc_clk clk_mout_epll = {
44         .clk    = {
45                 .name           = "mout_epll",
46                 .id             = -1,
47         },
48         .sources        = &clk_src_epll,
49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
50 };
51
52 static struct clksrc_clk clk_mout_mpll = {
53         .clk = {
54                 .name           = "mout_mpll",
55                 .id             = -1,
56         },
57         .sources        = &clk_src_mpll,
58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59 };
60
61 static struct clk *clkset_armclk_list[] = {
62         [0] = &clk_mout_apll.clk,
63         [1] = &clk_mout_mpll.clk,
64 };
65
66 static struct clksrc_sources clkset_armclk = {
67         .sources        = clkset_armclk_list,
68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
69 };
70
71 static struct clksrc_clk clk_armclk = {
72         .clk    = {
73                 .name           = "armclk",
74                 .id             = -1,
75         },
76         .sources        = &clkset_armclk,
77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79 };
80
81 static struct clksrc_clk clk_hclk_msys = {
82         .clk    = {
83                 .name           = "hclk_msys",
84                 .id             = -1,
85                 .parent         = &clk_armclk.clk,
86         },
87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
88 };
89
90 static struct clksrc_clk clk_pclk_msys = {
91         .clk    = {
92                 .name           = "pclk_msys",
93                 .id             = -1,
94                 .parent         = &clk_hclk_msys.clk,
95         },
96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
97 };
98
99 static struct clksrc_clk clk_sclk_a2m = {
100         .clk    = {
101                 .name           = "sclk_a2m",
102                 .id             = -1,
103                 .parent         = &clk_mout_apll.clk,
104         },
105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
106 };
107
108 static struct clk *clkset_hclk_sys_list[] = {
109         [0] = &clk_mout_mpll.clk,
110         [1] = &clk_sclk_a2m.clk,
111 };
112
113 static struct clksrc_sources clkset_hclk_sys = {
114         .sources        = clkset_hclk_sys_list,
115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
116 };
117
118 static struct clksrc_clk clk_hclk_dsys = {
119         .clk    = {
120                 .name   = "hclk_dsys",
121                 .id     = -1,
122         },
123         .sources        = &clkset_hclk_sys,
124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
126 };
127
128 static struct clksrc_clk clk_pclk_dsys = {
129         .clk    = {
130                 .name   = "pclk_dsys",
131                 .id     = -1,
132                 .parent = &clk_hclk_dsys.clk,
133         },
134         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
135 };
136
137 static struct clksrc_clk clk_hclk_psys = {
138         .clk    = {
139                 .name   = "hclk_psys",
140                 .id     = -1,
141         },
142         .sources        = &clkset_hclk_sys,
143         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
145 };
146
147 static struct clksrc_clk clk_pclk_psys = {
148         .clk    = {
149                 .name   = "pclk_psys",
150                 .id     = -1,
151                 .parent = &clk_hclk_psys.clk,
152         },
153         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
154 };
155
156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
157 {
158         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
159 }
160
161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
162 {
163         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
164 }
165
166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
167 {
168         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
169 }
170
171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
172 {
173         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
174 }
175
176 static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
177 {
178         return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
179 }
180
181 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
182 {
183         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184 }
185
186 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187 {
188         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
189 }
190
191 static struct clk clk_sclk_hdmi27m = {
192         .name           = "sclk_hdmi27m",
193         .id             = -1,
194         .rate           = 27000000,
195 };
196
197 static struct clk clk_sclk_hdmiphy = {
198         .name           = "sclk_hdmiphy",
199         .id             = -1,
200 };
201
202 static struct clk clk_sclk_usbphy0 = {
203         .name           = "sclk_usbphy0",
204         .id             = -1,
205 };
206
207 static struct clk clk_sclk_usbphy1 = {
208         .name           = "sclk_usbphy1",
209         .id             = -1,
210 };
211
212 static struct clk clk_pcmcdclk0 = {
213         .name           = "pcmcdclk",
214         .id             = -1,
215 };
216
217 static struct clk clk_pcmcdclk1 = {
218         .name           = "pcmcdclk",
219         .id             = -1,
220 };
221
222 static struct clk clk_pcmcdclk2 = {
223         .name           = "pcmcdclk",
224         .id             = -1,
225 };
226
227 static struct clk *clkset_vpllsrc_list[] = {
228         [0] = &clk_fin_vpll,
229         [1] = &clk_sclk_hdmi27m,
230 };
231
232 static struct clksrc_sources clkset_vpllsrc = {
233         .sources        = clkset_vpllsrc_list,
234         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
235 };
236
237 static struct clksrc_clk clk_vpllsrc = {
238         .clk    = {
239                 .name           = "vpll_src",
240                 .id             = -1,
241                 .enable         = s5pv210_clk_mask0_ctrl,
242                 .ctrlbit        = (1 << 7),
243         },
244         .sources        = &clkset_vpllsrc,
245         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
246 };
247
248 static struct clk *clkset_sclk_vpll_list[] = {
249         [0] = &clk_vpllsrc.clk,
250         [1] = &clk_fout_vpll,
251 };
252
253 static struct clksrc_sources clkset_sclk_vpll = {
254         .sources        = clkset_sclk_vpll_list,
255         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
256 };
257
258 static struct clksrc_clk clk_sclk_vpll = {
259         .clk    = {
260                 .name           = "sclk_vpll",
261                 .id             = -1,
262         },
263         .sources        = &clkset_sclk_vpll,
264         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
265 };
266
267 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
268 {
269         return clk_get_rate(clk->parent) / 2;
270 }
271
272 static struct clk_ops clk_hclk_imem_ops = {
273         .get_rate       = s5pv210_clk_imem_get_rate,
274 };
275
276 static struct clk init_clocks_disable[] = {
277         {
278                 .name           = "rot",
279                 .id             = -1,
280                 .parent         = &clk_hclk_dsys.clk,
281                 .enable         = s5pv210_clk_ip0_ctrl,
282                 .ctrlbit        = (1<<29),
283         }, {
284                 .name           = "otg",
285                 .id             = -1,
286                 .parent         = &clk_hclk_psys.clk,
287                 .enable         = s5pv210_clk_ip1_ctrl,
288                 .ctrlbit        = (1<<16),
289         }, {
290                 .name           = "usb-host",
291                 .id             = -1,
292                 .parent         = &clk_hclk_psys.clk,
293                 .enable         = s5pv210_clk_ip1_ctrl,
294                 .ctrlbit        = (1<<17),
295         }, {
296                 .name           = "lcd",
297                 .id             = -1,
298                 .parent         = &clk_hclk_dsys.clk,
299                 .enable         = s5pv210_clk_ip1_ctrl,
300                 .ctrlbit        = (1<<0),
301         }, {
302                 .name           = "cfcon",
303                 .id             = 0,
304                 .parent         = &clk_hclk_psys.clk,
305                 .enable         = s5pv210_clk_ip1_ctrl,
306                 .ctrlbit        = (1<<25),
307         }, {
308                 .name           = "hsmmc",
309                 .id             = 0,
310                 .parent         = &clk_hclk_psys.clk,
311                 .enable         = s5pv210_clk_ip2_ctrl,
312                 .ctrlbit        = (1<<16),
313         }, {
314                 .name           = "hsmmc",
315                 .id             = 1,
316                 .parent         = &clk_hclk_psys.clk,
317                 .enable         = s5pv210_clk_ip2_ctrl,
318                 .ctrlbit        = (1<<17),
319         }, {
320                 .name           = "hsmmc",
321                 .id             = 2,
322                 .parent         = &clk_hclk_psys.clk,
323                 .enable         = s5pv210_clk_ip2_ctrl,
324                 .ctrlbit        = (1<<18),
325         }, {
326                 .name           = "hsmmc",
327                 .id             = 3,
328                 .parent         = &clk_hclk_psys.clk,
329                 .enable         = s5pv210_clk_ip2_ctrl,
330                 .ctrlbit        = (1<<19),
331         }, {
332                 .name           = "systimer",
333                 .id             = -1,
334                 .parent         = &clk_pclk_psys.clk,
335                 .enable         = s5pv210_clk_ip3_ctrl,
336                 .ctrlbit        = (1<<16),
337         }, {
338                 .name           = "watchdog",
339                 .id             = -1,
340                 .parent         = &clk_pclk_psys.clk,
341                 .enable         = s5pv210_clk_ip3_ctrl,
342                 .ctrlbit        = (1<<22),
343         }, {
344                 .name           = "rtc",
345                 .id             = -1,
346                 .parent         = &clk_pclk_psys.clk,
347                 .enable         = s5pv210_clk_ip3_ctrl,
348                 .ctrlbit        = (1<<15),
349         }, {
350                 .name           = "i2c",
351                 .id             = 0,
352                 .parent         = &clk_pclk_psys.clk,
353                 .enable         = s5pv210_clk_ip3_ctrl,
354                 .ctrlbit        = (1<<7),
355         }, {
356                 .name           = "i2c",
357                 .id             = 1,
358                 .parent         = &clk_pclk_psys.clk,
359                 .enable         = s5pv210_clk_ip3_ctrl,
360                 .ctrlbit        = (1<<8),
361         }, {
362                 .name           = "i2c",
363                 .id             = 2,
364                 .parent         = &clk_pclk_psys.clk,
365                 .enable         = s5pv210_clk_ip3_ctrl,
366                 .ctrlbit        = (1<<9),
367         }, {
368                 .name           = "spi",
369                 .id             = 0,
370                 .parent         = &clk_pclk_psys.clk,
371                 .enable         = s5pv210_clk_ip3_ctrl,
372                 .ctrlbit        = (1<<12),
373         }, {
374                 .name           = "spi",
375                 .id             = 1,
376                 .parent         = &clk_pclk_psys.clk,
377                 .enable         = s5pv210_clk_ip3_ctrl,
378                 .ctrlbit        = (1<<13),
379         }, {
380                 .name           = "spi",
381                 .id             = 2,
382                 .parent         = &clk_pclk_psys.clk,
383                 .enable         = s5pv210_clk_ip3_ctrl,
384                 .ctrlbit        = (1<<14),
385         }, {
386                 .name           = "timers",
387                 .id             = -1,
388                 .parent         = &clk_pclk_psys.clk,
389                 .enable         = s5pv210_clk_ip3_ctrl,
390                 .ctrlbit        = (1<<23),
391         }, {
392                 .name           = "adc",
393                 .id             = -1,
394                 .parent         = &clk_pclk_psys.clk,
395                 .enable         = s5pv210_clk_ip3_ctrl,
396                 .ctrlbit        = (1<<24),
397         }, {
398                 .name           = "keypad",
399                 .id             = -1,
400                 .parent         = &clk_pclk_psys.clk,
401                 .enable         = s5pv210_clk_ip3_ctrl,
402                 .ctrlbit        = (1<<21),
403         }, {
404                 .name           = "i2s_v50",
405                 .id             = 0,
406                 .parent         = &clk_p,
407                 .enable         = s5pv210_clk_ip3_ctrl,
408                 .ctrlbit        = (1<<4),
409         }, {
410                 .name           = "i2s_v32",
411                 .id             = 0,
412                 .parent         = &clk_p,
413                 .enable         = s5pv210_clk_ip3_ctrl,
414                 .ctrlbit        = (1 << 5),
415         }, {
416                 .name           = "i2s_v32",
417                 .id             = 1,
418                 .parent         = &clk_p,
419                 .enable         = s5pv210_clk_ip3_ctrl,
420                 .ctrlbit        = (1 << 6),
421         },
422 };
423
424 static struct clk init_clocks[] = {
425         {
426                 .name           = "hclk_imem",
427                 .id             = -1,
428                 .parent         = &clk_hclk_msys.clk,
429                 .ctrlbit        = (1 << 5),
430                 .enable         = s5pv210_clk_ip0_ctrl,
431                 .ops            = &clk_hclk_imem_ops,
432         }, {
433                 .name           = "uart",
434                 .id             = 0,
435                 .parent         = &clk_pclk_psys.clk,
436                 .enable         = s5pv210_clk_ip3_ctrl,
437                 .ctrlbit        = (1 << 17),
438         }, {
439                 .name           = "uart",
440                 .id             = 1,
441                 .parent         = &clk_pclk_psys.clk,
442                 .enable         = s5pv210_clk_ip3_ctrl,
443                 .ctrlbit        = (1 << 18),
444         }, {
445                 .name           = "uart",
446                 .id             = 2,
447                 .parent         = &clk_pclk_psys.clk,
448                 .enable         = s5pv210_clk_ip3_ctrl,
449                 .ctrlbit        = (1 << 19),
450         }, {
451                 .name           = "uart",
452                 .id             = 3,
453                 .parent         = &clk_pclk_psys.clk,
454                 .enable         = s5pv210_clk_ip3_ctrl,
455                 .ctrlbit        = (1 << 20),
456         },
457 };
458
459 static struct clk *clkset_uart_list[] = {
460         [6] = &clk_mout_mpll.clk,
461         [7] = &clk_mout_epll.clk,
462 };
463
464 static struct clksrc_sources clkset_uart = {
465         .sources        = clkset_uart_list,
466         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
467 };
468
469 static struct clk *clkset_group1_list[] = {
470         [0] = &clk_sclk_a2m.clk,
471         [1] = &clk_mout_mpll.clk,
472         [2] = &clk_mout_epll.clk,
473         [3] = &clk_sclk_vpll.clk,
474 };
475
476 static struct clksrc_sources clkset_group1 = {
477         .sources        = clkset_group1_list,
478         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
479 };
480
481 static struct clk *clkset_sclk_onenand_list[] = {
482         [0] = &clk_hclk_psys.clk,
483         [1] = &clk_hclk_dsys.clk,
484 };
485
486 static struct clksrc_sources clkset_sclk_onenand = {
487         .sources        = clkset_sclk_onenand_list,
488         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
489 };
490
491 static struct clk *clkset_sclk_dac_list[] = {
492         [0] = &clk_sclk_vpll.clk,
493         [1] = &clk_sclk_hdmiphy,
494 };
495
496 static struct clksrc_sources clkset_sclk_dac = {
497         .sources        = clkset_sclk_dac_list,
498         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
499 };
500
501 static struct clksrc_clk clk_sclk_dac = {
502         .clk            = {
503                 .name           = "sclk_dac",
504                 .id             = -1,
505                 .enable         = s5pv210_clk_mask0_ctrl,
506                 .ctrlbit        = (1 << 2),
507         },
508         .sources        = &clkset_sclk_dac,
509         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
510 };
511
512 static struct clksrc_clk clk_sclk_pixel = {
513         .clk            = {
514                 .name           = "sclk_pixel",
515                 .id             = -1,
516                 .parent         = &clk_sclk_vpll.clk,
517         },
518         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
519 };
520
521 static struct clk *clkset_sclk_hdmi_list[] = {
522         [0] = &clk_sclk_pixel.clk,
523         [1] = &clk_sclk_hdmiphy,
524 };
525
526 static struct clksrc_sources clkset_sclk_hdmi = {
527         .sources        = clkset_sclk_hdmi_list,
528         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
529 };
530
531 static struct clksrc_clk clk_sclk_hdmi = {
532         .clk            = {
533                 .name           = "sclk_hdmi",
534                 .id             = -1,
535                 .enable         = s5pv210_clk_mask0_ctrl,
536                 .ctrlbit        = (1 << 0),
537         },
538         .sources        = &clkset_sclk_hdmi,
539         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
540 };
541
542 static struct clk *clkset_sclk_mixer_list[] = {
543         [0] = &clk_sclk_dac.clk,
544         [1] = &clk_sclk_hdmi.clk,
545 };
546
547 static struct clksrc_sources clkset_sclk_mixer = {
548         .sources        = clkset_sclk_mixer_list,
549         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
550 };
551
552 static struct clk *clkset_sclk_audio0_list[] = {
553         [0] = &clk_ext_xtal_mux,
554         [1] = &clk_pcmcdclk0,
555         [2] = &clk_sclk_hdmi27m,
556         [3] = &clk_sclk_usbphy0,
557         [4] = &clk_sclk_usbphy1,
558         [5] = &clk_sclk_hdmiphy,
559         [6] = &clk_mout_mpll.clk,
560         [7] = &clk_mout_epll.clk,
561         [8] = &clk_sclk_vpll.clk,
562 };
563
564 static struct clksrc_sources clkset_sclk_audio0 = {
565         .sources        = clkset_sclk_audio0_list,
566         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
567 };
568
569 static struct clksrc_clk clk_sclk_audio0 = {
570         .clk            = {
571                 .name           = "sclk_audio",
572                 .id             = 0,
573                 .enable         = s5pv210_clk_mask0_ctrl,
574                 .ctrlbit        = (1 << 24),
575         },
576         .sources = &clkset_sclk_audio0,
577         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
578         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
579 };
580
581 static struct clk *clkset_sclk_audio1_list[] = {
582         [0] = &clk_ext_xtal_mux,
583         [1] = &clk_pcmcdclk1,
584         [2] = &clk_sclk_hdmi27m,
585         [3] = &clk_sclk_usbphy0,
586         [4] = &clk_sclk_usbphy1,
587         [5] = &clk_sclk_hdmiphy,
588         [6] = &clk_mout_mpll.clk,
589         [7] = &clk_mout_epll.clk,
590         [8] = &clk_sclk_vpll.clk,
591 };
592
593 static struct clksrc_sources clkset_sclk_audio1 = {
594         .sources        = clkset_sclk_audio1_list,
595         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
596 };
597
598 static struct clksrc_clk clk_sclk_audio1 = {
599         .clk            = {
600                 .name           = "sclk_audio",
601                 .id             = 1,
602                 .enable         = s5pv210_clk_mask0_ctrl,
603                 .ctrlbit        = (1 << 25),
604         },
605         .sources = &clkset_sclk_audio1,
606         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
607         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
608 };
609
610 static struct clk *clkset_sclk_audio2_list[] = {
611         [0] = &clk_ext_xtal_mux,
612         [1] = &clk_pcmcdclk0,
613         [2] = &clk_sclk_hdmi27m,
614         [3] = &clk_sclk_usbphy0,
615         [4] = &clk_sclk_usbphy1,
616         [5] = &clk_sclk_hdmiphy,
617         [6] = &clk_mout_mpll.clk,
618         [7] = &clk_mout_epll.clk,
619         [8] = &clk_sclk_vpll.clk,
620 };
621
622 static struct clksrc_sources clkset_sclk_audio2 = {
623         .sources        = clkset_sclk_audio2_list,
624         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
625 };
626
627 static struct clksrc_clk clk_sclk_audio2 = {
628         .clk            = {
629                 .name           = "sclk_audio",
630                 .id             = 2,
631                 .enable         = s5pv210_clk_mask0_ctrl,
632                 .ctrlbit        = (1 << 26),
633         },
634         .sources = &clkset_sclk_audio2,
635         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
636         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
637 };
638
639 static struct clk *clkset_sclk_spdif_list[] = {
640         [0] = &clk_sclk_audio0.clk,
641         [1] = &clk_sclk_audio1.clk,
642         [2] = &clk_sclk_audio2.clk,
643 };
644
645 static struct clksrc_sources clkset_sclk_spdif = {
646         .sources        = clkset_sclk_spdif_list,
647         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
648 };
649
650 static struct clk *clkset_group2_list[] = {
651         [0] = &clk_ext_xtal_mux,
652         [1] = &clk_xusbxti,
653         [2] = &clk_sclk_hdmi27m,
654         [3] = &clk_sclk_usbphy0,
655         [4] = &clk_sclk_usbphy1,
656         [5] = &clk_sclk_hdmiphy,
657         [6] = &clk_mout_mpll.clk,
658         [7] = &clk_mout_epll.clk,
659         [8] = &clk_sclk_vpll.clk,
660 };
661
662 static struct clksrc_sources clkset_group2 = {
663         .sources        = clkset_group2_list,
664         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
665 };
666
667 static struct clksrc_clk clksrcs[] = {
668         {
669                 .clk    = {
670                         .name           = "sclk_dmc",
671                         .id             = -1,
672                 },
673                 .sources = &clkset_group1,
674                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
675                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
676         }, {
677                 .clk    = {
678                         .name           = "sclk_onenand",
679                         .id             = -1,
680                 },
681                 .sources = &clkset_sclk_onenand,
682                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
683                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
684         }, {
685                 .clk    = {
686                         .name           = "uclk1",
687                         .id             = 0,
688                         .enable         = s5pv210_clk_mask0_ctrl,
689                         .ctrlbit        = (1 << 12),
690                 },
691                 .sources = &clkset_uart,
692                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
693                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
694         }, {
695                 .clk            = {
696                         .name           = "uclk1",
697                         .id             = 1,
698                         .enable         = s5pv210_clk_mask0_ctrl,
699                         .ctrlbit        = (1 << 13),
700                 },
701                 .sources = &clkset_uart,
702                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
703                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
704         }, {
705                 .clk            = {
706                         .name           = "uclk1",
707                         .id             = 2,
708                         .enable         = s5pv210_clk_mask0_ctrl,
709                         .ctrlbit        = (1 << 14),
710                 },
711                 .sources = &clkset_uart,
712                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
713                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
714         }, {
715                 .clk            = {
716                         .name           = "uclk1",
717                         .id             = 3,
718                         .enable         = s5pv210_clk_mask0_ctrl,
719                         .ctrlbit        = (1 << 15),
720                 },
721                 .sources = &clkset_uart,
722                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
723                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
724         }, {
725                 .clk    = {
726                         .name           = "sclk_mixer",
727                         .id             = -1,
728                         .enable         = s5pv210_clk_mask0_ctrl,
729                         .ctrlbit        = (1 << 1),
730                 },
731                 .sources = &clkset_sclk_mixer,
732                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
733         }, {
734                 .clk            = {
735                         .name           = "sclk_spdif",
736                         .id             = -1,
737                         .enable         = s5pv210_clk_mask0_ctrl,
738                         .ctrlbit        = (1 << 27),
739                 },
740                 .sources = &clkset_sclk_spdif,
741                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
742         }, {
743                 .clk    = {
744                         .name           = "sclk_fimc",
745                         .id             = 0,
746                         .enable         = s5pv210_clk_mask1_ctrl,
747                         .ctrlbit        = (1 << 2),
748                 },
749                 .sources = &clkset_group2,
750                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
751                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
752         }, {
753                 .clk    = {
754                         .name           = "sclk_fimc",
755                         .id             = 1,
756                         .enable         = s5pv210_clk_mask1_ctrl,
757                         .ctrlbit        = (1 << 3),
758                 },
759                 .sources = &clkset_group2,
760                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
761                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
762         }, {
763                 .clk    = {
764                         .name           = "sclk_fimc",
765                         .id             = 2,
766                         .enable         = s5pv210_clk_mask1_ctrl,
767                         .ctrlbit        = (1 << 4),
768                 },
769                 .sources = &clkset_group2,
770                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
771                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
772         }, {
773                 .clk            = {
774                         .name           = "sclk_cam",
775                         .id             = 0,
776                         .enable         = s5pv210_clk_mask0_ctrl,
777                         .ctrlbit        = (1 << 3),
778                 },
779                 .sources = &clkset_group2,
780                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
781                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
782         }, {
783                 .clk            = {
784                         .name           = "sclk_cam",
785                         .id             = 1,
786                         .enable         = s5pv210_clk_mask0_ctrl,
787                         .ctrlbit        = (1 << 4),
788                 },
789                 .sources = &clkset_group2,
790                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
791                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
792         }, {
793                 .clk            = {
794                         .name           = "sclk_fimd",
795                         .id             = -1,
796                         .enable         = s5pv210_clk_mask0_ctrl,
797                         .ctrlbit        = (1 << 5),
798                 },
799                 .sources = &clkset_group2,
800                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
801                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
802         }, {
803                 .clk            = {
804                         .name           = "sclk_mmc",
805                         .id             = 0,
806                         .enable         = s5pv210_clk_mask0_ctrl,
807                         .ctrlbit        = (1 << 8),
808                 },
809                 .sources = &clkset_group2,
810                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
811                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
812         }, {
813                 .clk            = {
814                         .name           = "sclk_mmc",
815                         .id             = 1,
816                         .enable         = s5pv210_clk_mask0_ctrl,
817                         .ctrlbit        = (1 << 9),
818                 },
819                 .sources = &clkset_group2,
820                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
821                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
822         }, {
823                 .clk            = {
824                         .name           = "sclk_mmc",
825                         .id             = 2,
826                         .enable         = s5pv210_clk_mask0_ctrl,
827                         .ctrlbit        = (1 << 10),
828                 },
829                 .sources = &clkset_group2,
830                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
831                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
832         }, {
833                 .clk            = {
834                         .name           = "sclk_mmc",
835                         .id             = 3,
836                         .enable         = s5pv210_clk_mask0_ctrl,
837                         .ctrlbit        = (1 << 11),
838                 },
839                 .sources = &clkset_group2,
840                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
841                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
842         }, {
843                 .clk            = {
844                         .name           = "sclk_mfc",
845                         .id             = -1,
846                         .enable         = s5pv210_clk_ip0_ctrl,
847                         .ctrlbit        = (1 << 16),
848                 },
849                 .sources = &clkset_group1,
850                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
851                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
852         }, {
853                 .clk            = {
854                         .name           = "sclk_g2d",
855                         .id             = -1,
856                         .enable         = s5pv210_clk_ip0_ctrl,
857                         .ctrlbit        = (1 << 12),
858                 },
859                 .sources = &clkset_group1,
860                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
861                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
862         }, {
863                 .clk            = {
864                         .name           = "sclk_g3d",
865                         .id             = -1,
866                         .enable         = s5pv210_clk_ip0_ctrl,
867                         .ctrlbit        = (1 << 8),
868                 },
869                 .sources = &clkset_group1,
870                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
871                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
872         }, {
873                 .clk            = {
874                         .name           = "sclk_csis",
875                         .id             = -1,
876                         .enable         = s5pv210_clk_mask0_ctrl,
877                         .ctrlbit        = (1 << 6),
878                 },
879                 .sources = &clkset_group2,
880                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
881                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
882         }, {
883                 .clk            = {
884                         .name           = "sclk_spi",
885                         .id             = 0,
886                         .enable         = s5pv210_clk_mask0_ctrl,
887                         .ctrlbit        = (1 << 16),
888                 },
889                 .sources = &clkset_group2,
890                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
891                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
892         }, {
893                 .clk            = {
894                         .name           = "sclk_spi",
895                         .id             = 1,
896                         .enable         = s5pv210_clk_mask0_ctrl,
897                         .ctrlbit        = (1 << 17),
898                 },
899                 .sources = &clkset_group2,
900                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
901                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
902         }, {
903                 .clk            = {
904                         .name           = "sclk_pwi",
905                         .id             = -1,
906                         .enable         = s5pv210_clk_mask0_ctrl,
907                         .ctrlbit        = (1 << 29),
908                 },
909                 .sources = &clkset_group2,
910                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
911                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
912         }, {
913                 .clk            = {
914                         .name           = "sclk_pwm",
915                         .id             = -1,
916                         .enable         = s5pv210_clk_mask0_ctrl,
917                         .ctrlbit        = (1 << 19),
918                 },
919                 .sources = &clkset_group2,
920                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
921                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
922         },
923 };
924
925 /* Clock initialisation code */
926 static struct clksrc_clk *sysclks[] = {
927         &clk_mout_apll,
928         &clk_mout_epll,
929         &clk_mout_mpll,
930         &clk_armclk,
931         &clk_hclk_msys,
932         &clk_sclk_a2m,
933         &clk_hclk_dsys,
934         &clk_hclk_psys,
935         &clk_pclk_msys,
936         &clk_pclk_dsys,
937         &clk_pclk_psys,
938         &clk_vpllsrc,
939         &clk_sclk_vpll,
940         &clk_sclk_dac,
941         &clk_sclk_pixel,
942         &clk_sclk_hdmi,
943 };
944
945 void __init_or_cpufreq s5pv210_setup_clocks(void)
946 {
947         struct clk *xtal_clk;
948         unsigned long xtal;
949         unsigned long vpllsrc;
950         unsigned long armclk;
951         unsigned long hclk_msys;
952         unsigned long hclk_dsys;
953         unsigned long hclk_psys;
954         unsigned long pclk_msys;
955         unsigned long pclk_dsys;
956         unsigned long pclk_psys;
957         unsigned long apll;
958         unsigned long mpll;
959         unsigned long epll;
960         unsigned long vpll;
961         unsigned int ptr;
962         u32 clkdiv0, clkdiv1;
963
964         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
965
966         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
967         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
968
969         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
970                                 __func__, clkdiv0, clkdiv1);
971
972         xtal_clk = clk_get(NULL, "xtal");
973         BUG_ON(IS_ERR(xtal_clk));
974
975         xtal = clk_get_rate(xtal_clk);
976         clk_put(xtal_clk);
977
978         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
979
980         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
981         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
982         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
983         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
984         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
985
986         clk_fout_apll.rate = apll;
987         clk_fout_mpll.rate = mpll;
988         clk_fout_epll.rate = epll;
989         clk_fout_vpll.rate = vpll;
990
991         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
992                         apll, mpll, epll, vpll);
993
994         armclk = clk_get_rate(&clk_armclk.clk);
995         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
996         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
997         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
998         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
999         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1000         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1001
1002         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1003                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1004                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1005                         pclk_msys, pclk_dsys, pclk_psys);
1006
1007         clk_f.rate = armclk;
1008         clk_h.rate = hclk_psys;
1009         clk_p.rate = pclk_psys;
1010
1011         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1012                 s3c_set_clksrc(&clksrcs[ptr], true);
1013 }
1014
1015 static struct clk *clks[] __initdata = {
1016         &clk_sclk_hdmi27m,
1017         &clk_sclk_hdmiphy,
1018         &clk_sclk_usbphy0,
1019         &clk_sclk_usbphy1,
1020         &clk_pcmcdclk0,
1021         &clk_pcmcdclk1,
1022         &clk_pcmcdclk2,
1023 };
1024
1025 void __init s5pv210_register_clocks(void)
1026 {
1027         struct clk *clkp;
1028         int ret;
1029         int ptr;
1030
1031         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1032         if (ret > 0)
1033                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1034
1035         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1036                 s3c_register_clksrc(sysclks[ptr], 1);
1037
1038         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1039         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1040
1041         clkp = init_clocks_disable;
1042         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1043                 ret = s3c24xx_register_clock(clkp);
1044                 if (ret < 0) {
1045                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
1046                                clkp->name, ret);
1047                 }
1048                 (clkp->enable)(clkp, 0);
1049         }
1050
1051         s3c_pwmclk_init();
1052 }