arch/arm/mach-s5pc100/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Copyright 2009 Samsung Electronics Co.
   6  *      Byungho Min <bhmin@samsung.com>
   7  *
   8  * Common Codes for S5PC100
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/list.h>
  19 #include <linux/timer.h>
  20 #include <linux/init.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/device.h>
  24 #include <linux/serial_core.h>
  25 #include <linux/serial_s3c.h>
  26 #include <clocksource/samsung_pwm.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/sched.h>
  29 #include <linux/reboot.h>
  30
  31 #include <asm/irq.h>
  32 #include <asm/proc-fns.h>
  33 #include <asm/system_misc.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37
  38 #include <mach/map.h>
  39 #include <mach/hardware.h>
  40 #include <mach/regs-clock.h>
  41
  42 #include <plat/cpu.h>
  43 #include <plat/devs.h>
  44 #include <plat/clock.h>
  45 #include <plat/sdhci.h>
  46 #include <plat/adc-core.h>
  47 #include <plat/ata-core.h>
  48 #include <plat/fb-core.h>
  49 #include <plat/iic-core.h>
  50 #include <plat/onenand-core.h>
  51 #include <plat/pwm-core.h>
  52 #include <plat/spi-core.h>
  53 #include <plat/watchdog-reset.h>
  54
  55 #include "common.h"
  56
  57 static const char name_s5pc100[] = "S5PC100";
  58
  59 static struct cpu_table cpu_ids[] __initdata = {
  60         {
  61                 .idcode         = S5PC100_CPU_ID,
  62                 .idmask         = S5PC100_CPU_MASK,
  63                 .map_io         = s5pc100_map_io,
  64                 .init_clocks    = s5pc100_init_clocks,
  65                 .init_uarts     = s5pc100_init_uarts,
  66                 .init           = s5pc100_init,
  67                 .name           = name_s5pc100,
  68         },
  69 };
  70
  71 /* Initial IO mappings */
  72
  73 static struct map_desc s5pc100_iodesc[] __initdata = {
  74         {
  75                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  76                 .pfn            = __phys_to_pfn(S5PC100_PA_CHIPID),
  77                 .length         = SZ_4K,
  78                 .type           = MT_DEVICE,
  79         }, {
  80                 .virtual        = (unsigned long)S3C_VA_SYS,
  81                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSCON),
  82                 .length         = SZ_64K,
  83                 .type           = MT_DEVICE,
  84         }, {
  85                 .virtual        = (unsigned long)S3C_VA_TIMER,
  86                 .pfn            = __phys_to_pfn(S5PC100_PA_TIMER),
  87                 .length         = SZ_16K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  91                 .pfn            = __phys_to_pfn(S5PC100_PA_WATCHDOG),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S5P_VA_SROMC,
  96                 .pfn            = __phys_to_pfn(S5PC100_PA_SROMC),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 101                 .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
 102                 .length         = SZ_16K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_GPIO,
 106                 .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)VA_VIC0,
 111                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
 112                 .length         = SZ_16K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)VA_VIC1,
 116                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
 117                 .length         = SZ_16K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)VA_VIC2,
 121                 .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
 122                 .length         = SZ_16K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S3C_VA_UART,
 126                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 127                 .length         = SZ_512K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S5PC100_VA_OTHERS,
 131                 .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE,
 134         }
 135 };
 136
 137 static struct samsung_pwm_variant s5pc100_pwm_variant = {
 138         .bits           = 32,
 139         .div_base       = 0,
 140         .has_tint_cstat = true,
 141         .tclk_mask      = (1 << 5),
 142 };
 143
 144 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 145 {
 146         s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 147         s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 148 }
 149
 150 void __init samsung_timer_init(void)
 151 {
 152         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 153                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 154                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 155         };
 156
 157         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 158                                         timer_irqs, &s5pc100_pwm_variant);
 159 }
 160
 161 /*
 162  * s5pc100_map_io
 163  *
 164  * register the standard CPU IO areas
 165  */
 166
 167 void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
 168 {
 169         /* initialize the io descriptors we need for initialization */
 170         iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
 171         if (mach_desc)
 172                 iotable_init(mach_desc, size);
 173
 174         /* detect cpu id and rev. */
 175         s5p_init_cpu(S5P_VA_CHIPID);
 176
 177         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 178
 179         samsung_pwm_set_platdata(&s5pc100_pwm_variant);
 180 }
 181
 182 void __init s5pc100_map_io(void)
 183 {
 184         /* initialise device information early */
 185         s5pc100_default_sdhci0();
 186         s5pc100_default_sdhci1();
 187         s5pc100_default_sdhci2();
 188
 189         s3c_adc_setname("s3c64xx-adc");
 190
 191         /* the i2c devices are directly compatible with s3c2440 */
 192         s3c_i2c0_setname("s3c2440-i2c");
 193         s3c_i2c1_setname("s3c2440-i2c");
 194
 195         s3c_onenand_setname("s5pc100-onenand");
 196         s3c_fb_setname("s5pc100-fb");
 197         s3c_cfcon_setname("s5pc100-pata");
 198
 199         s3c64xx_spi_setname("s5pc100-spi");
 200 }
 201
 202 void __init s5pc100_init_clocks(int xtal)
 203 {
 204         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 205
 206         s3c24xx_register_baseclocks(xtal);
 207         s5p_register_clocks(xtal);
 208         s5pc100_register_clocks();
 209         s5pc100_setup_clocks();
 210         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 211 }
 212
 213 void __init s5pc100_init_irq(void)
 214 {
 215         u32 vic[] = {~0, ~0, ~0};
 216
 217         /* VIC0, VIC1, and VIC2 are fully populated. */
 218         s5p_init_irq(vic, ARRAY_SIZE(vic));
 219 }
 220
 221 static struct bus_type s5pc100_subsys = {
 222         .name           = "s5pc100-core",
 223         .dev_name       = "s5pc100-core",
 224 };
 225
 226 static struct device s5pc100_dev = {
 227         .bus    = &s5pc100_subsys,
 228 };
 229
 230 static int __init s5pc100_core_init(void)
 231 {
 232         return subsys_system_register(&s5pc100_subsys, NULL);
 233 }
 234 core_initcall(s5pc100_core_init);
 235
 236 int __init s5pc100_init(void)
 237 {
 238         printk(KERN_INFO "S5PC100: Initializing architecture\n");
 239         return device_register(&s5pc100_dev);
 240 }
 241
 242 /* uart registration process */
 243
 244 void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 245 {
 246         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 247 }
 248
 249 void s5pc100_restart(enum reboot_mode mode, const char *cmd)
 250 {
 251         if (mode != REBOOT_SOFT)
 252                 samsung_wdt_reset();
 253
 254         soft_restart(0);
 255 }