ARM: S3C24XX: Add samsung-time support for s3c24xx
[sfrench/cifs-2.6.git] / arch / arm / mach-s3c24xx / mach-jive.c
1 /* linux/arch/arm/mach-s3c2410/mach-jive.c
2  *
3  * Copyright 2007 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * http://armlinux.simtec.co.uk/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/syscore_ops.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/i2c.h>
24
25 #include <video/ili9320.h>
26
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi_gpio.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <plat/regs-serial.h>
35 #include <linux/platform_data/mtd-nand-s3c2410.h>
36 #include <linux/platform_data/i2c-s3c2410.h>
37
38 #include <mach/regs-gpio.h>
39 #include <mach/regs-lcd.h>
40 #include <mach/fb.h>
41
42 #include <asm/mach-types.h>
43
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/partitions.h>
48
49 #include <plat/gpio-cfg.h>
50 #include <plat/clock.h>
51 #include <plat/devs.h>
52 #include <plat/cpu.h>
53 #include <plat/pm.h>
54 #include <linux/platform_data/usb-s3c2410_udc.h>
55 #include <plat/samsung-time.h>
56
57 #include "common.h"
58 #include "s3c2412-power.h"
59
60 static struct map_desc jive_iodesc[] __initdata = {
61 };
62
63 #define UCON S3C2410_UCON_DEFAULT
64 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
65 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
66
67 static struct s3c2410_uartcfg jive_uartcfgs[] = {
68         [0] = {
69                 .hwport      = 0,
70                 .flags       = 0,
71                 .ucon        = UCON,
72                 .ulcon       = ULCON,
73                 .ufcon       = UFCON,
74         },
75         [1] = {
76                 .hwport      = 1,
77                 .flags       = 0,
78                 .ucon        = UCON,
79                 .ulcon       = ULCON,
80                 .ufcon       = UFCON,
81         },
82         [2] = {
83                 .hwport      = 2,
84                 .flags       = 0,
85                 .ucon        = UCON,
86                 .ulcon       = ULCON,
87                 .ufcon       = UFCON,
88         }
89 };
90
91 /* Jive flash assignment
92  *
93  * 0x00000000-0x00028000 : uboot
94  * 0x00028000-0x0002c000 : uboot env
95  * 0x0002c000-0x00030000 : spare
96  * 0x00030000-0x00200000 : zimage A
97  * 0x00200000-0x01600000 : cramfs A
98  * 0x01600000-0x017d0000 : zimage B
99  * 0x017d0000-0x02bd0000 : cramfs B
100  * 0x02bd0000-0x03fd0000 : yaffs
101  */
102 static struct mtd_partition __initdata jive_imageA_nand_part[] = {
103
104 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
105         /* Don't allow access to the bootloader from linux */
106         {
107                 .name           = "uboot",
108                 .offset         = 0,
109                 .size           = (160 * SZ_1K),
110                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
111         },
112
113         /* spare */
114         {
115                 .name           = "spare",
116                 .offset         = (176 * SZ_1K),
117                 .size           = (16 * SZ_1K),
118         },
119 #endif
120
121         /* booted images */
122         {
123                 .name           = "kernel (ro)",
124                 .offset         = (192 * SZ_1K),
125                 .size           = (SZ_2M) - (192 * SZ_1K),
126                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
127         }, {
128                 .name           = "root (ro)",
129                 .offset         = (SZ_2M),
130                 .size           = (20 * SZ_1M),
131                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
132         },
133
134         /* yaffs */
135         {
136                 .name           = "yaffs",
137                 .offset         = (44 * SZ_1M),
138                 .size           = (20 * SZ_1M),
139         },
140
141         /* bootloader environment */
142         {
143                 .name           = "env",
144                 .offset         = (160 * SZ_1K),
145                 .size           = (16 * SZ_1K),
146         },
147
148         /* upgrade images */
149         {
150                 .name           = "zimage",
151                 .offset         = (22 * SZ_1M),
152                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
153         }, {
154                 .name           = "cramfs",
155                 .offset         = (24 * SZ_1M) - (192*SZ_1K),
156                 .size           = (20 * SZ_1M),
157         },
158 };
159
160 static struct mtd_partition __initdata jive_imageB_nand_part[] = {
161
162 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
163         /* Don't allow access to the bootloader from linux */
164         {
165                 .name           = "uboot",
166                 .offset         = 0,
167                 .size           = (160 * SZ_1K),
168                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
169         },
170
171         /* spare */
172         {
173                 .name           = "spare",
174                 .offset         = (176 * SZ_1K),
175                 .size           = (16 * SZ_1K),
176         },
177 #endif
178
179         /* booted images */
180         {
181                 .name           = "kernel (ro)",
182                 .offset         = (22 * SZ_1M),
183                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
184                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
185         },
186         {
187                 .name           = "root (ro)",
188                 .offset         = (24 * SZ_1M) - (192 * SZ_1K),
189                 .size           = (20 * SZ_1M),
190                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
191         },
192
193         /* yaffs */
194         {
195                 .name           = "yaffs",
196                 .offset         = (44 * SZ_1M),
197                 .size           = (20 * SZ_1M),
198         },
199
200         /* bootloader environment */
201         {
202                 .name           = "env",
203                 .offset         = (160 * SZ_1K),
204                 .size           = (16 * SZ_1K),
205         },
206
207         /* upgrade images */
208         {
209                 .name           = "zimage",
210                 .offset         = (192 * SZ_1K),
211                 .size           = (2 * SZ_1M) - (192 * SZ_1K),
212         }, {
213                 .name           = "cramfs",
214                 .offset         = (2 * SZ_1M),
215                 .size           = (20 * SZ_1M),
216         },
217 };
218
219 static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
220         [0] = {
221                 .name           = "flash",
222                 .nr_chips       = 1,
223                 .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
224                 .partitions     = jive_imageA_nand_part,
225         },
226 };
227
228 static struct s3c2410_platform_nand __initdata jive_nand_info = {
229         /* set taken from osiris nand timings, possibly still conservative */
230         .tacls          = 30,
231         .twrph0         = 55,
232         .twrph1         = 40,
233         .sets           = jive_nand_sets,
234         .nr_sets        = ARRAY_SIZE(jive_nand_sets),
235 };
236
237 static int __init jive_mtdset(char *options)
238 {
239         struct s3c2410_nand_set *nand = &jive_nand_sets[0];
240         unsigned long set;
241
242         if (options == NULL || options[0] == '\0')
243                 return 0;
244
245         if (strict_strtoul(options, 10, &set)) {
246                 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
247                 return 0;
248         }
249
250         switch (set) {
251         case 1:
252                 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
253                 nand->partitions = jive_imageB_nand_part;
254         case 0:
255                 /* this is already setup in the nand info */
256                 break;
257         default:
258                 printk(KERN_ERR "Unknown mtd set %ld specified,"
259                        "using default.", set);
260         }
261
262         return 0;
263 }
264
265 /* parse the mtdset= option given to the kernel command line */
266 __setup("mtdset=", jive_mtdset);
267
268 /* LCD timing and setup */
269
270 #define LCD_XRES         (240)
271 #define LCD_YRES         (320)
272 #define LCD_LEFT_MARGIN  (12)
273 #define LCD_RIGHT_MARGIN (12)
274 #define LCD_LOWER_MARGIN (12)
275 #define LCD_UPPER_MARGIN (12)
276 #define LCD_VSYNC        (2)
277 #define LCD_HSYNC        (2)
278
279 #define LCD_REFRESH      (60)
280
281 #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
282 #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
283
284 static struct s3c2410fb_display jive_vgg2432a4_display[] = {
285         [0] = {
286                 .width          = LCD_XRES,
287                 .height         = LCD_YRES,
288                 .xres           = LCD_XRES,
289                 .yres           = LCD_YRES,
290                 .left_margin    = LCD_LEFT_MARGIN,
291                 .right_margin   = LCD_RIGHT_MARGIN,
292                 .upper_margin   = LCD_UPPER_MARGIN,
293                 .lower_margin   = LCD_LOWER_MARGIN,
294                 .hsync_len      = LCD_HSYNC,
295                 .vsync_len      = LCD_VSYNC,
296
297                 .pixclock       = (1000000000000LL /
298                                    (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
299
300                 .bpp            = 16,
301                 .type           = (S3C2410_LCDCON1_TFT16BPP |
302                                    S3C2410_LCDCON1_TFT),
303
304                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
305                                    S3C2410_LCDCON5_INVVLINE |
306                                    S3C2410_LCDCON5_INVVFRAME |
307                                    S3C2410_LCDCON5_INVVDEN |
308                                    S3C2410_LCDCON5_PWREN),
309         },
310 };
311
312 /* todo - put into gpio header */
313
314 #define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
315 #define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
316
317 static struct s3c2410fb_mach_info jive_lcd_config = {
318         .displays        = jive_vgg2432a4_display,
319         .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
320         .default_display = 0,
321
322         /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
323          * and disable the pull down resistors on pins we are using for LCD
324          * data. */
325
326         .gpcup          = (0xf << 1) | (0x3f << 10),
327
328         .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
329                            S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
330                            S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
331                            S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
332                            S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
333
334         .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
335                            S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
336                            S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
337                            S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
338                            S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
339
340         .gpdup          = (0x3f << 2) | (0x3f << 10),
341
342         .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
343                            S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
344                            S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
345                            S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
346                            S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
347                            S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
348
349         .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
350                            S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
351                            S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
352                            S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
353                            S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
354                            S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
355 };
356
357 /* ILI9320 support. */
358
359 static void jive_lcm_reset(unsigned int set)
360 {
361         printk(KERN_DEBUG "%s(%d)\n", __func__, set);
362
363         gpio_set_value(S3C2410_GPG(13), set);
364 }
365
366 #undef LCD_UPPER_MARGIN
367 #define LCD_UPPER_MARGIN 2
368
369 static struct ili9320_platdata jive_lcm_config = {
370         .hsize          = LCD_XRES,
371         .vsize          = LCD_YRES,
372
373         .reset          = jive_lcm_reset,
374         .suspend        = ILI9320_SUSPEND_DEEP,
375
376         .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
377         .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
378                            ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
379         .display3       = 0x0,
380         .display4       = 0x0,
381         .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
382                            ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
383         .rgb_if2        = ILI9320_RGBIF2_DPL,
384         .interface2     = 0x0,
385         .interface3     = 0x3,
386         .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
387                            ILI9320_INTERFACE4_DIVE(1)),
388         .interface5     = 0x0,
389         .interface6     = 0x0,
390 };
391
392 /* LCD SPI support */
393
394 static struct spi_gpio_platform_data jive_lcd_spi = {
395         .sck            = S3C2410_GPG(8),
396         .mosi           = S3C2410_GPB(8),
397         .miso           = SPI_GPIO_NO_MISO,
398 };
399
400 static struct platform_device jive_device_lcdspi = {
401         .name           = "spi-gpio",
402         .id             = 1,
403         .dev.platform_data = &jive_lcd_spi,
404 };
405
406
407 /* WM8750 audio code SPI definition */
408
409 static struct spi_gpio_platform_data jive_wm8750_spi = {
410         .sck            = S3C2410_GPB(4),
411         .mosi           = S3C2410_GPB(9),
412         .miso           = SPI_GPIO_NO_MISO,
413 };
414
415 static struct platform_device jive_device_wm8750 = {
416         .name           = "spi-gpio",
417         .id             = 2,
418         .dev.platform_data = &jive_wm8750_spi,
419 };
420
421 /* JIVE SPI devices. */
422
423 static struct spi_board_info __initdata jive_spi_devs[] = {
424         [0] = {
425                 .modalias       = "VGG2432A4",
426                 .bus_num        = 1,
427                 .chip_select    = 0,
428                 .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
429                 .max_speed_hz   = 100000,
430                 .platform_data  = &jive_lcm_config,
431                 .controller_data = (void *)S3C2410_GPB(7),
432         }, {
433                 .modalias       = "WM8750",
434                 .bus_num        = 2,
435                 .chip_select    = 0,
436                 .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
437                 .max_speed_hz   = 100000,
438                 .controller_data = (void *)S3C2410_GPH(10),
439         },
440 };
441
442 /* I2C bus and device configuration. */
443
444 static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
445         .frequency      = 80 * 1000,
446         .flags          = S3C_IICFLG_FILTER,
447         .sda_delay      = 2,
448 };
449
450 static struct i2c_board_info jive_i2c_devs[] __initdata = {
451         [0] = {
452                 I2C_BOARD_INFO("lis302dl", 0x1c),
453                 .irq    = IRQ_EINT14,
454         },
455 };
456
457 /* The platform devices being used. */
458
459 static struct platform_device *jive_devices[] __initdata = {
460         &s3c_device_ohci,
461         &s3c_device_rtc,
462         &s3c_device_wdt,
463         &s3c_device_i2c0,
464         &s3c_device_lcd,
465         &jive_device_lcdspi,
466         &jive_device_wm8750,
467         &s3c_device_nand,
468         &s3c_device_usbgadget,
469 };
470
471 static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
472         .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
473 };
474
475 /* Jive power management device */
476
477 #ifdef CONFIG_PM
478 static int jive_pm_suspend(void)
479 {
480         /* Write the magic value u-boot uses to check for resume into
481          * the INFORM0 register, and ensure INFORM1 is set to the
482          * correct address to resume from. */
483
484         __raw_writel(0x2BED, S3C2412_INFORM0);
485         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
486
487         return 0;
488 }
489
490 static void jive_pm_resume(void)
491 {
492         __raw_writel(0x0, S3C2412_INFORM0);
493 }
494
495 #else
496 #define jive_pm_suspend NULL
497 #define jive_pm_resume NULL
498 #endif
499
500 static struct syscore_ops jive_pm_syscore_ops = {
501         .suspend        = jive_pm_suspend,
502         .resume         = jive_pm_resume,
503 };
504
505 static void __init jive_map_io(void)
506 {
507         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
508         s3c24xx_init_clocks(12000000);
509         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
510         samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
511 }
512
513 static void jive_power_off(void)
514 {
515         printk(KERN_INFO "powering system down...\n");
516
517         gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
518         gpio_free(S3C2410_GPC(5));
519 }
520
521 static void __init jive_machine_init(void)
522 {
523         /* register system core operations for managing low level suspend */
524
525         register_syscore_ops(&jive_pm_syscore_ops);
526
527         /* write our sleep configurations for the IO. Pull down all unused
528          * IO, ensure that we have turned off all peripherals we do not
529          * need, and configure the ones we do need. */
530
531         /* Port B sleep */
532
533         __raw_writel(S3C2412_SLPCON_IN(0)   |
534                      S3C2412_SLPCON_PULL(1) |
535                      S3C2412_SLPCON_HIGH(2) |
536                      S3C2412_SLPCON_PULL(3) |
537                      S3C2412_SLPCON_PULL(4) |
538                      S3C2412_SLPCON_PULL(5) |
539                      S3C2412_SLPCON_PULL(6) |
540                      S3C2412_SLPCON_HIGH(7) |
541                      S3C2412_SLPCON_PULL(8) |
542                      S3C2412_SLPCON_PULL(9) |
543                      S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
544
545         /* Port C sleep */
546
547         __raw_writel(S3C2412_SLPCON_PULL(0) |
548                      S3C2412_SLPCON_PULL(1) |
549                      S3C2412_SLPCON_PULL(2) |
550                      S3C2412_SLPCON_PULL(3) |
551                      S3C2412_SLPCON_PULL(4) |
552                      S3C2412_SLPCON_PULL(5) |
553                      S3C2412_SLPCON_LOW(6)  |
554                      S3C2412_SLPCON_PULL(6) |
555                      S3C2412_SLPCON_PULL(7) |
556                      S3C2412_SLPCON_PULL(8) |
557                      S3C2412_SLPCON_PULL(9) |
558                      S3C2412_SLPCON_PULL(10) |
559                      S3C2412_SLPCON_PULL(11) |
560                      S3C2412_SLPCON_PULL(12) |
561                      S3C2412_SLPCON_PULL(13) |
562                      S3C2412_SLPCON_PULL(14) |
563                      S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
564
565         /* Port D sleep */
566
567         __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
568
569         /* Port F sleep */
570
571         __raw_writel(S3C2412_SLPCON_LOW(0)  |
572                      S3C2412_SLPCON_LOW(1)  |
573                      S3C2412_SLPCON_LOW(2)  |
574                      S3C2412_SLPCON_EINT(3) |
575                      S3C2412_SLPCON_EINT(4) |
576                      S3C2412_SLPCON_EINT(5) |
577                      S3C2412_SLPCON_EINT(6) |
578                      S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
579
580         /* Port G sleep */
581
582         __raw_writel(S3C2412_SLPCON_IN(0)    |
583                      S3C2412_SLPCON_IN(1)    |
584                      S3C2412_SLPCON_IN(2)    |
585                      S3C2412_SLPCON_IN(3)    |
586                      S3C2412_SLPCON_IN(4)    |
587                      S3C2412_SLPCON_IN(5)    |
588                      S3C2412_SLPCON_IN(6)    |
589                      S3C2412_SLPCON_IN(7)    |
590                      S3C2412_SLPCON_PULL(8)  |
591                      S3C2412_SLPCON_PULL(9)  |
592                      S3C2412_SLPCON_IN(10)   |
593                      S3C2412_SLPCON_PULL(11) |
594                      S3C2412_SLPCON_PULL(12) |
595                      S3C2412_SLPCON_PULL(13) |
596                      S3C2412_SLPCON_IN(14)   |
597                      S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
598
599         /* Port H sleep */
600
601         __raw_writel(S3C2412_SLPCON_PULL(0) |
602                      S3C2412_SLPCON_PULL(1) |
603                      S3C2412_SLPCON_PULL(2) |
604                      S3C2412_SLPCON_PULL(3) |
605                      S3C2412_SLPCON_PULL(4) |
606                      S3C2412_SLPCON_PULL(5) |
607                      S3C2412_SLPCON_PULL(6) |
608                      S3C2412_SLPCON_IN(7)   |
609                      S3C2412_SLPCON_IN(8)   |
610                      S3C2412_SLPCON_PULL(9) |
611                      S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
612
613         /* initialise the power management now we've setup everything. */
614
615         s3c_pm_init();
616
617         /** TODO - check that this is after the cmdline option! */
618         s3c_nand_set_platdata(&jive_nand_info);
619
620         /* initialise the spi */
621
622         gpio_request(S3C2410_GPG(13), "lcm reset");
623         gpio_direction_output(S3C2410_GPG(13), 0);
624
625         gpio_request(S3C2410_GPB(7), "jive spi");
626         gpio_direction_output(S3C2410_GPB(7), 1);
627
628         gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
629         gpio_free(S3C2410_GPB(6));
630
631         gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
632         gpio_free(S3C2410_GPG(8));
633
634         /* initialise the WM8750 spi */
635
636         gpio_request(S3C2410_GPH(10), "jive wm8750 spi");
637         gpio_direction_output(S3C2410_GPH(10), 1);
638
639         /* Turn off suspend on both USB ports, and switch the
640          * selectable USB port to USB device mode. */
641
642         s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
643                               S3C2410_MISCCR_USBSUSPND0 |
644                               S3C2410_MISCCR_USBSUSPND1, 0x0);
645
646         s3c24xx_udc_set_platdata(&jive_udc_cfg);
647         s3c24xx_fb_set_platdata(&jive_lcd_config);
648
649         spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
650
651         s3c_i2c0_set_platdata(&jive_i2c_cfg);
652         i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
653
654         pm_power_off = jive_power_off;
655
656         platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
657 }
658
659 MACHINE_START(JIVE, "JIVE")
660         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
661         .atag_offset    = 0x100,
662
663         .init_irq       = s3c24xx_init_irq,
664         .map_io         = jive_map_io,
665         .init_machine   = jive_machine_init,
666         .init_time      = samsung_timer_init,
667         .restart        = s3c2412_restart,
668 MACHINE_END