arch/arm/mach-s3c24xx/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright 2003-2008 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dm9000.h>
  24 #include <linux/ata_platform.h>
  25 #include <linux/i2c.h>
  26 #include <linux/io.h>
  27 #include <linux/serial_8250.h>
  28
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/nand_ecc.h>
  32 #include <linux/mtd/partitions.h>
  33
  34 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
  35 #include <linux/platform_data/hwmon-s3c.h>
  36 #include <linux/platform_data/i2c-s3c2410.h>
  37 #include <linux/platform_data/mtd-nand-s3c2410.h>
  38
  39 #include <net/ax88796.h>
  40
  41 #include <asm/irq.h>
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach-types.h>
  46
  47 #include <mach/fb.h>
  48 #include <mach/hardware.h>
  49 #include <mach/regs-gpio.h>
  50 #include <mach/regs-lcd.h>
  51
  52 #include <plat/clock.h>
  53 #include <plat/cpu.h>
  54 #include <plat/cpu-freq.h>
  55 #include <plat/devs.h>
  56 #include <plat/gpio-cfg.h>
  57 #include <plat/regs-serial.h>
  58
  59 #include "bast.h"
  60 #include "common.h"
  61 #include "simtec.h"
  62
  63 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
  64
  65 /* macros for virtual address mods for the io space entries */
  66 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  67 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  68 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  69 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  70
  71 /* macros to modify the physical addresses for io space */
  72
  73 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  74 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  75 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  76 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  77
  78 static struct map_desc bast_iodesc[] __initdata = {
  79   /* ISA IO areas */
  80   {
  81           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  82           .pfn          = PA_CS2(BAST_PA_ISAIO),
  83           .length       = SZ_16M,
  84           .type         = MT_DEVICE,
  85   }, {
  86           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  87           .pfn          = PA_CS3(BAST_PA_ISAIO),
  88           .length       = SZ_16M,
  89           .type         = MT_DEVICE,
  90   },
  91   /* bast CPLD control registers, and external interrupt controls */
  92   {
  93           .virtual      = (u32)BAST_VA_CTRL1,
  94           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
  95           .length       = SZ_1M,
  96           .type         = MT_DEVICE,
  97   }, {
  98           .virtual      = (u32)BAST_VA_CTRL2,
  99           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 100           .length       = SZ_1M,
 101           .type         = MT_DEVICE,
 102   }, {
 103           .virtual      = (u32)BAST_VA_CTRL3,
 104           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 105           .length       = SZ_1M,
 106           .type         = MT_DEVICE,
 107   }, {
 108           .virtual      = (u32)BAST_VA_CTRL4,
 109           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 110           .length       = SZ_1M,
 111           .type         = MT_DEVICE,
 112   },
 113   /* PC104 IRQ mux */
 114   {
 115           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 116           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 117           .length       = SZ_1M,
 118           .type         = MT_DEVICE,
 119   }, {
 120           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 121           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 122           .length       = SZ_1M,
 123           .type         = MT_DEVICE,
 124   }, {
 125           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 126           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 127           .length       = SZ_1M,
 128           .type         = MT_DEVICE,
 129   },
 130
 131   /* peripheral space... one for each of fast/slow/byte/16bit */
 132   /* note, ide is only decoded in word space, even though some registers
 133    * are only 8bit */
 134
 135   /* slow, byte */
 136   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 137   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 138   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 139
 140   /* slow, word */
 141   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 142   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 143   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 144
 145   /* fast, byte */
 146   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 147   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 148   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 149
 150   /* fast, word */
 151   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 152   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 153   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 154 };
 155
 156 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 157 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 158 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 159
 160 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 161         [0] = {
 162                 .hwport      = 0,
 163                 .flags       = 0,
 164                 .ucon        = UCON,
 165                 .ulcon       = ULCON,
 166                 .ufcon       = UFCON,
 167         },
 168         [1] = {
 169                 .hwport      = 1,
 170                 .flags       = 0,
 171                 .ucon        = UCON,
 172                 .ulcon       = ULCON,
 173                 .ufcon       = UFCON,
 174         },
 175         /* port 2 is not actually used */
 176         [2] = {
 177                 .hwport      = 2,
 178                 .flags       = 0,
 179                 .ucon        = UCON,
 180                 .ulcon       = ULCON,
 181                 .ufcon       = UFCON,
 182         }
 183 };
 184
 185 /* NAND Flash on BAST board */
 186
 187 #ifdef CONFIG_PM
 188 static int bast_pm_suspend(void)
 189 {
 190         /* ensure that an nRESET is not generated on resume. */
 191         gpio_direction_output(S3C2410_GPA(21), 1);
 192         return 0;
 193 }
 194
 195 static void bast_pm_resume(void)
 196 {
 197         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 198 }
 199
 200 #else
 201 #define bast_pm_suspend NULL
 202 #define bast_pm_resume NULL
 203 #endif
 204
 205 static struct syscore_ops bast_pm_syscore_ops = {
 206         .suspend        = bast_pm_suspend,
 207         .resume         = bast_pm_resume,
 208 };
 209
 210 static int smartmedia_map[] = { 0 };
 211 static int chip0_map[] = { 1 };
 212 static int chip1_map[] = { 2 };
 213 static int chip2_map[] = { 3 };
 214
 215 static struct mtd_partition __initdata bast_default_nand_part[] = {
 216         [0] = {
 217                 .name   = "Boot Agent",
 218                 .size   = SZ_16K,
 219                 .offset = 0,
 220         },
 221         [1] = {
 222                 .name   = "/boot",
 223                 .size   = SZ_4M - SZ_16K,
 224                 .offset = SZ_16K,
 225         },
 226         [2] = {
 227                 .name   = "user",
 228                 .offset = SZ_4M,
 229                 .size   = MTDPART_SIZ_FULL,
 230         }
 231 };
 232
 233 /* the bast has 4 selectable slots for nand-flash, the three
 234  * on-board chip areas, as well as the external SmartMedia
 235  * slot.
 236  *
 237  * Note, there is no current hot-plug support for the SmartMedia
 238  * socket.
 239 */
 240
 241 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
 242         [0] = {
 243                 .name           = "SmartMedia",
 244                 .nr_chips       = 1,
 245                 .nr_map         = smartmedia_map,
 246                 .options        = NAND_SCAN_SILENT_NODEV,
 247                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 248                 .partitions     = bast_default_nand_part,
 249         },
 250         [1] = {
 251                 .name           = "chip0",
 252                 .nr_chips       = 1,
 253                 .nr_map         = chip0_map,
 254                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 255                 .partitions     = bast_default_nand_part,
 256         },
 257         [2] = {
 258                 .name           = "chip1",
 259                 .nr_chips       = 1,
 260                 .nr_map         = chip1_map,
 261                 .options        = NAND_SCAN_SILENT_NODEV,
 262                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 263                 .partitions     = bast_default_nand_part,
 264         },
 265         [3] = {
 266                 .name           = "chip2",
 267                 .nr_chips       = 1,
 268                 .nr_map         = chip2_map,
 269                 .options        = NAND_SCAN_SILENT_NODEV,
 270                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 271                 .partitions     = bast_default_nand_part,
 272         }
 273 };
 274
 275 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 276 {
 277         unsigned int tmp;
 278
 279         slot = set->nr_map[slot] & 3;
 280
 281         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 282                  slot, set, set->nr_map);
 283
 284         tmp = __raw_readb(BAST_VA_CTRL2);
 285         tmp &= BAST_CPLD_CTLR2_IDERST;
 286         tmp |= slot;
 287         tmp |= BAST_CPLD_CTRL2_WNAND;
 288
 289         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 290
 291         __raw_writeb(tmp, BAST_VA_CTRL2);
 292 }
 293
 294 static struct s3c2410_platform_nand __initdata bast_nand_info = {
 295         .tacls          = 30,
 296         .twrph0         = 60,
 297         .twrph1         = 60,
 298         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 299         .sets           = bast_nand_sets,
 300         .select_chip    = bast_nand_select,
 301 };
 302
 303 /* DM9000 */
 304
 305 static struct resource bast_dm9k_resource[] = {
 306         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
 307         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
 308         [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
 309                                         | IORESOURCE_IRQ_HIGHLEVEL),
 310 };
 311
 312 /* for the moment we limit ourselves to 16bit IO until some
 313  * better IO routines can be written and tested
 314 */
 315
 316 static struct dm9000_plat_data bast_dm9k_platdata = {
 317         .flags          = DM9000_PLATF_16BITONLY,
 318 };
 319
 320 static struct platform_device bast_device_dm9k = {
 321         .name           = "dm9000",
 322         .id             = 0,
 323         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 324         .resource       = bast_dm9k_resource,
 325         .dev            = {
 326                 .platform_data = &bast_dm9k_platdata,
 327         }
 328 };
 329
 330 /* serial devices */
 331
 332 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 333 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 334 #define SERIAL_CLK   (1843200)
 335
 336 static struct plat_serial8250_port bast_sio_data[] = {
 337         [0] = {
 338                 .mapbase        = SERIAL_BASE + 0x2f8,
 339                 .irq            = BAST_IRQ_PCSERIAL1,
 340                 .flags          = SERIAL_FLAGS,
 341                 .iotype         = UPIO_MEM,
 342                 .regshift       = 0,
 343                 .uartclk        = SERIAL_CLK,
 344         },
 345         [1] = {
 346                 .mapbase        = SERIAL_BASE + 0x3f8,
 347                 .irq            = BAST_IRQ_PCSERIAL2,
 348                 .flags          = SERIAL_FLAGS,
 349                 .iotype         = UPIO_MEM,
 350                 .regshift       = 0,
 351                 .uartclk        = SERIAL_CLK,
 352         },
 353         { }
 354 };
 355
 356 static struct platform_device bast_sio = {
 357         .name                   = "serial8250",
 358         .id                     = PLAT8250_DEV_PLATFORM,
 359         .dev                    = {
 360                 .platform_data  = &bast_sio_data,
 361         },
 362 };
 363
 364 /* we have devices on the bus which cannot work much over the
 365  * standard 100KHz i2c bus frequency
 366 */
 367
 368 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 369         .flags          = 0,
 370         .slave_addr     = 0x10,
 371         .frequency      = 100*1000,
 372 };
 373
 374 /* Asix AX88796 10/100 ethernet controller */
 375
 376 static struct ax_plat_data bast_asix_platdata = {
 377         .flags          = AXFLG_MAC_FROMDEV,
 378         .wordlength     = 2,
 379         .dcr_val        = 0x48,
 380         .rcr_val        = 0x40,
 381 };
 382
 383 static struct resource bast_asix_resource[] = {
 384         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
 385         [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
 386         [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
 387 };
 388
 389 static struct platform_device bast_device_asix = {
 390         .name           = "ax88796",
 391         .id             = 0,
 392         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 393         .resource       = bast_asix_resource,
 394         .dev            = {
 395                 .platform_data = &bast_asix_platdata
 396         }
 397 };
 398
 399 /* Asix AX88796 10/100 ethernet controller parallel port */
 400
 401 static struct resource bast_asixpp_resource[] = {
 402         [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
 403                                         0x30 * 0x20),
 404 };
 405
 406 static struct platform_device bast_device_axpp = {
 407         .name           = "ax88796-pp",
 408         .id             = 0,
 409         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 410         .resource       = bast_asixpp_resource,
 411 };
 412
 413 /* LCD/VGA controller */
 414
 415 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 416         {
 417                 .type           = S3C2410_LCDCON1_TFT,
 418                 .width          = 640,
 419                 .height         = 480,
 420
 421                 .pixclock       = 33333,
 422                 .xres           = 640,
 423                 .yres           = 480,
 424                 .bpp            = 4,
 425                 .left_margin    = 40,
 426                 .right_margin   = 20,
 427                 .hsync_len      = 88,
 428                 .upper_margin   = 30,
 429                 .lower_margin   = 32,
 430                 .vsync_len      = 3,
 431
 432                 .lcdcon5        = 0x00014b02,
 433         },
 434         {
 435                 .type           = S3C2410_LCDCON1_TFT,
 436                 .width          = 640,
 437                 .height         = 480,
 438
 439                 .pixclock       = 33333,
 440                 .xres           = 640,
 441                 .yres           = 480,
 442                 .bpp            = 8,
 443                 .left_margin    = 40,
 444                 .right_margin   = 20,
 445                 .hsync_len      = 88,
 446                 .upper_margin   = 30,
 447                 .lower_margin   = 32,
 448                 .vsync_len      = 3,
 449
 450                 .lcdcon5        = 0x00014b02,
 451         },
 452         {
 453                 .type           = S3C2410_LCDCON1_TFT,
 454                 .width          = 640,
 455                 .height         = 480,
 456
 457                 .pixclock       = 33333,
 458                 .xres           = 640,
 459                 .yres           = 480,
 460                 .bpp            = 16,
 461                 .left_margin    = 40,
 462                 .right_margin   = 20,
 463                 .hsync_len      = 88,
 464                 .upper_margin   = 30,
 465                 .lower_margin   = 32,
 466                 .vsync_len      = 3,
 467
 468                 .lcdcon5        = 0x00014b02,
 469         },
 470 };
 471
 472 /* LCD/VGA controller */
 473
 474 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 475
 476         .displays = bast_lcd_info,
 477         .num_displays = ARRAY_SIZE(bast_lcd_info),
 478         .default_display = 1,
 479 };
 480
 481 /* I2C devices fitted. */
 482
 483 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 484         {
 485                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 486         }, {
 487                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 488         }, {
 489                 I2C_BOARD_INFO("ch7013", 0x75),
 490         },
 491 };
 492
 493 static struct s3c_hwmon_pdata bast_hwmon_info = {
 494         /* LCD contrast (0-6.6V) */
 495         .in[0] = &(struct s3c_hwmon_chcfg) {
 496                 .name           = "lcd-contrast",
 497                 .mult           = 3300,
 498                 .div            = 512,
 499         },
 500         /* LED current feedback */
 501         .in[1] = &(struct s3c_hwmon_chcfg) {
 502                 .name           = "led-feedback",
 503                 .mult           = 3300,
 504                 .div            = 1024,
 505         },
 506         /* LCD feedback (0-6.6V) */
 507         .in[2] = &(struct s3c_hwmon_chcfg) {
 508                 .name           = "lcd-feedback",
 509                 .mult           = 3300,
 510                 .div            = 512,
 511         },
 512         /* Vcore (1.8-2.0V), Vref 3.3V  */
 513         .in[3] = &(struct s3c_hwmon_chcfg) {
 514                 .name           = "vcore",
 515                 .mult           = 3300,
 516                 .div            = 1024,
 517         },
 518 };
 519
 520 /* Standard BAST devices */
 521 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 522
 523 static struct platform_device *bast_devices[] __initdata = {
 524         &s3c_device_ohci,
 525         &s3c_device_lcd,
 526         &s3c_device_wdt,
 527         &s3c_device_i2c0,
 528         &s3c_device_rtc,
 529         &s3c_device_nand,
 530         &s3c_device_adc,
 531         &s3c_device_hwmon,
 532         &bast_device_dm9k,
 533         &bast_device_asix,
 534         &bast_device_axpp,
 535         &bast_sio,
 536 };
 537
 538 static struct clk *bast_clocks[] __initdata = {
 539         &s3c24xx_dclk0,
 540         &s3c24xx_dclk1,
 541         &s3c24xx_clkout0,
 542         &s3c24xx_clkout1,
 543         &s3c24xx_uclk,
 544 };
 545
 546 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 547         .refresh        = 7800, /* 7.8usec */
 548         .auto_io        = 1,
 549         .need_io        = 1,
 550 };
 551
 552 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 553         .have_mic       = 1,
 554         .have_lout      = 1,
 555 };
 556
 557 static void __init bast_map_io(void)
 558 {
 559         /* initialise the clocks */
 560
 561         s3c24xx_dclk0.parent = &clk_upll;
 562         s3c24xx_dclk0.rate   = 12*1000*1000;
 563
 564         s3c24xx_dclk1.parent = &clk_upll;
 565         s3c24xx_dclk1.rate   = 24*1000*1000;
 566
 567         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 568         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 569
 570         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 571
 572         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 573
 574         s3c_hwmon_set_platdata(&bast_hwmon_info);
 575
 576         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 577         s3c24xx_init_clocks(0);
 578         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 579 }
 580
 581 static void __init bast_init(void)
 582 {
 583         register_syscore_ops(&bast_pm_syscore_ops);
 584
 585         s3c_i2c0_set_platdata(&bast_i2c_info);
 586         s3c_nand_set_platdata(&bast_nand_info);
 587         s3c24xx_fb_set_platdata(&bast_fb_info);
 588         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 589
 590         i2c_register_board_info(0, bast_i2c_devs,
 591                                 ARRAY_SIZE(bast_i2c_devs));
 592
 593         usb_simtec_init();
 594         nor_simtec_init();
 595         simtec_audio_add(NULL, true, &bast_audio);
 596
 597         WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
 598
 599         s3c_cpufreq_setboard(&bast_cpufreq);
 600 }
 601
 602 MACHINE_START(BAST, "Simtec-BAST")
 603         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 604         .atag_offset    = 0x100,
 605         .map_io         = bast_map_io,
 606         .init_irq       = s3c24xx_init_irq,
 607         .init_machine   = bast_init,
 608         .init_time      = s3c24xx_timer_init,
 609         .restart        = s3c2410_restart,
 610 MACHINE_END