arch/arm/mach-s3c24xx/clock-s3c2412.c

   1 /* linux/arch/arm/mach-s3c2412/clock.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2412,S3C2413 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/device.h>
  30 #include <linux/clk.h>
  31 #include <linux/mutex.h>
  32 #include <linux/delay.h>
  33 #include <linux/serial_core.h>
  34 #include <linux/serial_s3c.h>
  35 #include <linux/io.h>
  36
  37 #include <asm/mach/map.h>
  38
  39 #include <mach/hardware.h>
  40 #include <mach/regs-clock.h>
  41 #include <mach/regs-gpio.h>
  42
  43 #include <plat/clock.h>
  44 #include <plat/cpu.h>
  45
  46 /* We currently have to assume that the system is running
  47  * from the XTPll input, and that all ***REFCLKs are being
  48  * fed from it, as we cannot read the state of OM[4] from
  49  * software.
  50  *
  51  * It would be possible for each board initialisation to
  52  * set the correct muxing at initialisation
  53 */
  54
  55 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
  56 {
  57         unsigned int clocks = clk->ctrlbit;
  58         unsigned long clkcon;
  59
  60         clkcon = __raw_readl(S3C2410_CLKCON);
  61
  62         if (enable)
  63                 clkcon |= clocks;
  64         else
  65                 clkcon &= ~clocks;
  66
  67         __raw_writel(clkcon, S3C2410_CLKCON);
  68
  69         return 0;
  70 }
  71
  72 static int s3c2412_upll_enable(struct clk *clk, int enable)
  73 {
  74         unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
  75         unsigned long orig = upllcon;
  76
  77         if (!enable)
  78                 upllcon |= S3C2412_PLLCON_OFF;
  79         else
  80                 upllcon &= ~S3C2412_PLLCON_OFF;
  81
  82         __raw_writel(upllcon, S3C2410_UPLLCON);
  83
  84         /* allow ~150uS for the PLL to settle and lock */
  85
  86         if (enable && (orig & S3C2412_PLLCON_OFF))
  87                 udelay(150);
  88
  89         return 0;
  90 }
  91
  92 /* clock selections */
  93
  94 static struct clk clk_erefclk = {
  95         .name           = "erefclk",
  96 };
  97
  98 static struct clk clk_urefclk = {
  99         .name           = "urefclk",
 100 };
 101
 102 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
 103 {
 104         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 105
 106         if (parent == &clk_urefclk)
 107                 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
 108         else if (parent == &clk_upll)
 109                 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
 110         else
 111                 return -EINVAL;
 112
 113         clk->parent = parent;
 114
 115         __raw_writel(clksrc, S3C2412_CLKSRC);
 116         return 0;
 117 }
 118
 119 static struct clk clk_usysclk = {
 120         .name           = "usysclk",
 121         .parent         = &clk_xtal,
 122         .ops            = &(struct clk_ops) {
 123                 .set_parent     = s3c2412_setparent_usysclk,
 124         },
 125 };
 126
 127 static struct clk clk_mrefclk = {
 128         .name           = "mrefclk",
 129         .parent         = &clk_xtal,
 130 };
 131
 132 static struct clk clk_mdivclk = {
 133         .name           = "mdivclk",
 134         .parent         = &clk_xtal,
 135 };
 136
 137 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
 138 {
 139         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 140
 141         if (parent == &clk_usysclk)
 142                 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
 143         else if (parent == &clk_h)
 144                 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
 145         else
 146                 return -EINVAL;
 147
 148         clk->parent = parent;
 149
 150         __raw_writel(clksrc, S3C2412_CLKSRC);
 151         return 0;
 152 }
 153
 154 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
 155                                               unsigned long rate)
 156 {
 157         unsigned long parent_rate = clk_get_rate(clk->parent);
 158         int div;
 159
 160         if (rate > parent_rate)
 161                 return parent_rate;
 162
 163         div = parent_rate / rate;
 164         if (div > 2)
 165                 div = 2;
 166
 167         return parent_rate / div;
 168 }
 169
 170 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
 171 {
 172         unsigned long parent_rate = clk_get_rate(clk->parent);
 173         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 174
 175         return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
 176 }
 177
 178 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
 179 {
 180         unsigned long parent_rate = clk_get_rate(clk->parent);
 181         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 182
 183         rate = s3c2412_roundrate_usbsrc(clk, rate);
 184
 185         if ((parent_rate / rate) == 2)
 186                 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
 187         else
 188                 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
 189
 190         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 191         return 0;
 192 }
 193
 194 static struct clk clk_usbsrc = {
 195         .name           = "usbsrc",
 196         .ops            = &(struct clk_ops) {
 197                 .get_rate       = s3c2412_getrate_usbsrc,
 198                 .set_rate       = s3c2412_setrate_usbsrc,
 199                 .round_rate     = s3c2412_roundrate_usbsrc,
 200                 .set_parent     = s3c2412_setparent_usbsrc,
 201         },
 202 };
 203
 204 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
 205 {
 206         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 207
 208         if (parent == &clk_mdivclk)
 209                 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
 210         else if (parent == &clk_mpll)
 211                 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
 212         else
 213                 return -EINVAL;
 214
 215         clk->parent = parent;
 216
 217         __raw_writel(clksrc, S3C2412_CLKSRC);
 218         return 0;
 219 }
 220
 221 static struct clk clk_msysclk = {
 222         .name           = "msysclk",
 223         .ops            = &(struct clk_ops) {
 224                 .set_parent     = s3c2412_setparent_msysclk,
 225         },
 226 };
 227
 228 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
 229 {
 230         unsigned long flags;
 231         unsigned long clkdiv;
 232         unsigned long dvs;
 233
 234         /* Note, we current equate fclk andf msysclk for S3C2412 */
 235
 236         if (parent == &clk_msysclk || parent == &clk_f)
 237                 dvs = 0;
 238         else if (parent == &clk_h)
 239                 dvs = S3C2412_CLKDIVN_DVSEN;
 240         else
 241                 return -EINVAL;
 242
 243         clk->parent = parent;
 244
 245         /* update this under irq lockdown, clkdivn is not protected
 246          * by the clock system. */
 247
 248         local_irq_save(flags);
 249
 250         clkdiv  = __raw_readl(S3C2410_CLKDIVN);
 251         clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
 252         clkdiv |= dvs;
 253         __raw_writel(clkdiv, S3C2410_CLKDIVN);
 254
 255         local_irq_restore(flags);
 256
 257         return 0;
 258 }
 259
 260 static struct clk clk_armclk = {
 261         .name           = "armclk",
 262         .parent         = &clk_msysclk,
 263         .ops            = &(struct clk_ops) {
 264                 .set_parent     = s3c2412_setparent_armclk,
 265         },
 266 };
 267
 268 /* these next clocks have an divider immediately after them,
 269  * so we can register them with their divider and leave out the
 270  * intermediate clock stage
 271 */
 272 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
 273                                               unsigned long rate)
 274 {
 275         unsigned long parent_rate = clk_get_rate(clk->parent);
 276         int div;
 277
 278         if (rate > parent_rate)
 279                 return parent_rate;
 280
 281         /* note, we remove the +/- 1 calculations as they cancel out */
 282
 283         div = (rate / parent_rate);
 284
 285         if (div < 1)
 286                 div = 1;
 287         else if (div > 16)
 288                 div = 16;
 289
 290         return parent_rate / div;
 291 }
 292
 293 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
 294 {
 295         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 296
 297         if (parent == &clk_erefclk)
 298                 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
 299         else if (parent == &clk_mpll)
 300                 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
 301         else
 302                 return -EINVAL;
 303
 304         clk->parent = parent;
 305
 306         __raw_writel(clksrc, S3C2412_CLKSRC);
 307         return 0;
 308 }
 309
 310 static unsigned long s3c2412_getrate_uart(struct clk *clk)
 311 {
 312         unsigned long parent_rate = clk_get_rate(clk->parent);
 313         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 314
 315         div &= S3C2412_CLKDIVN_UARTDIV_MASK;
 316         div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
 317
 318         return parent_rate / (div + 1);
 319 }
 320
 321 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
 322 {
 323         unsigned long parent_rate = clk_get_rate(clk->parent);
 324         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 325
 326         rate = s3c2412_roundrate_clksrc(clk, rate);
 327
 328         clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
 329         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
 330
 331         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 332         return 0;
 333 }
 334
 335 static struct clk clk_uart = {
 336         .name           = "uartclk",
 337         .ops            = &(struct clk_ops) {
 338                 .get_rate       = s3c2412_getrate_uart,
 339                 .set_rate       = s3c2412_setrate_uart,
 340                 .set_parent     = s3c2412_setparent_uart,
 341                 .round_rate     = s3c2412_roundrate_clksrc,
 342         },
 343 };
 344
 345 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
 346 {
 347         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 348
 349         if (parent == &clk_erefclk)
 350                 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
 351         else if (parent == &clk_mpll)
 352                 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
 353         else
 354                 return -EINVAL;
 355
 356         clk->parent = parent;
 357
 358         __raw_writel(clksrc, S3C2412_CLKSRC);
 359         return 0;
 360 }
 361
 362 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
 363 {
 364         unsigned long parent_rate = clk_get_rate(clk->parent);
 365         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 366
 367         div &= S3C2412_CLKDIVN_I2SDIV_MASK;
 368         div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
 369
 370         return parent_rate / (div + 1);
 371 }
 372
 373 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
 374 {
 375         unsigned long parent_rate = clk_get_rate(clk->parent);
 376         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 377
 378         rate = s3c2412_roundrate_clksrc(clk, rate);
 379
 380         clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
 381         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
 382
 383         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 384         return 0;
 385 }
 386
 387 static struct clk clk_i2s = {
 388         .name           = "i2sclk",
 389         .ops            = &(struct clk_ops) {
 390                 .get_rate       = s3c2412_getrate_i2s,
 391                 .set_rate       = s3c2412_setrate_i2s,
 392                 .set_parent     = s3c2412_setparent_i2s,
 393                 .round_rate     = s3c2412_roundrate_clksrc,
 394         },
 395 };
 396
 397 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
 398 {
 399         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 400
 401         if (parent == &clk_usysclk)
 402                 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
 403         else if (parent == &clk_h)
 404                 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
 405         else
 406                 return -EINVAL;
 407
 408         clk->parent = parent;
 409
 410         __raw_writel(clksrc, S3C2412_CLKSRC);
 411         return 0;
 412 }
 413 static unsigned long s3c2412_getrate_cam(struct clk *clk)
 414 {
 415         unsigned long parent_rate = clk_get_rate(clk->parent);
 416         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
 417
 418         div &= S3C2412_CLKDIVN_CAMDIV_MASK;
 419         div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
 420
 421         return parent_rate / (div + 1);
 422 }
 423
 424 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
 425 {
 426         unsigned long parent_rate = clk_get_rate(clk->parent);
 427         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
 428
 429         rate = s3c2412_roundrate_clksrc(clk, rate);
 430
 431         clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
 432         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
 433
 434         __raw_writel(clkdivn, S3C2410_CLKDIVN);
 435         return 0;
 436 }
 437
 438 static struct clk clk_cam = {
 439         .name           = "camif-upll", /* same as 2440 name */
 440         .ops            = &(struct clk_ops) {
 441                 .get_rate       = s3c2412_getrate_cam,
 442                 .set_rate       = s3c2412_setrate_cam,
 443                 .set_parent     = s3c2412_setparent_cam,
 444                 .round_rate     = s3c2412_roundrate_clksrc,
 445         },
 446 };
 447
 448 /* standard clock definitions */
 449
 450 static struct clk init_clocks_disable[] = {
 451         {
 452                 .name           = "nand",
 453                 .parent         = &clk_h,
 454                 .enable         = s3c2412_clkcon_enable,
 455                 .ctrlbit        = S3C2412_CLKCON_NAND,
 456         }, {
 457                 .name           = "sdi",
 458                 .parent         = &clk_p,
 459                 .enable         = s3c2412_clkcon_enable,
 460                 .ctrlbit        = S3C2412_CLKCON_SDI,
 461         }, {
 462                 .name           = "adc",
 463                 .parent         = &clk_p,
 464                 .enable         = s3c2412_clkcon_enable,
 465                 .ctrlbit        = S3C2412_CLKCON_ADC,
 466         }, {
 467                 .name           = "i2c",
 468                 .parent         = &clk_p,
 469                 .enable         = s3c2412_clkcon_enable,
 470                 .ctrlbit        = S3C2412_CLKCON_IIC,
 471         }, {
 472                 .name           = "iis",
 473                 .parent         = &clk_p,
 474                 .enable         = s3c2412_clkcon_enable,
 475                 .ctrlbit        = S3C2412_CLKCON_IIS,
 476         }, {
 477                 .name           = "spi",
 478                 .parent         = &clk_p,
 479                 .enable         = s3c2412_clkcon_enable,
 480                 .ctrlbit        = S3C2412_CLKCON_SPI,
 481         }
 482 };
 483
 484 static struct clk init_clocks[] = {
 485         {
 486                 .name           = "dma.0",
 487                 .parent         = &clk_h,
 488                 .enable         = s3c2412_clkcon_enable,
 489                 .ctrlbit        = S3C2412_CLKCON_DMA0,
 490         }, {
 491                 .name           = "dma.1",
 492                 .parent         = &clk_h,
 493                 .enable         = s3c2412_clkcon_enable,
 494                 .ctrlbit        = S3C2412_CLKCON_DMA1,
 495         }, {
 496                 .name           = "dma.2",
 497                 .parent         = &clk_h,
 498                 .enable         = s3c2412_clkcon_enable,
 499                 .ctrlbit        = S3C2412_CLKCON_DMA2,
 500         }, {
 501                 .name           = "dma.3",
 502                 .parent         = &clk_h,
 503                 .enable         = s3c2412_clkcon_enable,
 504                 .ctrlbit        = S3C2412_CLKCON_DMA3,
 505         }, {
 506                 .name           = "lcd",
 507                 .parent         = &clk_h,
 508                 .enable         = s3c2412_clkcon_enable,
 509                 .ctrlbit        = S3C2412_CLKCON_LCDC,
 510         }, {
 511                 .name           = "gpio",
 512                 .parent         = &clk_p,
 513                 .enable         = s3c2412_clkcon_enable,
 514                 .ctrlbit        = S3C2412_CLKCON_GPIO,
 515         }, {
 516                 .name           = "usb-host",
 517                 .parent         = &clk_h,
 518                 .enable         = s3c2412_clkcon_enable,
 519                 .ctrlbit        = S3C2412_CLKCON_USBH,
 520         }, {
 521                 .name           = "usb-device",
 522                 .parent         = &clk_h,
 523                 .enable         = s3c2412_clkcon_enable,
 524                 .ctrlbit        = S3C2412_CLKCON_USBD,
 525         }, {
 526                 .name           = "timers",
 527                 .parent         = &clk_p,
 528                 .enable         = s3c2412_clkcon_enable,
 529                 .ctrlbit        = S3C2412_CLKCON_PWMT,
 530         }, {
 531                 .name           = "uart",
 532                 .devname        = "s3c2412-uart.0",
 533                 .parent         = &clk_p,
 534                 .enable         = s3c2412_clkcon_enable,
 535                 .ctrlbit        = S3C2412_CLKCON_UART0,
 536         }, {
 537                 .name           = "uart",
 538                 .devname        = "s3c2412-uart.1",
 539                 .parent         = &clk_p,
 540                 .enable         = s3c2412_clkcon_enable,
 541                 .ctrlbit        = S3C2412_CLKCON_UART1,
 542         }, {
 543                 .name           = "uart",
 544                 .devname        = "s3c2412-uart.2",
 545                 .parent         = &clk_p,
 546                 .enable         = s3c2412_clkcon_enable,
 547                 .ctrlbit        = S3C2412_CLKCON_UART2,
 548         }, {
 549                 .name           = "rtc",
 550                 .parent         = &clk_p,
 551                 .enable         = s3c2412_clkcon_enable,
 552                 .ctrlbit        = S3C2412_CLKCON_RTC,
 553         }, {
 554                 .name           = "watchdog",
 555                 .parent         = &clk_p,
 556                 .ctrlbit        = 0,
 557         }, {
 558                 .name           = "usb-bus-gadget",
 559                 .parent         = &clk_usb_bus,
 560                 .enable         = s3c2412_clkcon_enable,
 561                 .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
 562         }, {
 563                 .name           = "usb-bus-host",
 564                 .parent         = &clk_usb_bus,
 565                 .enable         = s3c2412_clkcon_enable,
 566                 .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
 567         }
 568 };
 569
 570 /* clocks to add where we need to check their parentage */
 571
 572 struct clk_init {
 573         struct clk      *clk;
 574         unsigned int     bit;
 575         struct clk      *src_0;
 576         struct clk      *src_1;
 577 };
 578
 579 static struct clk_init clks_src[] __initdata = {
 580         {
 581                 .clk    = &clk_usysclk,
 582                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
 583                 .src_0  = &clk_urefclk,
 584                 .src_1  = &clk_upll,
 585         }, {
 586                 .clk    = &clk_i2s,
 587                 .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
 588                 .src_0  = &clk_erefclk,
 589                 .src_1  = &clk_mpll,
 590         }, {
 591                 .clk    = &clk_cam,
 592                 .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
 593                 .src_0  = &clk_usysclk,
 594                 .src_1  = &clk_h,
 595         }, {
 596                 .clk    = &clk_msysclk,
 597                 .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
 598                 .src_0  = &clk_mdivclk,
 599                 .src_1  = &clk_mpll,
 600         }, {
 601                 .clk    = &clk_uart,
 602                 .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
 603                 .src_0  = &clk_erefclk,
 604                 .src_1  = &clk_mpll,
 605         }, {
 606                 .clk    = &clk_usbsrc,
 607                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
 608                 .src_0  = &clk_usysclk,
 609                 .src_1  = &clk_h,
 610         /* here we assume  OM[4] select xtal */
 611         }, {
 612                 .clk    = &clk_erefclk,
 613                 .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
 614                 .src_0  = &clk_xtal,
 615                 .src_1  = &clk_ext,
 616         }, {
 617                 .clk    = &clk_urefclk,
 618                 .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
 619                 .src_0  = &clk_xtal,
 620                 .src_1  = &clk_ext,
 621         },
 622 };
 623
 624 /* s3c2412_clk_initparents
 625  *
 626  * Initialise the parents for the clocks that we get at start-time
 627 */
 628
 629 static void __init s3c2412_clk_initparents(void)
 630 {
 631         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
 632         struct clk_init *cip = clks_src;
 633         struct clk *src;
 634         int ptr;
 635         int ret;
 636
 637         for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
 638                 ret = s3c24xx_register_clock(cip->clk);
 639                 if (ret < 0) {
 640                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 641                                cip->clk->name, ret);
 642                 }
 643
 644                 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
 645
 646                 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
 647                 clk_set_parent(cip->clk, src);
 648         }
 649 }
 650
 651 /* clocks to add straight away */
 652
 653 static struct clk *clks[] __initdata = {
 654         &clk_ext,
 655         &clk_usb_bus,
 656         &clk_mrefclk,
 657         &clk_armclk,
 658 };
 659
 660 static struct clk_lookup s3c2412_clk_lookup[] = {
 661         CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
 662         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 663         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
 664 };
 665
 666 int __init s3c2412_baseclk_add(void)
 667 {
 668         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
 669         unsigned int dvs;
 670         struct clk *clkp;
 671         int ret;
 672         int ptr;
 673
 674         clk_upll.enable = s3c2412_upll_enable;
 675         clk_usb_bus.parent = &clk_usbsrc;
 676         clk_usb_bus.rate = 0x0;
 677
 678         clk_f.parent = &clk_msysclk;
 679
 680         s3c2412_clk_initparents();
 681
 682         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
 683                 clkp = clks[ptr];
 684
 685                 ret = s3c24xx_register_clock(clkp);
 686                 if (ret < 0) {
 687                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 688                                clkp->name, ret);
 689                 }
 690         }
 691
 692         /* set the dvs state according to what we got at boot time */
 693
 694         dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
 695
 696         if (dvs)
 697                 clk_armclk.parent = &clk_h;
 698
 699         printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
 700
 701         /* ensure usb bus clock is within correct rate of 48MHz */
 702
 703         if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
 704                 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
 705
 706                 /* for the moment, let's use the UPLL, and see if we can
 707                  * get 48MHz */
 708
 709                 clk_set_parent(&clk_usysclk, &clk_upll);
 710                 clk_set_parent(&clk_usbsrc, &clk_usysclk);
 711                 clk_set_rate(&clk_usbsrc, 48*1000*1000);
 712         }
 713
 714         printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
 715                (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
 716                print_mhz(clk_get_rate(&clk_upll)),
 717                print_mhz(clk_get_rate(&clk_usb_bus)));
 718
 719         /* register clocks from clock array */
 720
 721         clkp = init_clocks;
 722         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 723                 /* ensure that we note the clock state */
 724
 725                 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
 726
 727                 ret = s3c24xx_register_clock(clkp);
 728                 if (ret < 0) {
 729                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 730                                clkp->name, ret);
 731                 }
 732         }
 733
 734         /* We must be careful disabling the clocks we are not intending to
 735          * be using at boot time, as subsystems such as the LCD which do
 736          * their own DMA requests to the bus can cause the system to lockup
 737          * if they where in the middle of requesting bus access.
 738          *
 739          * Disabling the LCD clock if the LCD is active is very dangerous,
 740          * and therefore the bootloader should be careful to not enable
 741          * the LCD clock if it is not needed.
 742         */
 743
 744         /* install (and disable) the clocks we do not need immediately */
 745
 746         clkp = init_clocks_disable;
 747         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 748
 749                 ret = s3c24xx_register_clock(clkp);
 750                 if (ret < 0) {
 751                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 752                                clkp->name, ret);
 753                 }
 754
 755                 s3c2412_clkcon_enable(clkp, 0);
 756         }
 757
 758         clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
 759         return 0;
 760 }