1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Low level suspend code for AM43XX SoCs
5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Dave Gerlach, Vaibhav Bedia
9 #include <generated/ti-pm-asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <linux/ti-emif-sram.h>
13 #include <asm/assembler.h>
14 #include <asm/hardware/cache-l2x0.h>
15 #include <asm/memory.h>
20 #include "omap-secure.h"
25 #define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
26 #define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
27 #define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
29 #define AM43XX_EMIF_POWEROFF_ENABLE 0x1
30 #define AM43XX_EMIF_POWEROFF_DISABLE 0x0
32 #define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1
33 #define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 0x3
35 #define AM43XX_CM_BASE 0x44DF0000
37 #define AM43XX_CM_REGADDR(inst, reg) \
38 AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg))
40 #define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
41 AM43XX_CM_MPU_MPU_CDOFFS)
42 #define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \
43 AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET)
44 #define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \
45 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
46 #define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
52 stmfd sp!, {r4 - r11, lr} @ save registers on stack
54 #ifdef CONFIG_CACHE_L2X0
55 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
56 ldr r1, get_l2cache_base
62 * Flush all data from the L1 and L2 data cache before disabling
69 * Clear the SCTLR.C bit to prevent further data cache
70 * allocation. Clearing SCTLR.C would make all the data accesses
71 * strongly ordered and would not hit the cache.
73 mrc p15, 0, r0, c1, c0, 0
74 bic r0, r0, #(1 << 2) @ Disable the C bit
75 mcr p15, 0, r0, c1, c0, 0
80 * Invalidate L1 and L2 data cache.
85 #ifdef CONFIG_CACHE_L2X0
87 * Clean and invalidate the L2 cache.
89 #ifdef CONFIG_PL310_ERRATA_727915
91 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
97 adr r4, am43xx_pm_ro_sram_data
98 ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
101 ldr r0, [r2, #L2X0_AUX_CTRL]
102 str r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
103 ldr r0, [r2, #L310_PREFETCH_CTRL]
104 str r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
107 str r0, [r2, #L2X0_CLEAN_INV_WAY]
109 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
113 #ifdef CONFIG_PL310_ERRATA_727915
115 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
124 str r0, [r2, #L2X0_CACHE_SYNC]
126 ldr r0, [r2, #L2X0_CACHE_SYNC]
131 adr r9, am43xx_emif_sram_table
133 ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
136 ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
140 ldr r1, am43xx_virt_emif_clkctrl
142 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
147 mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
149 bne wait_emif_disable
152 * For the MPU WFI to be registered as an interrupt
153 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
156 ldr r1, am43xx_virt_mpu_clkctrl
158 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
162 * Put MPU CLKDM to SW_SLEEP
164 ldr r1, am43xx_virt_mpu_clkstctrl
165 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
169 * Execute a barrier instruction to ensure that all cache,
170 * TLB and branch predictor maintenance operations issued
177 * Execute a WFI instruction and wait until the
178 * STANDBYWFI output is asserted to indicate that the
179 * CPU is in idle and low power state. CPU can specualatively
180 * prefetch the instructions so add NOPs after WFI. Sixteen
181 * NOPs as per Cortex-A9 pipeline.
202 /* We come here in case of an abort due to a late interrupt */
203 ldr r1, am43xx_virt_mpu_clkstctrl
204 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
207 /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
208 ldr r1, am43xx_virt_mpu_clkctrl
209 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
213 ldr r1, am43xx_virt_emif_clkctrl
214 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
222 * Set SCTLR.C bit to allow data cache allocation
224 mrc p15, 0, r0, c1, c0, 0
225 orr r0, r0, #(1 << 2) @ Enable the C bit
226 mcr p15, 0, r0, c1, c0, 0
229 ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
232 /* Let the suspend code know about the abort */
234 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
235 ENDPROC(am43xx_do_wfi)
238 ENTRY(am43xx_resume_offset)
239 .word . - am43xx_do_wfi
241 ENTRY(am43xx_resume_from_deep_sleep)
242 /* Set MPU CLKSTCTRL to HW AUTO so that CPUidle works properly */
243 ldr r1, am43xx_virt_mpu_clkstctrl
244 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO
247 /* For AM43xx, use EMIF power down until context is restored */
248 ldr r2, am43xx_phys_emif_poweroff
249 mov r1, #AM43XX_EMIF_POWEROFF_ENABLE
253 ldr r1, am43xx_phys_emif_clkctrl
254 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
259 bne wait_emif_enable1
261 adr r9, am43xx_emif_sram_table
263 ldr r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
266 ldr r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
269 ldr r2, am43xx_phys_emif_poweroff
270 mov r1, #AM43XX_EMIF_POWEROFF_DISABLE
273 #ifdef CONFIG_CACHE_L2X0
274 ldr r2, l2_cache_base
275 ldr r0, [r2, #L2X0_CTRL]
278 beq skip_l2en @ Skip if already enabled
280 adr r4, am43xx_pm_ro_sram_data
281 ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET]
282 ldr r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
289 ldr r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
295 /* L2 invalidate on resume */
297 ldr r2, l2_cache_base
298 str r0, [r2, #L2X0_INV_WAY]
300 ldr r0, [r2, #L2X0_INV_WAY]
304 #ifdef CONFIG_PL310_ERRATA_727915
306 mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
312 ldr r2, l2_cache_base
314 str r0, [r2, #L2X0_CACHE_SYNC]
316 ldr r0, [r2, #L2X0_CACHE_SYNC]
327 /* We are back. Branch to the common CPU resume routine */
330 ENDPROC(am43xx_resume_from_deep_sleep)
337 .word cpu_resume - PAGE_OFFSET + 0x80000000
339 .word v7_flush_dcache_all
343 am43xx_phys_emif_poweroff:
344 .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \
345 AM43XX_PRM_EMIF_CTRL_OFFSET)
346 am43xx_virt_mpu_clkstctrl:
347 .word (AM43XX_CM_MPU_CLKSTCTRL)
348 am43xx_virt_mpu_clkctrl:
349 .word (AM43XX_CM_MPU_MPU_CLKCTRL)
350 am43xx_virt_emif_clkctrl:
351 .word (AM43XX_CM_PER_EMIF_CLKCTRL)
352 am43xx_phys_emif_clkctrl:
353 .word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \
354 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
356 #ifdef CONFIG_CACHE_L2X0
357 /* L2 cache related defines for AM437x */
359 .word omap4_get_l2cache_base
361 .word OMAP44XX_L2CACHE_BASE
363 .word OMAP4_MON_L2X0_PREFETCH_INDEX
365 .word OMAP4_MON_L2X0_AUXCTRL_INDEX
367 .word OMAP4_MON_L2X0_CTRL_INDEX
373 /* DDR related defines */
374 ENTRY(am43xx_emif_sram_table)
375 .space EMIF_PM_FUNCTIONS_SIZE
377 ENTRY(am43xx_pm_sram)
379 .word am43xx_do_wfi_sz
380 .word am43xx_resume_offset
381 .word am43xx_emif_sram_table
382 .word am43xx_pm_ro_sram_data
386 ENTRY(am43xx_pm_ro_sram_data)
387 .space AMX3_PM_RO_SRAM_DATA_SIZE
389 ENTRY(am43xx_do_wfi_sz)
390 .word . - am43xx_do_wfi