arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_8250.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/common.h>
  28 #include <plat/board.h>
  29 #include <plat/clock.h>
  30 #include <plat/control.h>
  31
  32 #include "prm.h"
  33 #include "pm.h"
  34 #include "prm-regbits-34xx.h"
  35
  36 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  37 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  38
  39 #define DEFAULT_TIMEOUT (5 * HZ)
  40
  41 struct omap_uart_state {
  42         int num;
  43         int can_sleep;
  44         struct timer_list timer;
  45         u32 timeout;
  46
  47         void __iomem *wk_st;
  48         void __iomem *wk_en;
  49         u32 wk_mask;
  50         u32 padconf;
  51
  52         struct clk *ick;
  53         struct clk *fck;
  54         int clocked;
  55
  56         struct plat_serial8250_port *p;
  57         struct list_head node;
  58         struct platform_device pdev;
  59
  60 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  61         int context_valid;
  62
  63         /* Registers to be saved/restored for OFF-mode */
  64         u16 dll;
  65         u16 dlh;
  66         u16 ier;
  67         u16 sysc;
  68         u16 scr;
  69         u16 wer;
  70 #endif
  71 };
  72
  73 static LIST_HEAD(uart_list);
  74
  75 static struct plat_serial8250_port serial_platform_data0[] = {
  76         {
  77                 .mapbase        = OMAP_UART1_BASE,
  78                 .irq            = 72,
  79                 .flags          = UPF_BOOT_AUTOCONF,
  80                 .iotype         = UPIO_MEM,
  81                 .regshift       = 2,
  82                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  83         }, {
  84                 .flags          = 0
  85         }
  86 };
  87
  88 static struct plat_serial8250_port serial_platform_data1[] = {
  89         {
  90                 .mapbase        = OMAP_UART2_BASE,
  91                 .irq            = 73,
  92                 .flags          = UPF_BOOT_AUTOCONF,
  93                 .iotype         = UPIO_MEM,
  94                 .regshift       = 2,
  95                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  96         }, {
  97                 .flags          = 0
  98         }
  99 };
 100
 101 static struct plat_serial8250_port serial_platform_data2[] = {
 102         {
 103                 .mapbase        = OMAP_UART3_BASE,
 104                 .irq            = 74,
 105                 .flags          = UPF_BOOT_AUTOCONF,
 106                 .iotype         = UPIO_MEM,
 107                 .regshift       = 2,
 108                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 109         }, {
 110                 .flags          = 0
 111         }
 112 };
 113
 114 #ifdef CONFIG_ARCH_OMAP4
 115 static struct plat_serial8250_port serial_platform_data3[] = {
 116         {
 117                 .mapbase        = OMAP_UART4_BASE,
 118                 .irq            = 70,
 119                 .flags          = UPF_BOOT_AUTOCONF,
 120                 .iotype         = UPIO_MEM,
 121                 .regshift       = 2,
 122                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 123         }, {
 124                 .flags          = 0
 125         }
 126 };
 127 #endif
 128 static inline unsigned int __serial_read_reg(struct uart_port *up,
 129                                            int offset)
 130 {
 131         offset <<= up->regshift;
 132         return (unsigned int)__raw_readb(up->membase + offset);
 133 }
 134
 135 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 136                                            int offset)
 137 {
 138         offset <<= up->regshift;
 139         return (unsigned int)__raw_readb(up->membase + offset);
 140 }
 141
 142 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 143                                     int value)
 144 {
 145         offset <<= p->regshift;
 146         __raw_writeb(value, p->membase + offset);
 147 }
 148
 149 /*
 150  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 151  * properly. Note that the TX watermark initialization may not be needed
 152  * once the 8250.c watermark handling code is merged.
 153  */
 154 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 155 {
 156         struct plat_serial8250_port *p = uart->p;
 157
 158         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
 159         serial_write_reg(p, UART_OMAP_SCR, 0x08);
 160         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
 161         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 162 }
 163
 164 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 165
 166 static void omap_uart_save_context(struct omap_uart_state *uart)
 167 {
 168         u16 lcr = 0;
 169         struct plat_serial8250_port *p = uart->p;
 170
 171         if (!enable_off_mode)
 172                 return;
 173
 174         lcr = serial_read_reg(p, UART_LCR);
 175         serial_write_reg(p, UART_LCR, 0xBF);
 176         uart->dll = serial_read_reg(p, UART_DLL);
 177         uart->dlh = serial_read_reg(p, UART_DLM);
 178         serial_write_reg(p, UART_LCR, lcr);
 179         uart->ier = serial_read_reg(p, UART_IER);
 180         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
 181         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
 182         uart->wer = serial_read_reg(p, UART_OMAP_WER);
 183
 184         uart->context_valid = 1;
 185 }
 186
 187 static void omap_uart_restore_context(struct omap_uart_state *uart)
 188 {
 189         u16 efr = 0;
 190         struct plat_serial8250_port *p = uart->p;
 191
 192         if (!enable_off_mode)
 193                 return;
 194
 195         if (!uart->context_valid)
 196                 return;
 197
 198         uart->context_valid = 0;
 199
 200         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
 201         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 202         efr = serial_read_reg(p, UART_EFR);
 203         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
 204         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 205         serial_write_reg(p, UART_IER, 0x0);
 206         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 207         serial_write_reg(p, UART_DLL, uart->dll);
 208         serial_write_reg(p, UART_DLM, uart->dlh);
 209         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 210         serial_write_reg(p, UART_IER, uart->ier);
 211         serial_write_reg(p, UART_FCR, 0xA1);
 212         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 213         serial_write_reg(p, UART_EFR, efr);
 214         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
 215         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
 216         serial_write_reg(p, UART_OMAP_WER, uart->wer);
 217         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
 218         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 219 }
 220 #else
 221 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 222 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 223 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 224
 225 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 226 {
 227         if (uart->clocked)
 228                 return;
 229
 230         clk_enable(uart->ick);
 231         clk_enable(uart->fck);
 232         uart->clocked = 1;
 233         omap_uart_restore_context(uart);
 234 }
 235
 236 #ifdef CONFIG_PM
 237
 238 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 239 {
 240         if (!uart->clocked)
 241                 return;
 242
 243         omap_uart_save_context(uart);
 244         uart->clocked = 0;
 245         clk_disable(uart->ick);
 246         clk_disable(uart->fck);
 247 }
 248
 249 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 250 {
 251         /* Set wake-enable bit */
 252         if (uart->wk_en && uart->wk_mask) {
 253                 u32 v = __raw_readl(uart->wk_en);
 254                 v |= uart->wk_mask;
 255                 __raw_writel(v, uart->wk_en);
 256         }
 257
 258         /* Ensure IOPAD wake-enables are set */
 259         if (cpu_is_omap34xx() && uart->padconf) {
 260                 u16 v = omap_ctrl_readw(uart->padconf);
 261                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 262                 omap_ctrl_writew(v, uart->padconf);
 263         }
 264 }
 265
 266 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 267 {
 268         /* Clear wake-enable bit */
 269         if (uart->wk_en && uart->wk_mask) {
 270                 u32 v = __raw_readl(uart->wk_en);
 271                 v &= ~uart->wk_mask;
 272                 __raw_writel(v, uart->wk_en);
 273         }
 274
 275         /* Ensure IOPAD wake-enables are cleared */
 276         if (cpu_is_omap34xx() && uart->padconf) {
 277                 u16 v = omap_ctrl_readw(uart->padconf);
 278                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 279                 omap_ctrl_writew(v, uart->padconf);
 280         }
 281 }
 282
 283 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 284                                           int enable)
 285 {
 286         struct plat_serial8250_port *p = uart->p;
 287         u16 sysc;
 288
 289         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
 290         if (enable)
 291                 sysc |= 0x2 << 3;
 292         else
 293                 sysc |= 0x1 << 3;
 294
 295         serial_write_reg(p, UART_OMAP_SYSC, sysc);
 296 }
 297
 298 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 299 {
 300         omap_uart_enable_clocks(uart);
 301
 302         omap_uart_smart_idle_enable(uart, 0);
 303         uart->can_sleep = 0;
 304         if (uart->timeout)
 305                 mod_timer(&uart->timer, jiffies + uart->timeout);
 306         else
 307                 del_timer(&uart->timer);
 308 }
 309
 310 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 311 {
 312         if (device_may_wakeup(&uart->pdev.dev))
 313                 omap_uart_enable_wakeup(uart);
 314         else
 315                 omap_uart_disable_wakeup(uart);
 316
 317         if (!uart->clocked)
 318                 return;
 319
 320         omap_uart_smart_idle_enable(uart, 1);
 321         uart->can_sleep = 1;
 322         del_timer(&uart->timer);
 323 }
 324
 325 static void omap_uart_idle_timer(unsigned long data)
 326 {
 327         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 328
 329         omap_uart_allow_sleep(uart);
 330 }
 331
 332 void omap_uart_prepare_idle(int num)
 333 {
 334         struct omap_uart_state *uart;
 335
 336         list_for_each_entry(uart, &uart_list, node) {
 337                 if (num == uart->num && uart->can_sleep) {
 338                         omap_uart_disable_clocks(uart);
 339                         return;
 340                 }
 341         }
 342 }
 343
 344 void omap_uart_resume_idle(int num)
 345 {
 346         struct omap_uart_state *uart;
 347
 348         list_for_each_entry(uart, &uart_list, node) {
 349                 if (num == uart->num) {
 350                         omap_uart_enable_clocks(uart);
 351
 352                         /* Check for IO pad wakeup */
 353                         if (cpu_is_omap34xx() && uart->padconf) {
 354                                 u16 p = omap_ctrl_readw(uart->padconf);
 355
 356                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 357                                         omap_uart_block_sleep(uart);
 358                         }
 359
 360                         /* Check for normal UART wakeup */
 361                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 362                                 omap_uart_block_sleep(uart);
 363                         return;
 364                 }
 365         }
 366 }
 367
 368 void omap_uart_prepare_suspend(void)
 369 {
 370         struct omap_uart_state *uart;
 371
 372         list_for_each_entry(uart, &uart_list, node) {
 373                 omap_uart_allow_sleep(uart);
 374         }
 375 }
 376
 377 int omap_uart_can_sleep(void)
 378 {
 379         struct omap_uart_state *uart;
 380         int can_sleep = 1;
 381
 382         list_for_each_entry(uart, &uart_list, node) {
 383                 if (!uart->clocked)
 384                         continue;
 385
 386                 if (!uart->can_sleep) {
 387                         can_sleep = 0;
 388                         continue;
 389                 }
 390
 391                 /* This UART can now safely sleep. */
 392                 omap_uart_allow_sleep(uart);
 393         }
 394
 395         return can_sleep;
 396 }
 397
 398 /**
 399  * omap_uart_interrupt()
 400  *
 401  * This handler is used only to detect that *any* UART interrupt has
 402  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 403  * any UART interrupt will trigger the inactivity timer so the
 404  * UART will not idle or sleep for its timeout period.
 405  *
 406  **/
 407 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 408 {
 409         struct omap_uart_state *uart = dev_id;
 410
 411         omap_uart_block_sleep(uart);
 412
 413         return IRQ_NONE;
 414 }
 415
 416 static void omap_uart_idle_init(struct omap_uart_state *uart)
 417 {
 418         struct plat_serial8250_port *p = uart->p;
 419         int ret;
 420
 421         uart->can_sleep = 0;
 422         uart->timeout = DEFAULT_TIMEOUT;
 423         setup_timer(&uart->timer, omap_uart_idle_timer,
 424                     (unsigned long) uart);
 425         mod_timer(&uart->timer, jiffies + uart->timeout);
 426         omap_uart_smart_idle_enable(uart, 0);
 427
 428         if (cpu_is_omap34xx()) {
 429                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
 430                 u32 wk_mask = 0;
 431                 u32 padconf = 0;
 432
 433                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 434                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 435                 switch (uart->num) {
 436                 case 0:
 437                         wk_mask = OMAP3430_ST_UART1_MASK;
 438                         padconf = 0x182;
 439                         break;
 440                 case 1:
 441                         wk_mask = OMAP3430_ST_UART2_MASK;
 442                         padconf = 0x17a;
 443                         break;
 444                 case 2:
 445                         wk_mask = OMAP3430_ST_UART3_MASK;
 446                         padconf = 0x19e;
 447                         break;
 448                 }
 449                 uart->wk_mask = wk_mask;
 450                 uart->padconf = padconf;
 451         } else if (cpu_is_omap24xx()) {
 452                 u32 wk_mask = 0;
 453
 454                 if (cpu_is_omap2430()) {
 455                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 456                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
 457                 } else if (cpu_is_omap2420()) {
 458                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 459                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
 460                 }
 461                 switch (uart->num) {
 462                 case 0:
 463                         wk_mask = OMAP24XX_ST_UART1_MASK;
 464                         break;
 465                 case 1:
 466                         wk_mask = OMAP24XX_ST_UART2_MASK;
 467                         break;
 468                 case 2:
 469                         wk_mask = OMAP24XX_ST_UART3_MASK;
 470                         break;
 471                 }
 472                 uart->wk_mask = wk_mask;
 473         } else {
 474                 uart->wk_en = 0;
 475                 uart->wk_st = 0;
 476                 uart->wk_mask = 0;
 477                 uart->padconf = 0;
 478         }
 479
 480         p->irqflags |= IRQF_SHARED;
 481         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
 482                           "serial idle", (void *)uart);
 483         WARN_ON(ret);
 484 }
 485
 486 void omap_uart_enable_irqs(int enable)
 487 {
 488         int ret;
 489         struct omap_uart_state *uart;
 490
 491         list_for_each_entry(uart, &uart_list, node) {
 492                 if (enable)
 493                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
 494                                 IRQF_SHARED, "serial idle", (void *)uart);
 495                 else
 496                         free_irq(uart->p->irq, (void *)uart);
 497         }
 498 }
 499
 500 static ssize_t sleep_timeout_show(struct device *dev,
 501                                   struct device_attribute *attr,
 502                                   char *buf)
 503 {
 504         struct platform_device *pdev = container_of(dev,
 505                                         struct platform_device, dev);
 506         struct omap_uart_state *uart = container_of(pdev,
 507                                         struct omap_uart_state, pdev);
 508
 509         return sprintf(buf, "%u\n", uart->timeout / HZ);
 510 }
 511
 512 static ssize_t sleep_timeout_store(struct device *dev,
 513                                    struct device_attribute *attr,
 514                                    const char *buf, size_t n)
 515 {
 516         struct platform_device *pdev = container_of(dev,
 517                                         struct platform_device, dev);
 518         struct omap_uart_state *uart = container_of(pdev,
 519                                         struct omap_uart_state, pdev);
 520         unsigned int value;
 521
 522         if (sscanf(buf, "%u", &value) != 1) {
 523                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
 524                 return -EINVAL;
 525         }
 526
 527         uart->timeout = value * HZ;
 528         if (uart->timeout)
 529                 mod_timer(&uart->timer, jiffies + uart->timeout);
 530         else
 531                 /* A zero value means disable timeout feature */
 532                 omap_uart_block_sleep(uart);
 533
 534         return n;
 535 }
 536
 537 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
 538 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 539 #else
 540 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 541 #define DEV_CREATE_FILE(dev, attr)
 542 #endif /* CONFIG_PM */
 543
 544 static struct omap_uart_state omap_uart[] = {
 545         {
 546                 .pdev = {
 547                         .name                   = "serial8250",
 548                         .id                     = PLAT8250_DEV_PLATFORM,
 549                         .dev                    = {
 550                                 .platform_data  = serial_platform_data0,
 551                         },
 552                 },
 553         }, {
 554                 .pdev = {
 555                         .name                   = "serial8250",
 556                         .id                     = PLAT8250_DEV_PLATFORM1,
 557                         .dev                    = {
 558                                 .platform_data  = serial_platform_data1,
 559                         },
 560                 },
 561         }, {
 562                 .pdev = {
 563                         .name                   = "serial8250",
 564                         .id                     = PLAT8250_DEV_PLATFORM2,
 565                         .dev                    = {
 566                                 .platform_data  = serial_platform_data2,
 567                         },
 568                 },
 569         },
 570 #ifdef CONFIG_ARCH_OMAP4
 571         {
 572                 .pdev = {
 573                         .name                   = "serial8250",
 574                         .id                     = 3,
 575                         .dev                    = {
 576                                 .platform_data  = serial_platform_data3,
 577                         },
 578                 },
 579         },
 580 #endif
 581 };
 582
 583 /*
 584  * Override the default 8250 read handler: mem_serial_in()
 585  * Empty RX fifo read causes an abort on omap3630 and omap4
 586  * This function makes sure that an empty rx fifo is not read on these silicons
 587  * (OMAP1/2/3430 are not affected)
 588  */
 589 static unsigned int serial_in_override(struct uart_port *up, int offset)
 590 {
 591         if (UART_RX == offset) {
 592                 unsigned int lsr;
 593                 lsr = __serial_read_reg(up, UART_LSR);
 594                 if (!(lsr & UART_LSR_DR))
 595                         return -EPERM;
 596         }
 597
 598         return __serial_read_reg(up, offset);
 599 }
 600
 601 void __init omap_serial_early_init(void)
 602 {
 603         int i;
 604         char name[16];
 605
 606         /*
 607          * Make sure the serial ports are muxed on at this point.
 608          * You have to mux them off in device drivers later on
 609          * if not needed.
 610          */
 611
 612         for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
 613                 struct omap_uart_state *uart = &omap_uart[i];
 614                 struct platform_device *pdev = &uart->pdev;
 615                 struct device *dev = &pdev->dev;
 616                 struct plat_serial8250_port *p = dev->platform_data;
 617
 618                 /*
 619                  * Module 4KB + L4 interconnect 4KB
 620                  * Static mapping, never released
 621                  */
 622                 p->membase = ioremap(p->mapbase, SZ_8K);
 623                 if (!p->membase) {
 624                         printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
 625                         continue;
 626                 }
 627
 628                 sprintf(name, "uart%d_ick", i+1);
 629                 uart->ick = clk_get(NULL, name);
 630                 if (IS_ERR(uart->ick)) {
 631                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
 632                         uart->ick = NULL;
 633                 }
 634
 635                 sprintf(name, "uart%d_fck", i+1);
 636                 uart->fck = clk_get(NULL, name);
 637                 if (IS_ERR(uart->fck)) {
 638                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
 639                         uart->fck = NULL;
 640                 }
 641
 642                 /* FIXME: Remove this once the clkdev is ready */
 643                 if (!cpu_is_omap44xx()) {
 644                         if (!uart->ick || !uart->fck)
 645                                 continue;
 646                 }
 647
 648                 uart->num = i;
 649                 p->private_data = uart;
 650                 uart->p = p;
 651
 652                 if (cpu_is_omap44xx())
 653                         p->irq += 32;
 654         }
 655 }
 656
 657 /**
 658  * omap_serial_init_port() - initialize single serial port
 659  * @port: serial port number (0-3)
 660  *
 661  * This function initialies serial driver for given @port only.
 662  * Platforms can call this function instead of omap_serial_init()
 663  * if they don't plan to use all available UARTs as serial ports.
 664  *
 665  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 666  * use only one of the two.
 667  */
 668 void __init omap_serial_init_port(int port)
 669 {
 670         struct omap_uart_state *uart;
 671         struct platform_device *pdev;
 672         struct device *dev;
 673
 674         BUG_ON(port < 0);
 675         BUG_ON(port >= ARRAY_SIZE(omap_uart));
 676
 677         uart = &omap_uart[port];
 678         pdev = &uart->pdev;
 679         dev = &pdev->dev;
 680
 681         omap_uart_enable_clocks(uart);
 682
 683         omap_uart_reset(uart);
 684         omap_uart_idle_init(uart);
 685
 686         list_add_tail(&uart->node, &uart_list);
 687
 688         if (WARN_ON(platform_device_register(pdev)))
 689                 return;
 690
 691         if ((cpu_is_omap34xx() && uart->padconf) ||
 692             (uart->wk_en && uart->wk_mask)) {
 693                 device_init_wakeup(dev, true);
 694                 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
 695         }
 696
 697                 /* omap44xx: Never read empty UART fifo
 698                  * omap3xxx: Never read empty UART fifo on UARTs
 699                  * with IP rev >=0x52
 700                  */
 701                 if (cpu_is_omap44xx())
 702                         uart->p->serial_in = serial_in_override;
 703                 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
 704                                 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 705                         uart->p->serial_in = serial_in_override;
 706 }
 707
 708 /**
 709  * omap_serial_init() - intialize all supported serial ports
 710  *
 711  * Initializes all available UARTs as serial ports. Platforms
 712  * can call this function when they want to have default behaviour
 713  * for serial ports (e.g initialize them all as serial ports).
 714  */
 715 void __init omap_serial_init(void)
 716 {
 717         int i;
 718
 719         for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
 720                 omap_serial_init_port(i);
 721 }